1854 lines · cpp
1//===------ SemaRISCV.cpp ------- RISC-V target-specific routines ---------===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file implements semantic analysis functions specific to RISC-V.10//11//===----------------------------------------------------------------------===//12 13#include "clang/Sema/SemaRISCV.h"14#include "clang/AST/ASTContext.h"15#include "clang/AST/Attr.h"16#include "clang/AST/Attrs.inc"17#include "clang/AST/Decl.h"18#include "clang/Basic/Builtins.h"19#include "clang/Basic/TargetBuiltins.h"20#include "clang/Basic/TargetInfo.h"21#include "clang/Lex/Preprocessor.h"22#include "clang/Sema/Attr.h"23#include "clang/Sema/Initialization.h"24#include "clang/Sema/Lookup.h"25#include "clang/Sema/ParsedAttr.h"26#include "clang/Sema/RISCVIntrinsicManager.h"27#include "clang/Sema/Sema.h"28#include "clang/Support/RISCVVIntrinsicUtils.h"29#include "llvm/ADT/SmallVector.h"30#include "llvm/TargetParser/RISCVISAInfo.h"31#include "llvm/TargetParser/RISCVTargetParser.h"32#include <optional>33#include <string>34#include <vector>35 36using namespace llvm;37using namespace clang;38using namespace clang::RISCV;39 40using IntrinsicKind = sema::RISCVIntrinsicManager::IntrinsicKind;41 42namespace {43 44// Function definition of a RVV intrinsic.45struct RVVIntrinsicDef {46 /// Mapping to which clang built-in function, e.g. __builtin_rvv_vadd.47 std::string BuiltinName;48 49 /// Mapping to RequiredFeatures in riscv_vector.td50 StringRef RequiredExtensions;51 52 /// Function signature, first element is return type.53 RVVTypes Signature;54};55 56struct RVVOverloadIntrinsicDef {57 // Indexes of RISCVIntrinsicManagerImpl::IntrinsicList.58 SmallVector<uint32_t, 8> Indexes;59};60 61} // namespace62 63static const PrototypeDescriptor RVVSignatureTable[] = {64#define DECL_SIGNATURE_TABLE65#include "clang/Basic/riscv_vector_builtin_sema.inc"66#undef DECL_SIGNATURE_TABLE67};68 69static const PrototypeDescriptor RVSiFiveVectorSignatureTable[] = {70#define DECL_SIGNATURE_TABLE71#include "clang/Basic/riscv_sifive_vector_builtin_sema.inc"72#undef DECL_SIGNATURE_TABLE73};74 75static const PrototypeDescriptor RVAndesVectorSignatureTable[] = {76#define DECL_SIGNATURE_TABLE77#include "clang/Basic/riscv_andes_vector_builtin_sema.inc"78#undef DECL_SIGNATURE_TABLE79};80 81static const RVVIntrinsicRecord RVVIntrinsicRecords[] = {82#define DECL_INTRINSIC_RECORDS83#include "clang/Basic/riscv_vector_builtin_sema.inc"84#undef DECL_INTRINSIC_RECORDS85};86 87static const RVVIntrinsicRecord RVSiFiveVectorIntrinsicRecords[] = {88#define DECL_INTRINSIC_RECORDS89#include "clang/Basic/riscv_sifive_vector_builtin_sema.inc"90#undef DECL_INTRINSIC_RECORDS91};92 93static const RVVIntrinsicRecord RVAndesVectorIntrinsicRecords[] = {94#define DECL_INTRINSIC_RECORDS95#include "clang/Basic/riscv_andes_vector_builtin_sema.inc"96#undef DECL_INTRINSIC_RECORDS97};98 99// Get subsequence of signature table.100static ArrayRef<PrototypeDescriptor>101ProtoSeq2ArrayRef(IntrinsicKind K, uint16_t Index, uint8_t Length) {102 switch (K) {103 case IntrinsicKind::RVV:104 return ArrayRef(&RVVSignatureTable[Index], Length);105 case IntrinsicKind::SIFIVE_VECTOR:106 return ArrayRef(&RVSiFiveVectorSignatureTable[Index], Length);107 case IntrinsicKind::ANDES_VECTOR:108 return ArrayRef(&RVAndesVectorSignatureTable[Index], Length);109 }110 llvm_unreachable("Unhandled IntrinsicKind");111}112 113static QualType RVVType2Qual(ASTContext &Context, const RVVType *Type) {114 QualType QT;115 switch (Type->getScalarType()) {116 case ScalarTypeKind::Void:117 QT = Context.VoidTy;118 break;119 case ScalarTypeKind::Size_t:120 QT = Context.getSizeType();121 break;122 case ScalarTypeKind::Ptrdiff_t:123 QT = Context.getPointerDiffType();124 break;125 case ScalarTypeKind::UnsignedLong:126 QT = Context.UnsignedLongTy;127 break;128 case ScalarTypeKind::SignedLong:129 QT = Context.LongTy;130 break;131 case ScalarTypeKind::Boolean:132 QT = Context.BoolTy;133 break;134 case ScalarTypeKind::SignedInteger:135 QT = Context.getIntTypeForBitwidth(Type->getElementBitwidth(), true);136 break;137 case ScalarTypeKind::UnsignedInteger:138 QT = Context.getIntTypeForBitwidth(Type->getElementBitwidth(), false);139 break;140 case ScalarTypeKind::BFloat:141 QT = Context.BFloat16Ty;142 break;143 case ScalarTypeKind::Float:144 switch (Type->getElementBitwidth()) {145 case 64:146 QT = Context.DoubleTy;147 break;148 case 32:149 QT = Context.FloatTy;150 break;151 case 16:152 QT = Context.Float16Ty;153 break;154 default:155 llvm_unreachable("Unsupported floating point width.");156 }157 break;158 case Invalid:159 case Undefined:160 llvm_unreachable("Unhandled type.");161 }162 if (Type->isVector()) {163 if (Type->isTuple())164 QT = Context.getScalableVectorType(QT, *Type->getScale(), Type->getNF());165 else166 QT = Context.getScalableVectorType(QT, *Type->getScale());167 }168 169 if (Type->isConstant())170 QT = Context.getConstType(QT);171 172 // Transform the type to a pointer as the last step, if necessary.173 if (Type->isPointer())174 QT = Context.getPointerType(QT);175 176 return QT;177}178 179namespace {180class RISCVIntrinsicManagerImpl : public sema::RISCVIntrinsicManager {181private:182 Sema &S;183 RVVTypeCache TypeCache;184 bool ConstructedRISCVVBuiltins;185 bool ConstructedRISCVSiFiveVectorBuiltins;186 bool ConstructedRISCVAndesVectorBuiltins;187 188 // List of all RVV intrinsic.189 std::vector<RVVIntrinsicDef> IntrinsicList;190 // Mapping function name to index of IntrinsicList.191 StringMap<uint32_t> Intrinsics;192 // Mapping function name to RVVOverloadIntrinsicDef.193 StringMap<RVVOverloadIntrinsicDef> OverloadIntrinsics;194 195 // Create RVVIntrinsicDef.196 void InitRVVIntrinsic(const RVVIntrinsicRecord &Record, StringRef SuffixStr,197 StringRef OverloadedSuffixStr, bool IsMask,198 RVVTypes &Types, bool HasPolicy, Policy PolicyAttrs);199 200 // Create FunctionDecl for a vector intrinsic.201 void CreateRVVIntrinsicDecl(LookupResult &LR, IdentifierInfo *II,202 Preprocessor &PP, uint32_t Index,203 bool IsOverload);204 205 void ConstructRVVIntrinsics(ArrayRef<RVVIntrinsicRecord> Recs,206 IntrinsicKind K);207 208public:209 RISCVIntrinsicManagerImpl(clang::Sema &S) : S(S) {210 ConstructedRISCVVBuiltins = false;211 ConstructedRISCVSiFiveVectorBuiltins = false;212 ConstructedRISCVAndesVectorBuiltins = false;213 }214 215 // Initialize IntrinsicList216 void InitIntrinsicList() override;217 218 // Create RISC-V vector intrinsic and insert into symbol table if found, and219 // return true, otherwise return false.220 bool CreateIntrinsicIfFound(LookupResult &LR, IdentifierInfo *II,221 Preprocessor &PP) override;222};223} // namespace224 225void RISCVIntrinsicManagerImpl::ConstructRVVIntrinsics(226 ArrayRef<RVVIntrinsicRecord> Recs, IntrinsicKind K) {227 // Construction of RVVIntrinsicRecords need to sync with createRVVIntrinsics228 // in RISCVVEmitter.cpp.229 for (auto &Record : Recs) {230 // Create Intrinsics for each type and LMUL.231 BasicType BaseType = BasicType::Unknown;232 ArrayRef<PrototypeDescriptor> BasicProtoSeq =233 ProtoSeq2ArrayRef(K, Record.PrototypeIndex, Record.PrototypeLength);234 ArrayRef<PrototypeDescriptor> SuffixProto =235 ProtoSeq2ArrayRef(K, Record.SuffixIndex, Record.SuffixLength);236 ArrayRef<PrototypeDescriptor> OverloadedSuffixProto = ProtoSeq2ArrayRef(237 K, Record.OverloadedSuffixIndex, Record.OverloadedSuffixSize);238 239 PolicyScheme UnMaskedPolicyScheme =240 static_cast<PolicyScheme>(Record.UnMaskedPolicyScheme);241 PolicyScheme MaskedPolicyScheme =242 static_cast<PolicyScheme>(Record.MaskedPolicyScheme);243 244 const Policy DefaultPolicy;245 246 llvm::SmallVector<PrototypeDescriptor> ProtoSeq =247 RVVIntrinsic::computeBuiltinTypes(248 BasicProtoSeq, /*IsMasked=*/false,249 /*HasMaskedOffOperand=*/false, Record.HasVL, Record.NF,250 UnMaskedPolicyScheme, DefaultPolicy, Record.IsTuple);251 252 llvm::SmallVector<PrototypeDescriptor> ProtoMaskSeq;253 if (Record.HasMasked)254 ProtoMaskSeq = RVVIntrinsic::computeBuiltinTypes(255 BasicProtoSeq, /*IsMasked=*/true, Record.HasMaskedOffOperand,256 Record.HasVL, Record.NF, MaskedPolicyScheme, DefaultPolicy,257 Record.IsTuple);258 259 bool UnMaskedHasPolicy = UnMaskedPolicyScheme != PolicyScheme::SchemeNone;260 bool MaskedHasPolicy = MaskedPolicyScheme != PolicyScheme::SchemeNone;261 SmallVector<Policy> SupportedUnMaskedPolicies =262 RVVIntrinsic::getSupportedUnMaskedPolicies();263 SmallVector<Policy> SupportedMaskedPolicies =264 RVVIntrinsic::getSupportedMaskedPolicies(Record.HasTailPolicy,265 Record.HasMaskPolicy);266 267 for (unsigned int TypeRangeMaskShift = 0;268 TypeRangeMaskShift <= static_cast<unsigned int>(BasicType::MaxOffset);269 ++TypeRangeMaskShift) {270 unsigned int BaseTypeI = 1 << TypeRangeMaskShift;271 BaseType = static_cast<BasicType>(BaseTypeI);272 273 if ((BaseTypeI & Record.TypeRangeMask) != BaseTypeI)274 continue;275 276 // Expanded with different LMUL.277 for (int Log2LMUL = -3; Log2LMUL <= 3; Log2LMUL++) {278 if (!(Record.Log2LMULMask & (1 << (Log2LMUL + 3))))279 continue;280 281 std::optional<RVVTypes> Types =282 TypeCache.computeTypes(BaseType, Log2LMUL, Record.NF, ProtoSeq);283 284 // Ignored to create new intrinsic if there are any illegal types.285 if (!Types.has_value())286 continue;287 288 std::string SuffixStr = RVVIntrinsic::getSuffixStr(289 TypeCache, BaseType, Log2LMUL, SuffixProto);290 std::string OverloadedSuffixStr = RVVIntrinsic::getSuffixStr(291 TypeCache, BaseType, Log2LMUL, OverloadedSuffixProto);292 293 // Create non-masked intrinsic.294 InitRVVIntrinsic(Record, SuffixStr, OverloadedSuffixStr, false, *Types,295 UnMaskedHasPolicy, DefaultPolicy);296 297 // Create non-masked policy intrinsic.298 if (Record.UnMaskedPolicyScheme != PolicyScheme::SchemeNone) {299 for (auto P : SupportedUnMaskedPolicies) {300 llvm::SmallVector<PrototypeDescriptor> PolicyPrototype =301 RVVIntrinsic::computeBuiltinTypes(302 BasicProtoSeq, /*IsMasked=*/false,303 /*HasMaskedOffOperand=*/false, Record.HasVL, Record.NF,304 UnMaskedPolicyScheme, P, Record.IsTuple);305 std::optional<RVVTypes> PolicyTypes = TypeCache.computeTypes(306 BaseType, Log2LMUL, Record.NF, PolicyPrototype);307 InitRVVIntrinsic(Record, SuffixStr, OverloadedSuffixStr,308 /*IsMask=*/false, *PolicyTypes, UnMaskedHasPolicy,309 P);310 }311 }312 if (!Record.HasMasked)313 continue;314 // Create masked intrinsic.315 std::optional<RVVTypes> MaskTypes =316 TypeCache.computeTypes(BaseType, Log2LMUL, Record.NF, ProtoMaskSeq);317 InitRVVIntrinsic(Record, SuffixStr, OverloadedSuffixStr, true,318 *MaskTypes, MaskedHasPolicy, DefaultPolicy);319 if (Record.MaskedPolicyScheme == PolicyScheme::SchemeNone)320 continue;321 // Create masked policy intrinsic.322 for (auto P : SupportedMaskedPolicies) {323 llvm::SmallVector<PrototypeDescriptor> PolicyPrototype =324 RVVIntrinsic::computeBuiltinTypes(325 BasicProtoSeq, /*IsMasked=*/true, Record.HasMaskedOffOperand,326 Record.HasVL, Record.NF, MaskedPolicyScheme, P,327 Record.IsTuple);328 std::optional<RVVTypes> PolicyTypes = TypeCache.computeTypes(329 BaseType, Log2LMUL, Record.NF, PolicyPrototype);330 InitRVVIntrinsic(Record, SuffixStr, OverloadedSuffixStr,331 /*IsMask=*/true, *PolicyTypes, MaskedHasPolicy, P);332 }333 } // End for different LMUL334 } // End for different TypeRange335 }336}337 338void RISCVIntrinsicManagerImpl::InitIntrinsicList() {339 340 if (S.RISCV().DeclareRVVBuiltins && !ConstructedRISCVVBuiltins) {341 ConstructedRISCVVBuiltins = true;342 ConstructRVVIntrinsics(RVVIntrinsicRecords, IntrinsicKind::RVV);343 }344 if (S.RISCV().DeclareSiFiveVectorBuiltins &&345 !ConstructedRISCVSiFiveVectorBuiltins) {346 ConstructedRISCVSiFiveVectorBuiltins = true;347 ConstructRVVIntrinsics(RVSiFiveVectorIntrinsicRecords,348 IntrinsicKind::SIFIVE_VECTOR);349 }350 if (S.RISCV().DeclareAndesVectorBuiltins &&351 !ConstructedRISCVAndesVectorBuiltins) {352 ConstructedRISCVAndesVectorBuiltins = true;353 ConstructRVVIntrinsics(RVAndesVectorIntrinsicRecords,354 IntrinsicKind::ANDES_VECTOR);355 }356}357 358// Compute name and signatures for intrinsic with practical types.359void RISCVIntrinsicManagerImpl::InitRVVIntrinsic(360 const RVVIntrinsicRecord &Record, StringRef SuffixStr,361 StringRef OverloadedSuffixStr, bool IsMasked, RVVTypes &Signature,362 bool HasPolicy, Policy PolicyAttrs) {363 // Function name, e.g. vadd_vv_i32m1.364 std::string Name = Record.Name;365 if (!SuffixStr.empty())366 Name += "_" + SuffixStr.str();367 368 // Overloaded function name, e.g. vadd.369 std::string OverloadedName;370 if (!Record.OverloadedName)371 OverloadedName = StringRef(Record.Name).split("_").first.str();372 else373 OverloadedName = Record.OverloadedName;374 if (!OverloadedSuffixStr.empty())375 OverloadedName += "_" + OverloadedSuffixStr.str();376 377 // clang built-in function name, e.g. __builtin_rvv_vadd.378 std::string BuiltinName = std::string(Record.Name);379 380 RVVIntrinsic::updateNamesAndPolicy(IsMasked, HasPolicy, Name, BuiltinName,381 OverloadedName, PolicyAttrs,382 Record.HasFRMRoundModeOp);383 384 // Put into IntrinsicList.385 uint32_t Index = IntrinsicList.size();386 assert(IntrinsicList.size() == (size_t)Index &&387 "Intrinsics indices overflow.");388 IntrinsicList.push_back({BuiltinName, Record.RequiredExtensions, Signature});389 390 // Creating mapping to Intrinsics.391 Intrinsics.insert({Name, Index});392 393 // Get the RVVOverloadIntrinsicDef.394 RVVOverloadIntrinsicDef &OverloadIntrinsicDef =395 OverloadIntrinsics[OverloadedName];396 397 // And added the index.398 OverloadIntrinsicDef.Indexes.push_back(Index);399}400 401void RISCVIntrinsicManagerImpl::CreateRVVIntrinsicDecl(LookupResult &LR,402 IdentifierInfo *II,403 Preprocessor &PP,404 uint32_t Index,405 bool IsOverload) {406 ASTContext &Context = S.Context;407 RVVIntrinsicDef &IDef = IntrinsicList[Index];408 RVVTypes Sigs = IDef.Signature;409 size_t SigLength = Sigs.size();410 RVVType *ReturnType = Sigs[0];411 QualType RetType = RVVType2Qual(Context, ReturnType);412 SmallVector<QualType, 8> ArgTypes;413 QualType BuiltinFuncType;414 415 // Skip return type, and convert RVVType to QualType for arguments.416 for (size_t i = 1; i < SigLength; ++i)417 ArgTypes.push_back(RVVType2Qual(Context, Sigs[i]));418 419 FunctionProtoType::ExtProtoInfo PI(420 Context.getTargetInfo().getDefaultCallingConv());421 422 PI.Variadic = false;423 424 SourceLocation Loc = LR.getNameLoc();425 BuiltinFuncType = Context.getFunctionType(RetType, ArgTypes, PI);426 DeclContext *Parent = Context.getTranslationUnitDecl();427 428 FunctionDecl *RVVIntrinsicDecl = FunctionDecl::Create(429 Context, Parent, Loc, Loc, II, BuiltinFuncType, /*TInfo=*/nullptr,430 SC_Extern, S.getCurFPFeatures().isFPConstrained(),431 /*isInlineSpecified*/ false,432 /*hasWrittenPrototype*/ true);433 434 // Create Decl objects for each parameter, adding them to the435 // FunctionDecl.436 const auto *FP = cast<FunctionProtoType>(BuiltinFuncType);437 SmallVector<ParmVarDecl *, 8> ParmList;438 for (unsigned IParm = 0, E = FP->getNumParams(); IParm != E; ++IParm) {439 ParmVarDecl *Parm =440 ParmVarDecl::Create(Context, RVVIntrinsicDecl, Loc, Loc, nullptr,441 FP->getParamType(IParm), nullptr, SC_None, nullptr);442 Parm->setScopeInfo(0, IParm);443 ParmList.push_back(Parm);444 }445 RVVIntrinsicDecl->setParams(ParmList);446 447 // Add function attributes.448 if (IsOverload)449 RVVIntrinsicDecl->addAttr(OverloadableAttr::CreateImplicit(Context));450 451 if (IDef.RequiredExtensions != "")452 RVVIntrinsicDecl->addAttr(453 TargetAttr::CreateImplicit(Context, IDef.RequiredExtensions));454 // Setup alias to __builtin_rvv_*455 IdentifierInfo &IntrinsicII =456 PP.getIdentifierTable().get("__builtin_rvv_" + IDef.BuiltinName);457 RVVIntrinsicDecl->addAttr(458 BuiltinAliasAttr::CreateImplicit(S.Context, &IntrinsicII));459 460 // Add to symbol table.461 LR.addDecl(RVVIntrinsicDecl);462}463 464bool RISCVIntrinsicManagerImpl::CreateIntrinsicIfFound(LookupResult &LR,465 IdentifierInfo *II,466 Preprocessor &PP) {467 StringRef Name = II->getName();468 if (!Name.consume_front("__riscv_"))469 return false;470 471 // Lookup the function name from the overload intrinsics first.472 auto OvIItr = OverloadIntrinsics.find(Name);473 if (OvIItr != OverloadIntrinsics.end()) {474 const RVVOverloadIntrinsicDef &OvIntrinsicDef = OvIItr->second;475 for (auto Index : OvIntrinsicDef.Indexes)476 CreateRVVIntrinsicDecl(LR, II, PP, Index,477 /*IsOverload*/ true);478 479 // If we added overloads, need to resolve the lookup result.480 LR.resolveKind();481 return true;482 }483 484 // Lookup the function name from the intrinsics.485 auto Itr = Intrinsics.find(Name);486 if (Itr != Intrinsics.end()) {487 CreateRVVIntrinsicDecl(LR, II, PP, Itr->second,488 /*IsOverload*/ false);489 return true;490 }491 492 // It's not an RVV intrinsics.493 return false;494}495 496namespace clang {497std::unique_ptr<clang::sema::RISCVIntrinsicManager>498CreateRISCVIntrinsicManager(Sema &S) {499 return std::make_unique<RISCVIntrinsicManagerImpl>(S);500}501 502bool SemaRISCV::CheckLMUL(CallExpr *TheCall, unsigned ArgNum) {503 llvm::APSInt Result;504 505 // We can't check the value of a dependent argument.506 Expr *Arg = TheCall->getArg(ArgNum);507 if (Arg->isTypeDependent() || Arg->isValueDependent())508 return false;509 510 // Check constant-ness first.511 if (SemaRef.BuiltinConstantArg(TheCall, ArgNum, Result))512 return true;513 514 int64_t Val = Result.getSExtValue();515 if ((Val >= 0 && Val <= 3) || (Val >= 5 && Val <= 7))516 return false;517 518 return Diag(TheCall->getBeginLoc(), diag::err_riscv_builtin_invalid_lmul)519 << Arg->getSourceRange();520}521 522static bool CheckInvalidVLENandLMUL(const TargetInfo &TI,523 llvm::StringMap<bool> &FunctionFeatureMap,524 CallExpr *TheCall, Sema &S, QualType Type,525 int EGW) {526 assert((EGW == 128 || EGW == 256) && "EGW can only be 128 or 256 bits");527 528 // LMUL * VLEN >= EGW529 ASTContext::BuiltinVectorTypeInfo Info =530 S.Context.getBuiltinVectorTypeInfo(Type->castAs<BuiltinType>());531 unsigned ElemSize = S.Context.getTypeSize(Info.ElementType);532 unsigned MinElemCount = Info.EC.getKnownMinValue();533 534 unsigned EGS = EGW / ElemSize;535 // If EGS is less than or equal to the minimum number of elements, then the536 // type is valid.537 if (EGS <= MinElemCount)538 return false;539 540 // Otherwise, we need vscale to be at least EGS / MinElemCont.541 assert(EGS % MinElemCount == 0);542 unsigned VScaleFactor = EGS / MinElemCount;543 // Vscale is VLEN/RVVBitsPerBlock.544 unsigned MinRequiredVLEN = VScaleFactor * llvm::RISCV::RVVBitsPerBlock;545 std::string RequiredExt = "zvl" + std::to_string(MinRequiredVLEN) + "b";546 if (!TI.hasFeature(RequiredExt) && !FunctionFeatureMap.lookup(RequiredExt))547 return S.Diag(TheCall->getBeginLoc(),548 diag::err_riscv_type_requires_extension)549 << Type << RequiredExt;550 551 return false;552}553 554bool SemaRISCV::CheckBuiltinFunctionCall(const TargetInfo &TI,555 unsigned BuiltinID,556 CallExpr *TheCall) {557 ASTContext &Context = getASTContext();558 const FunctionDecl *FD = SemaRef.getCurFunctionDecl();559 llvm::StringMap<bool> FunctionFeatureMap;560 Context.getFunctionFeatureMap(FunctionFeatureMap, FD);561 562 if (const auto *A = TheCall->getCalleeDecl()->getAttr<TargetAttr>()) {563 StringRef FeaturesStr = A->getFeaturesStr();564 llvm::SmallVector<StringRef> RequiredFeatures;565 FeaturesStr.split(RequiredFeatures, ',');566 for (auto RF : RequiredFeatures)567 if (!TI.hasFeature(RF) && !FunctionFeatureMap.lookup(RF))568 return Diag(TheCall->getBeginLoc(),569 diag::err_riscv_builtin_requires_extension)570 << /* IsExtension */ true << TheCall->getSourceRange() << RF;571 }572 573 // vmulh.vv, vmulh.vx, vmulhu.vv, vmulhu.vx, vmulhsu.vv, vmulhsu.vx,574 // vsmul.vv, vsmul.vx are not included for EEW=64 in Zve64*.575 switch (BuiltinID) {576 default:577 break;578 case RISCVVector::BI__builtin_rvv_vmulhsu_vv:579 case RISCVVector::BI__builtin_rvv_vmulhsu_vx:580 case RISCVVector::BI__builtin_rvv_vmulhsu_vv_tu:581 case RISCVVector::BI__builtin_rvv_vmulhsu_vx_tu:582 case RISCVVector::BI__builtin_rvv_vmulhsu_vv_m:583 case RISCVVector::BI__builtin_rvv_vmulhsu_vx_m:584 case RISCVVector::BI__builtin_rvv_vmulhsu_vv_mu:585 case RISCVVector::BI__builtin_rvv_vmulhsu_vx_mu:586 case RISCVVector::BI__builtin_rvv_vmulhsu_vv_tum:587 case RISCVVector::BI__builtin_rvv_vmulhsu_vx_tum:588 case RISCVVector::BI__builtin_rvv_vmulhsu_vv_tumu:589 case RISCVVector::BI__builtin_rvv_vmulhsu_vx_tumu:590 case RISCVVector::BI__builtin_rvv_vmulhu_vv:591 case RISCVVector::BI__builtin_rvv_vmulhu_vx:592 case RISCVVector::BI__builtin_rvv_vmulhu_vv_tu:593 case RISCVVector::BI__builtin_rvv_vmulhu_vx_tu:594 case RISCVVector::BI__builtin_rvv_vmulhu_vv_m:595 case RISCVVector::BI__builtin_rvv_vmulhu_vx_m:596 case RISCVVector::BI__builtin_rvv_vmulhu_vv_mu:597 case RISCVVector::BI__builtin_rvv_vmulhu_vx_mu:598 case RISCVVector::BI__builtin_rvv_vmulhu_vv_tum:599 case RISCVVector::BI__builtin_rvv_vmulhu_vx_tum:600 case RISCVVector::BI__builtin_rvv_vmulhu_vv_tumu:601 case RISCVVector::BI__builtin_rvv_vmulhu_vx_tumu:602 case RISCVVector::BI__builtin_rvv_vmulh_vv:603 case RISCVVector::BI__builtin_rvv_vmulh_vx:604 case RISCVVector::BI__builtin_rvv_vmulh_vv_tu:605 case RISCVVector::BI__builtin_rvv_vmulh_vx_tu:606 case RISCVVector::BI__builtin_rvv_vmulh_vv_m:607 case RISCVVector::BI__builtin_rvv_vmulh_vx_m:608 case RISCVVector::BI__builtin_rvv_vmulh_vv_mu:609 case RISCVVector::BI__builtin_rvv_vmulh_vx_mu:610 case RISCVVector::BI__builtin_rvv_vmulh_vv_tum:611 case RISCVVector::BI__builtin_rvv_vmulh_vx_tum:612 case RISCVVector::BI__builtin_rvv_vmulh_vv_tumu:613 case RISCVVector::BI__builtin_rvv_vmulh_vx_tumu:614 case RISCVVector::BI__builtin_rvv_vsmul_vv:615 case RISCVVector::BI__builtin_rvv_vsmul_vx:616 case RISCVVector::BI__builtin_rvv_vsmul_vv_tu:617 case RISCVVector::BI__builtin_rvv_vsmul_vx_tu:618 case RISCVVector::BI__builtin_rvv_vsmul_vv_m:619 case RISCVVector::BI__builtin_rvv_vsmul_vx_m:620 case RISCVVector::BI__builtin_rvv_vsmul_vv_mu:621 case RISCVVector::BI__builtin_rvv_vsmul_vx_mu:622 case RISCVVector::BI__builtin_rvv_vsmul_vv_tum:623 case RISCVVector::BI__builtin_rvv_vsmul_vx_tum:624 case RISCVVector::BI__builtin_rvv_vsmul_vv_tumu:625 case RISCVVector::BI__builtin_rvv_vsmul_vx_tumu: {626 ASTContext::BuiltinVectorTypeInfo Info = Context.getBuiltinVectorTypeInfo(627 TheCall->getType()->castAs<BuiltinType>());628 629 if (Context.getTypeSize(Info.ElementType) == 64 && !TI.hasFeature("v") &&630 !FunctionFeatureMap.lookup("v"))631 return Diag(TheCall->getBeginLoc(),632 diag::err_riscv_builtin_requires_extension)633 << /* IsExtension */ true << TheCall->getSourceRange() << "v";634 635 break;636 }637 }638 639 auto CheckVSetVL = [&](unsigned SEWOffset, unsigned LMULOffset) -> bool {640 const FunctionDecl *FD = SemaRef.getCurFunctionDecl();641 llvm::StringMap<bool> FunctionFeatureMap;642 Context.getFunctionFeatureMap(FunctionFeatureMap, FD);643 llvm::APSInt SEWResult;644 llvm::APSInt LMULResult;645 if (SemaRef.BuiltinConstantArg(TheCall, SEWOffset, SEWResult) ||646 SemaRef.BuiltinConstantArg(TheCall, LMULOffset, LMULResult))647 return true;648 int SEWValue = SEWResult.getSExtValue();649 int LMULValue = LMULResult.getSExtValue();650 if (((SEWValue == 0 && LMULValue == 5) || // e8mf8651 (SEWValue == 1 && LMULValue == 6) || // e16mf4652 (SEWValue == 2 && LMULValue == 7) || // e32mf2653 SEWValue == 3) && // e64654 !TI.hasFeature("zve64x") &&655 !FunctionFeatureMap.lookup("zve64x"))656 return Diag(TheCall->getBeginLoc(),657 diag::err_riscv_builtin_requires_extension)658 << /* IsExtension */ true << TheCall->getSourceRange() << "zve64x";659 return SemaRef.BuiltinConstantArgRange(TheCall, SEWOffset, 0, 3) ||660 CheckLMUL(TheCall, LMULOffset);661 };662 switch (BuiltinID) {663 case RISCVVector::BI__builtin_rvv_vsetvli:664 return CheckVSetVL(1, 2);665 case RISCVVector::BI__builtin_rvv_vsetvlimax:666 return CheckVSetVL(0, 1);667 case RISCVVector::BI__builtin_rvv_sf_vsettnt:668 case RISCVVector::BI__builtin_rvv_sf_vsettm:669 case RISCVVector::BI__builtin_rvv_sf_vsettn:670 case RISCVVector::BI__builtin_rvv_sf_vsettk:671 return SemaRef.BuiltinConstantArgRange(TheCall, 1, 0, 3) ||672 SemaRef.BuiltinConstantArgRange(TheCall, 2, 1, 3);673 case RISCVVector::BI__builtin_rvv_sf_mm_f_f_w1:674 case RISCVVector::BI__builtin_rvv_sf_mm_f_f_w2:675 case RISCVVector::BI__builtin_rvv_sf_mm_e5m2_e4m3_w4:676 case RISCVVector::BI__builtin_rvv_sf_mm_e5m2_e5m2_w4:677 case RISCVVector::BI__builtin_rvv_sf_mm_e4m3_e4m3_w4:678 case RISCVVector::BI__builtin_rvv_sf_mm_e4m3_e5m2_w4:679 case RISCVVector::BI__builtin_rvv_sf_mm_u_u_w4:680 case RISCVVector::BI__builtin_rvv_sf_mm_u_s_w4:681 case RISCVVector::BI__builtin_rvv_sf_mm_s_u_w4:682 case RISCVVector::BI__builtin_rvv_sf_mm_s_s_w4: {683 QualType Arg1Type = TheCall->getArg(1)->getType();684 ASTContext::BuiltinVectorTypeInfo Info =685 SemaRef.Context.getBuiltinVectorTypeInfo(686 Arg1Type->castAs<BuiltinType>());687 unsigned EltSize = SemaRef.Context.getTypeSize(Info.ElementType);688 llvm::APSInt Result;689 690 // We can't check the value of a dependent argument.691 Expr *Arg = TheCall->getArg(0);692 if (Arg->isTypeDependent() || Arg->isValueDependent())693 return false;694 695 // Check constant-ness first.696 if (SemaRef.BuiltinConstantArg(TheCall, 0, Result))697 return true;698 699 // For TEW = 32, mtd can only be 0, 4, 8, 12.700 // For TEW = 64, mtd can only be 0, 2, 4, 6, 8, 10, 12, 14.701 // Only `sf_mm_f_f_w1` and `sf_mm_f_f_w2` might have TEW = 64.702 if ((BuiltinID == RISCVVector::BI__builtin_rvv_sf_mm_f_f_w1 &&703 EltSize == 64) ||704 (BuiltinID == RISCVVector::BI__builtin_rvv_sf_mm_f_f_w2 &&705 EltSize == 32))706 return SemaRef.BuiltinConstantArgRange(TheCall, 0, 0, 15) ||707 SemaRef.BuiltinConstantArgMultiple(TheCall, 0, 2);708 return SemaRef.BuiltinConstantArgRange(TheCall, 0, 0, 15) ||709 SemaRef.BuiltinConstantArgMultiple(TheCall, 0, 4);710 }711 case RISCVVector::BI__builtin_rvv_sf_vtzero_t: {712 llvm::APSInt Log2SEWResult;713 llvm::APSInt TWidenResult;714 if (SemaRef.BuiltinConstantArg(TheCall, 3, Log2SEWResult) ||715 SemaRef.BuiltinConstantArg(TheCall, 4, TWidenResult))716 return true;717 718 int Log2SEW = Log2SEWResult.getSExtValue();719 int TWiden = TWidenResult.getSExtValue();720 721 // 3 <= LogSEW <= 6722 if (SemaRef.BuiltinConstantArgRange(TheCall, 3, 3, 6))723 return true;724 725 // TWiden726 if (TWiden != 1 && TWiden != 2 && TWiden != 4)727 return Diag(TheCall->getBeginLoc(),728 diag::err_riscv_builtin_invalid_twiden);729 730 int TEW = (1 << Log2SEW) * TWiden;731 732 // For TEW = 8, mtd can be 0~15.733 // For TEW = 16 or 64, mtd can only be 0, 2, 4, 6, 8, 10, 12, 14.734 // For TEW = 32, mtd can only be 0, 4, 8, 12.735 if (SemaRef.BuiltinConstantArgRange(TheCall, 0, 0, 15))736 return true;737 if (TEW == 16 || TEW == 64)738 return SemaRef.BuiltinConstantArgMultiple(TheCall, 0, 2);739 return SemaRef.BuiltinConstantArgMultiple(TheCall, 0, 4);740 }741 case RISCVVector::BI__builtin_rvv_vget_v: {742 ASTContext::BuiltinVectorTypeInfo ResVecInfo =743 Context.getBuiltinVectorTypeInfo(cast<BuiltinType>(744 TheCall->getType().getCanonicalType().getTypePtr()));745 ASTContext::BuiltinVectorTypeInfo VecInfo =746 Context.getBuiltinVectorTypeInfo(cast<BuiltinType>(747 TheCall->getArg(0)->getType().getCanonicalType().getTypePtr()));748 unsigned MaxIndex;749 if (VecInfo.NumVectors != 1) // vget for tuple type750 MaxIndex = VecInfo.NumVectors;751 else // vget for non-tuple type752 MaxIndex = (VecInfo.EC.getKnownMinValue() * VecInfo.NumVectors) /753 (ResVecInfo.EC.getKnownMinValue() * ResVecInfo.NumVectors);754 return SemaRef.BuiltinConstantArgRange(TheCall, 1, 0, MaxIndex - 1);755 }756 case RISCVVector::BI__builtin_rvv_vset_v: {757 ASTContext::BuiltinVectorTypeInfo ResVecInfo =758 Context.getBuiltinVectorTypeInfo(cast<BuiltinType>(759 TheCall->getType().getCanonicalType().getTypePtr()));760 ASTContext::BuiltinVectorTypeInfo VecInfo =761 Context.getBuiltinVectorTypeInfo(cast<BuiltinType>(762 TheCall->getArg(2)->getType().getCanonicalType().getTypePtr()));763 unsigned MaxIndex;764 if (ResVecInfo.NumVectors != 1) // vset for tuple type765 MaxIndex = ResVecInfo.NumVectors;766 else // vset fo non-tuple type767 MaxIndex = (ResVecInfo.EC.getKnownMinValue() * ResVecInfo.NumVectors) /768 (VecInfo.EC.getKnownMinValue() * VecInfo.NumVectors);769 return SemaRef.BuiltinConstantArgRange(TheCall, 1, 0, MaxIndex - 1);770 }771 // Vector Crypto772 case RISCVVector::BI__builtin_rvv_vaeskf1_vi_tu:773 case RISCVVector::BI__builtin_rvv_vaeskf2_vi_tu:774 case RISCVVector::BI__builtin_rvv_vaeskf2_vi:775 case RISCVVector::BI__builtin_rvv_vsm4k_vi_tu: {776 QualType Arg0Type = TheCall->getArg(0)->getType();777 QualType Arg1Type = TheCall->getArg(1)->getType();778 return CheckInvalidVLENandLMUL(TI, FunctionFeatureMap, TheCall, SemaRef,779 Arg0Type, 128) ||780 CheckInvalidVLENandLMUL(TI, FunctionFeatureMap, TheCall, SemaRef,781 Arg1Type, 128) ||782 SemaRef.BuiltinConstantArgRange(TheCall, 2, 0, 31);783 }784 case RISCVVector::BI__builtin_rvv_vsm3c_vi_tu:785 case RISCVVector::BI__builtin_rvv_vsm3c_vi: {786 QualType Arg0Type = TheCall->getArg(0)->getType();787 return CheckInvalidVLENandLMUL(TI, FunctionFeatureMap, TheCall, SemaRef,788 Arg0Type, 256) ||789 SemaRef.BuiltinConstantArgRange(TheCall, 2, 0, 31);790 }791 case RISCVVector::BI__builtin_rvv_vaeskf1_vi:792 case RISCVVector::BI__builtin_rvv_vsm4k_vi: {793 QualType Arg0Type = TheCall->getArg(0)->getType();794 return CheckInvalidVLENandLMUL(TI, FunctionFeatureMap, TheCall, SemaRef,795 Arg0Type, 128) ||796 SemaRef.BuiltinConstantArgRange(TheCall, 1, 0, 31);797 }798 case RISCVVector::BI__builtin_rvv_vaesdf_vv:799 case RISCVVector::BI__builtin_rvv_vaesdf_vs:800 case RISCVVector::BI__builtin_rvv_vaesdm_vv:801 case RISCVVector::BI__builtin_rvv_vaesdm_vs:802 case RISCVVector::BI__builtin_rvv_vaesef_vv:803 case RISCVVector::BI__builtin_rvv_vaesef_vs:804 case RISCVVector::BI__builtin_rvv_vaesem_vv:805 case RISCVVector::BI__builtin_rvv_vaesem_vs:806 case RISCVVector::BI__builtin_rvv_vaesz_vs:807 case RISCVVector::BI__builtin_rvv_vsm4r_vv:808 case RISCVVector::BI__builtin_rvv_vsm4r_vs:809 case RISCVVector::BI__builtin_rvv_vaesdf_vv_tu:810 case RISCVVector::BI__builtin_rvv_vaesdf_vs_tu:811 case RISCVVector::BI__builtin_rvv_vaesdm_vv_tu:812 case RISCVVector::BI__builtin_rvv_vaesdm_vs_tu:813 case RISCVVector::BI__builtin_rvv_vaesef_vv_tu:814 case RISCVVector::BI__builtin_rvv_vaesef_vs_tu:815 case RISCVVector::BI__builtin_rvv_vaesem_vv_tu:816 case RISCVVector::BI__builtin_rvv_vaesem_vs_tu:817 case RISCVVector::BI__builtin_rvv_vaesz_vs_tu:818 case RISCVVector::BI__builtin_rvv_vsm4r_vv_tu:819 case RISCVVector::BI__builtin_rvv_vsm4r_vs_tu: {820 QualType Arg0Type = TheCall->getArg(0)->getType();821 QualType Arg1Type = TheCall->getArg(1)->getType();822 return CheckInvalidVLENandLMUL(TI, FunctionFeatureMap, TheCall, SemaRef,823 Arg0Type, 128) ||824 CheckInvalidVLENandLMUL(TI, FunctionFeatureMap, TheCall, SemaRef,825 Arg1Type, 128);826 }827 case RISCVVector::BI__builtin_rvv_vsha2ch_vv:828 case RISCVVector::BI__builtin_rvv_vsha2cl_vv:829 case RISCVVector::BI__builtin_rvv_vsha2ms_vv:830 case RISCVVector::BI__builtin_rvv_vsha2ch_vv_tu:831 case RISCVVector::BI__builtin_rvv_vsha2cl_vv_tu:832 case RISCVVector::BI__builtin_rvv_vsha2ms_vv_tu: {833 QualType Arg0Type = TheCall->getArg(0)->getType();834 QualType Arg1Type = TheCall->getArg(1)->getType();835 QualType Arg2Type = TheCall->getArg(2)->getType();836 ASTContext::BuiltinVectorTypeInfo Info =837 Context.getBuiltinVectorTypeInfo(Arg0Type->castAs<BuiltinType>());838 uint64_t ElemSize = Context.getTypeSize(Info.ElementType);839 if (ElemSize == 64 && !TI.hasFeature("zvknhb") &&840 !FunctionFeatureMap.lookup("zvknhb"))841 return Diag(TheCall->getBeginLoc(),842 diag::err_riscv_builtin_requires_extension)843 << /* IsExtension */ true << TheCall->getSourceRange() << "zvknhb";844 // If ElemSize is 32, check at least zvknha or zvknhb is enabled.845 if (!TI.hasFeature("zvknha") && !FunctionFeatureMap.lookup("zvknha") &&846 !TI.hasFeature("zvknhb") && !FunctionFeatureMap.lookup("zvknhb"))847 return Diag(TheCall->getBeginLoc(),848 diag::err_riscv_builtin_requires_extension)849 << /* IsExtension */ true << TheCall->getSourceRange()850 << "zvknha or zvknhb";851 852 return CheckInvalidVLENandLMUL(TI, FunctionFeatureMap, TheCall, SemaRef,853 Arg0Type, ElemSize * 4) ||854 CheckInvalidVLENandLMUL(TI, FunctionFeatureMap, TheCall, SemaRef,855 Arg1Type, ElemSize * 4) ||856 CheckInvalidVLENandLMUL(TI, FunctionFeatureMap, TheCall, SemaRef,857 Arg2Type, ElemSize * 4);858 }859 860 case RISCVVector::BI__builtin_rvv_sf_vc_i_se:861 // bit_27_26, bit_24_20, bit_11_7, simm5, sew, log2lmul862 return SemaRef.BuiltinConstantArgRange(TheCall, 0, 0, 3) ||863 SemaRef.BuiltinConstantArgRange(TheCall, 1, 0, 31) ||864 SemaRef.BuiltinConstantArgRange(TheCall, 2, 0, 31) ||865 SemaRef.BuiltinConstantArgRange(TheCall, 3, -16, 15) ||866 CheckLMUL(TheCall, 5);867 case RISCVVector::BI__builtin_rvv_sf_vc_iv_se:868 // bit_27_26, bit_11_7, vs2, simm5869 return SemaRef.BuiltinConstantArgRange(TheCall, 0, 0, 3) ||870 SemaRef.BuiltinConstantArgRange(TheCall, 1, 0, 31) ||871 SemaRef.BuiltinConstantArgRange(TheCall, 3, -16, 15);872 case RISCVVector::BI__builtin_rvv_sf_vc_v_i:873 case RISCVVector::BI__builtin_rvv_sf_vc_v_i_se:874 // bit_27_26, bit_24_20, simm5875 return SemaRef.BuiltinConstantArgRange(TheCall, 0, 0, 3) ||876 SemaRef.BuiltinConstantArgRange(TheCall, 1, 0, 31) ||877 SemaRef.BuiltinConstantArgRange(TheCall, 2, -16, 15);878 case RISCVVector::BI__builtin_rvv_sf_vc_v_iv:879 case RISCVVector::BI__builtin_rvv_sf_vc_v_iv_se:880 // bit_27_26, vs2, simm5881 return SemaRef.BuiltinConstantArgRange(TheCall, 0, 0, 3) ||882 SemaRef.BuiltinConstantArgRange(TheCall, 2, -16, 15);883 case RISCVVector::BI__builtin_rvv_sf_vc_ivv_se:884 case RISCVVector::BI__builtin_rvv_sf_vc_ivw_se:885 case RISCVVector::BI__builtin_rvv_sf_vc_v_ivv:886 case RISCVVector::BI__builtin_rvv_sf_vc_v_ivw:887 case RISCVVector::BI__builtin_rvv_sf_vc_v_ivv_se:888 case RISCVVector::BI__builtin_rvv_sf_vc_v_ivw_se:889 // bit_27_26, vd, vs2, simm5890 return SemaRef.BuiltinConstantArgRange(TheCall, 0, 0, 3) ||891 SemaRef.BuiltinConstantArgRange(TheCall, 3, -16, 15);892 case RISCVVector::BI__builtin_rvv_sf_vc_x_se:893 // bit_27_26, bit_24_20, bit_11_7, xs1, sew, log2lmul894 return SemaRef.BuiltinConstantArgRange(TheCall, 0, 0, 3) ||895 SemaRef.BuiltinConstantArgRange(TheCall, 1, 0, 31) ||896 SemaRef.BuiltinConstantArgRange(TheCall, 2, 0, 31) ||897 CheckLMUL(TheCall, 5);898 case RISCVVector::BI__builtin_rvv_sf_vc_xv_se:899 case RISCVVector::BI__builtin_rvv_sf_vc_vv_se:900 // bit_27_26, bit_11_7, vs2, xs1/vs1901 case RISCVVector::BI__builtin_rvv_sf_vc_v_x:902 case RISCVVector::BI__builtin_rvv_sf_vc_v_x_se:903 // bit_27_26, bit_24-20, xs1904 return SemaRef.BuiltinConstantArgRange(TheCall, 0, 0, 3) ||905 SemaRef.BuiltinConstantArgRange(TheCall, 1, 0, 31);906 case RISCVVector::BI__builtin_rvv_sf_vc_vvv_se:907 case RISCVVector::BI__builtin_rvv_sf_vc_xvv_se:908 case RISCVVector::BI__builtin_rvv_sf_vc_vvw_se:909 case RISCVVector::BI__builtin_rvv_sf_vc_xvw_se:910 // bit_27_26, vd, vs2, xs1911 case RISCVVector::BI__builtin_rvv_sf_vc_v_xv:912 case RISCVVector::BI__builtin_rvv_sf_vc_v_vv:913 case RISCVVector::BI__builtin_rvv_sf_vc_v_xv_se:914 case RISCVVector::BI__builtin_rvv_sf_vc_v_vv_se:915 // bit_27_26, vs2, xs1/vs1916 case RISCVVector::BI__builtin_rvv_sf_vc_v_xvv:917 case RISCVVector::BI__builtin_rvv_sf_vc_v_vvv:918 case RISCVVector::BI__builtin_rvv_sf_vc_v_xvw:919 case RISCVVector::BI__builtin_rvv_sf_vc_v_vvw:920 case RISCVVector::BI__builtin_rvv_sf_vc_v_xvv_se:921 case RISCVVector::BI__builtin_rvv_sf_vc_v_vvv_se:922 case RISCVVector::BI__builtin_rvv_sf_vc_v_xvw_se:923 case RISCVVector::BI__builtin_rvv_sf_vc_v_vvw_se:924 // bit_27_26, vd, vs2, xs1/vs1925 return SemaRef.BuiltinConstantArgRange(TheCall, 0, 0, 3);926 case RISCVVector::BI__builtin_rvv_sf_vc_fv_se:927 // bit_26, bit_11_7, vs2, fs1928 return SemaRef.BuiltinConstantArgRange(TheCall, 0, 0, 1) ||929 SemaRef.BuiltinConstantArgRange(TheCall, 1, 0, 31);930 case RISCVVector::BI__builtin_rvv_sf_vc_fvv_se:931 case RISCVVector::BI__builtin_rvv_sf_vc_fvw_se:932 case RISCVVector::BI__builtin_rvv_sf_vc_v_fvv:933 case RISCVVector::BI__builtin_rvv_sf_vc_v_fvw:934 case RISCVVector::BI__builtin_rvv_sf_vc_v_fvv_se:935 case RISCVVector::BI__builtin_rvv_sf_vc_v_fvw_se:936 // bit_26, vd, vs2, fs1937 case RISCVVector::BI__builtin_rvv_sf_vc_v_fv:938 case RISCVVector::BI__builtin_rvv_sf_vc_v_fv_se:939 // bit_26, vs2, fs1940 return SemaRef.BuiltinConstantArgRange(TheCall, 0, 0, 1);941 // Check if byteselect is in [0, 3]942 case RISCV::BI__builtin_riscv_aes32dsi:943 case RISCV::BI__builtin_riscv_aes32dsmi:944 case RISCV::BI__builtin_riscv_aes32esi:945 case RISCV::BI__builtin_riscv_aes32esmi:946 case RISCV::BI__builtin_riscv_sm4ks:947 case RISCV::BI__builtin_riscv_sm4ed:948 return SemaRef.BuiltinConstantArgRange(TheCall, 2, 0, 3);949 // Check if rnum is in [0, 10]950 case RISCV::BI__builtin_riscv_aes64ks1i:951 return SemaRef.BuiltinConstantArgRange(TheCall, 1, 0, 10);952 // Check if value range for vxrm is in [0, 3]953 case RISCVVector::BI__builtin_rvv_vaaddu_vv:954 case RISCVVector::BI__builtin_rvv_vaaddu_vx:955 case RISCVVector::BI__builtin_rvv_vaadd_vv:956 case RISCVVector::BI__builtin_rvv_vaadd_vx:957 case RISCVVector::BI__builtin_rvv_vasubu_vv:958 case RISCVVector::BI__builtin_rvv_vasubu_vx:959 case RISCVVector::BI__builtin_rvv_vasub_vv:960 case RISCVVector::BI__builtin_rvv_vasub_vx:961 case RISCVVector::BI__builtin_rvv_vsmul_vv:962 case RISCVVector::BI__builtin_rvv_vsmul_vx:963 case RISCVVector::BI__builtin_rvv_vssra_vv:964 case RISCVVector::BI__builtin_rvv_vssra_vx:965 case RISCVVector::BI__builtin_rvv_vssrl_vv:966 case RISCVVector::BI__builtin_rvv_vssrl_vx:967 case RISCVVector::BI__builtin_rvv_vnclip_wv:968 case RISCVVector::BI__builtin_rvv_vnclip_wx:969 case RISCVVector::BI__builtin_rvv_vnclipu_wv:970 case RISCVVector::BI__builtin_rvv_vnclipu_wx:971 return SemaRef.BuiltinConstantArgRange(TheCall, 2, 0, 3);972 case RISCVVector::BI__builtin_rvv_vaaddu_vv_tu:973 case RISCVVector::BI__builtin_rvv_vaaddu_vx_tu:974 case RISCVVector::BI__builtin_rvv_vaadd_vv_tu:975 case RISCVVector::BI__builtin_rvv_vaadd_vx_tu:976 case RISCVVector::BI__builtin_rvv_vasubu_vv_tu:977 case RISCVVector::BI__builtin_rvv_vasubu_vx_tu:978 case RISCVVector::BI__builtin_rvv_vasub_vv_tu:979 case RISCVVector::BI__builtin_rvv_vasub_vx_tu:980 case RISCVVector::BI__builtin_rvv_vsmul_vv_tu:981 case RISCVVector::BI__builtin_rvv_vsmul_vx_tu:982 case RISCVVector::BI__builtin_rvv_vssra_vv_tu:983 case RISCVVector::BI__builtin_rvv_vssra_vx_tu:984 case RISCVVector::BI__builtin_rvv_vssrl_vv_tu:985 case RISCVVector::BI__builtin_rvv_vssrl_vx_tu:986 case RISCVVector::BI__builtin_rvv_vnclip_wv_tu:987 case RISCVVector::BI__builtin_rvv_vnclip_wx_tu:988 case RISCVVector::BI__builtin_rvv_vnclipu_wv_tu:989 case RISCVVector::BI__builtin_rvv_vnclipu_wx_tu:990 case RISCVVector::BI__builtin_rvv_vaaddu_vv_m:991 case RISCVVector::BI__builtin_rvv_vaaddu_vx_m:992 case RISCVVector::BI__builtin_rvv_vaadd_vv_m:993 case RISCVVector::BI__builtin_rvv_vaadd_vx_m:994 case RISCVVector::BI__builtin_rvv_vasubu_vv_m:995 case RISCVVector::BI__builtin_rvv_vasubu_vx_m:996 case RISCVVector::BI__builtin_rvv_vasub_vv_m:997 case RISCVVector::BI__builtin_rvv_vasub_vx_m:998 case RISCVVector::BI__builtin_rvv_vsmul_vv_m:999 case RISCVVector::BI__builtin_rvv_vsmul_vx_m:1000 case RISCVVector::BI__builtin_rvv_vssra_vv_m:1001 case RISCVVector::BI__builtin_rvv_vssra_vx_m:1002 case RISCVVector::BI__builtin_rvv_vssrl_vv_m:1003 case RISCVVector::BI__builtin_rvv_vssrl_vx_m:1004 case RISCVVector::BI__builtin_rvv_vnclip_wv_m:1005 case RISCVVector::BI__builtin_rvv_vnclip_wx_m:1006 case RISCVVector::BI__builtin_rvv_vnclipu_wv_m:1007 case RISCVVector::BI__builtin_rvv_vnclipu_wx_m:1008 return SemaRef.BuiltinConstantArgRange(TheCall, 3, 0, 3);1009 case RISCVVector::BI__builtin_rvv_vaaddu_vv_tum:1010 case RISCVVector::BI__builtin_rvv_vaaddu_vv_tumu:1011 case RISCVVector::BI__builtin_rvv_vaaddu_vv_mu:1012 case RISCVVector::BI__builtin_rvv_vaaddu_vx_tum:1013 case RISCVVector::BI__builtin_rvv_vaaddu_vx_tumu:1014 case RISCVVector::BI__builtin_rvv_vaaddu_vx_mu:1015 case RISCVVector::BI__builtin_rvv_vaadd_vv_tum:1016 case RISCVVector::BI__builtin_rvv_vaadd_vv_tumu:1017 case RISCVVector::BI__builtin_rvv_vaadd_vv_mu:1018 case RISCVVector::BI__builtin_rvv_vaadd_vx_tum:1019 case RISCVVector::BI__builtin_rvv_vaadd_vx_tumu:1020 case RISCVVector::BI__builtin_rvv_vaadd_vx_mu:1021 case RISCVVector::BI__builtin_rvv_vasubu_vv_tum:1022 case RISCVVector::BI__builtin_rvv_vasubu_vv_tumu:1023 case RISCVVector::BI__builtin_rvv_vasubu_vv_mu:1024 case RISCVVector::BI__builtin_rvv_vasubu_vx_tum:1025 case RISCVVector::BI__builtin_rvv_vasubu_vx_tumu:1026 case RISCVVector::BI__builtin_rvv_vasubu_vx_mu:1027 case RISCVVector::BI__builtin_rvv_vasub_vv_tum:1028 case RISCVVector::BI__builtin_rvv_vasub_vv_tumu:1029 case RISCVVector::BI__builtin_rvv_vasub_vv_mu:1030 case RISCVVector::BI__builtin_rvv_vasub_vx_tum:1031 case RISCVVector::BI__builtin_rvv_vasub_vx_tumu:1032 case RISCVVector::BI__builtin_rvv_vasub_vx_mu:1033 case RISCVVector::BI__builtin_rvv_vsmul_vv_mu:1034 case RISCVVector::BI__builtin_rvv_vsmul_vx_mu:1035 case RISCVVector::BI__builtin_rvv_vssra_vv_mu:1036 case RISCVVector::BI__builtin_rvv_vssra_vx_mu:1037 case RISCVVector::BI__builtin_rvv_vssrl_vv_mu:1038 case RISCVVector::BI__builtin_rvv_vssrl_vx_mu:1039 case RISCVVector::BI__builtin_rvv_vnclip_wv_mu:1040 case RISCVVector::BI__builtin_rvv_vnclip_wx_mu:1041 case RISCVVector::BI__builtin_rvv_vnclipu_wv_mu:1042 case RISCVVector::BI__builtin_rvv_vnclipu_wx_mu:1043 case RISCVVector::BI__builtin_rvv_vsmul_vv_tum:1044 case RISCVVector::BI__builtin_rvv_vsmul_vx_tum:1045 case RISCVVector::BI__builtin_rvv_vssra_vv_tum:1046 case RISCVVector::BI__builtin_rvv_vssra_vx_tum:1047 case RISCVVector::BI__builtin_rvv_vssrl_vv_tum:1048 case RISCVVector::BI__builtin_rvv_vssrl_vx_tum:1049 case RISCVVector::BI__builtin_rvv_vnclip_wv_tum:1050 case RISCVVector::BI__builtin_rvv_vnclip_wx_tum:1051 case RISCVVector::BI__builtin_rvv_vnclipu_wv_tum:1052 case RISCVVector::BI__builtin_rvv_vnclipu_wx_tum:1053 case RISCVVector::BI__builtin_rvv_vsmul_vv_tumu:1054 case RISCVVector::BI__builtin_rvv_vsmul_vx_tumu:1055 case RISCVVector::BI__builtin_rvv_vssra_vv_tumu:1056 case RISCVVector::BI__builtin_rvv_vssra_vx_tumu:1057 case RISCVVector::BI__builtin_rvv_vssrl_vv_tumu:1058 case RISCVVector::BI__builtin_rvv_vssrl_vx_tumu:1059 case RISCVVector::BI__builtin_rvv_vnclip_wv_tumu:1060 case RISCVVector::BI__builtin_rvv_vnclip_wx_tumu:1061 case RISCVVector::BI__builtin_rvv_vnclipu_wv_tumu:1062 case RISCVVector::BI__builtin_rvv_vnclipu_wx_tumu:1063 return SemaRef.BuiltinConstantArgRange(TheCall, 4, 0, 3);1064 case RISCVVector::BI__builtin_rvv_vfsqrt_v_rm:1065 case RISCVVector::BI__builtin_rvv_vfrec7_v_rm:1066 case RISCVVector::BI__builtin_rvv_vfcvt_x_f_v_rm:1067 case RISCVVector::BI__builtin_rvv_vfcvt_xu_f_v_rm:1068 case RISCVVector::BI__builtin_rvv_vfcvt_f_x_v_rm:1069 case RISCVVector::BI__builtin_rvv_vfcvt_f_xu_v_rm:1070 case RISCVVector::BI__builtin_rvv_vfwcvt_x_f_v_rm:1071 case RISCVVector::BI__builtin_rvv_vfwcvt_xu_f_v_rm:1072 case RISCVVector::BI__builtin_rvv_vfncvt_x_f_w_rm:1073 case RISCVVector::BI__builtin_rvv_vfncvt_xu_f_w_rm:1074 case RISCVVector::BI__builtin_rvv_vfncvt_f_x_w_rm:1075 case RISCVVector::BI__builtin_rvv_vfncvt_f_xu_w_rm:1076 case RISCVVector::BI__builtin_rvv_vfncvt_f_f_w_rm:1077 case RISCVVector::BI__builtin_rvv_vfncvtbf16_f_f_w_rm:1078 return SemaRef.BuiltinConstantArgRange(TheCall, 1, 0, 4);1079 case RISCVVector::BI__builtin_rvv_vfadd_vv_rm:1080 case RISCVVector::BI__builtin_rvv_vfadd_vf_rm:1081 case RISCVVector::BI__builtin_rvv_vfsub_vv_rm:1082 case RISCVVector::BI__builtin_rvv_vfsub_vf_rm:1083 case RISCVVector::BI__builtin_rvv_vfrsub_vf_rm:1084 case RISCVVector::BI__builtin_rvv_vfwadd_vv_rm:1085 case RISCVVector::BI__builtin_rvv_vfwadd_vf_rm:1086 case RISCVVector::BI__builtin_rvv_vfwsub_vv_rm:1087 case RISCVVector::BI__builtin_rvv_vfwsub_vf_rm:1088 case RISCVVector::BI__builtin_rvv_vfwadd_wv_rm:1089 case RISCVVector::BI__builtin_rvv_vfwadd_wf_rm:1090 case RISCVVector::BI__builtin_rvv_vfwsub_wv_rm:1091 case RISCVVector::BI__builtin_rvv_vfwsub_wf_rm:1092 case RISCVVector::BI__builtin_rvv_vfmul_vv_rm:1093 case RISCVVector::BI__builtin_rvv_vfmul_vf_rm:1094 case RISCVVector::BI__builtin_rvv_vfdiv_vv_rm:1095 case RISCVVector::BI__builtin_rvv_vfdiv_vf_rm:1096 case RISCVVector::BI__builtin_rvv_vfrdiv_vf_rm:1097 case RISCVVector::BI__builtin_rvv_vfwmul_vv_rm:1098 case RISCVVector::BI__builtin_rvv_vfwmul_vf_rm:1099 case RISCVVector::BI__builtin_rvv_vfredosum_vs_rm:1100 case RISCVVector::BI__builtin_rvv_vfredusum_vs_rm:1101 case RISCVVector::BI__builtin_rvv_vfwredosum_vs_rm:1102 case RISCVVector::BI__builtin_rvv_vfwredusum_vs_rm:1103 case RISCVVector::BI__builtin_rvv_vfsqrt_v_rm_tu:1104 case RISCVVector::BI__builtin_rvv_vfrec7_v_rm_tu:1105 case RISCVVector::BI__builtin_rvv_vfcvt_x_f_v_rm_tu:1106 case RISCVVector::BI__builtin_rvv_vfcvt_xu_f_v_rm_tu:1107 case RISCVVector::BI__builtin_rvv_vfcvt_f_x_v_rm_tu:1108 case RISCVVector::BI__builtin_rvv_vfcvt_f_xu_v_rm_tu:1109 case RISCVVector::BI__builtin_rvv_vfwcvt_x_f_v_rm_tu:1110 case RISCVVector::BI__builtin_rvv_vfwcvt_xu_f_v_rm_tu:1111 case RISCVVector::BI__builtin_rvv_vfncvt_x_f_w_rm_tu:1112 case RISCVVector::BI__builtin_rvv_vfncvt_xu_f_w_rm_tu:1113 case RISCVVector::BI__builtin_rvv_vfncvt_f_x_w_rm_tu:1114 case RISCVVector::BI__builtin_rvv_vfncvt_f_xu_w_rm_tu:1115 case RISCVVector::BI__builtin_rvv_vfncvt_f_f_w_rm_tu:1116 case RISCVVector::BI__builtin_rvv_vfncvtbf16_f_f_w_rm_tu:1117 case RISCVVector::BI__builtin_rvv_vfsqrt_v_rm_m:1118 case RISCVVector::BI__builtin_rvv_vfrec7_v_rm_m:1119 case RISCVVector::BI__builtin_rvv_vfcvt_x_f_v_rm_m:1120 case RISCVVector::BI__builtin_rvv_vfcvt_xu_f_v_rm_m:1121 case RISCVVector::BI__builtin_rvv_vfcvt_f_x_v_rm_m:1122 case RISCVVector::BI__builtin_rvv_vfcvt_f_xu_v_rm_m:1123 case RISCVVector::BI__builtin_rvv_vfwcvt_x_f_v_rm_m:1124 case RISCVVector::BI__builtin_rvv_vfwcvt_xu_f_v_rm_m:1125 case RISCVVector::BI__builtin_rvv_vfncvt_x_f_w_rm_m:1126 case RISCVVector::BI__builtin_rvv_vfncvt_xu_f_w_rm_m:1127 case RISCVVector::BI__builtin_rvv_vfncvt_f_x_w_rm_m:1128 case RISCVVector::BI__builtin_rvv_vfncvt_f_xu_w_rm_m:1129 case RISCVVector::BI__builtin_rvv_vfncvt_f_f_w_rm_m:1130 case RISCVVector::BI__builtin_rvv_vfncvtbf16_f_f_w_rm_m:1131 return SemaRef.BuiltinConstantArgRange(TheCall, 2, 0, 4);1132 case RISCVVector::BI__builtin_rvv_vfadd_vv_rm_tu:1133 case RISCVVector::BI__builtin_rvv_vfadd_vf_rm_tu:1134 case RISCVVector::BI__builtin_rvv_vfsub_vv_rm_tu:1135 case RISCVVector::BI__builtin_rvv_vfsub_vf_rm_tu:1136 case RISCVVector::BI__builtin_rvv_vfrsub_vf_rm_tu:1137 case RISCVVector::BI__builtin_rvv_vfwadd_vv_rm_tu:1138 case RISCVVector::BI__builtin_rvv_vfwadd_vf_rm_tu:1139 case RISCVVector::BI__builtin_rvv_vfwsub_vv_rm_tu:1140 case RISCVVector::BI__builtin_rvv_vfwsub_vf_rm_tu:1141 case RISCVVector::BI__builtin_rvv_vfwadd_wv_rm_tu:1142 case RISCVVector::BI__builtin_rvv_vfwadd_wf_rm_tu:1143 case RISCVVector::BI__builtin_rvv_vfwsub_wv_rm_tu:1144 case RISCVVector::BI__builtin_rvv_vfwsub_wf_rm_tu:1145 case RISCVVector::BI__builtin_rvv_vfmul_vv_rm_tu:1146 case RISCVVector::BI__builtin_rvv_vfmul_vf_rm_tu:1147 case RISCVVector::BI__builtin_rvv_vfdiv_vv_rm_tu:1148 case RISCVVector::BI__builtin_rvv_vfdiv_vf_rm_tu:1149 case RISCVVector::BI__builtin_rvv_vfrdiv_vf_rm_tu:1150 case RISCVVector::BI__builtin_rvv_vfwmul_vv_rm_tu:1151 case RISCVVector::BI__builtin_rvv_vfwmul_vf_rm_tu:1152 case RISCVVector::BI__builtin_rvv_vfredosum_vs_rm_tu:1153 case RISCVVector::BI__builtin_rvv_vfredusum_vs_rm_tu:1154 case RISCVVector::BI__builtin_rvv_vfwredosum_vs_rm_tu:1155 case RISCVVector::BI__builtin_rvv_vfwredusum_vs_rm_tu:1156 case RISCVVector::BI__builtin_rvv_vfmacc_vv_rm:1157 case RISCVVector::BI__builtin_rvv_vfmacc_vf_rm:1158 case RISCVVector::BI__builtin_rvv_vfnmacc_vv_rm:1159 case RISCVVector::BI__builtin_rvv_vfnmacc_vf_rm:1160 case RISCVVector::BI__builtin_rvv_vfmsac_vv_rm:1161 case RISCVVector::BI__builtin_rvv_vfmsac_vf_rm:1162 case RISCVVector::BI__builtin_rvv_vfnmsac_vv_rm:1163 case RISCVVector::BI__builtin_rvv_vfnmsac_vf_rm:1164 case RISCVVector::BI__builtin_rvv_vfmadd_vv_rm:1165 case RISCVVector::BI__builtin_rvv_vfmadd_vf_rm:1166 case RISCVVector::BI__builtin_rvv_vfnmadd_vv_rm:1167 case RISCVVector::BI__builtin_rvv_vfnmadd_vf_rm:1168 case RISCVVector::BI__builtin_rvv_vfmsub_vv_rm:1169 case RISCVVector::BI__builtin_rvv_vfmsub_vf_rm:1170 case RISCVVector::BI__builtin_rvv_vfnmsub_vv_rm:1171 case RISCVVector::BI__builtin_rvv_vfnmsub_vf_rm:1172 case RISCVVector::BI__builtin_rvv_vfwmacc_vv_rm:1173 case RISCVVector::BI__builtin_rvv_vfwmacc_vf_rm:1174 case RISCVVector::BI__builtin_rvv_vfwnmacc_vv_rm:1175 case RISCVVector::BI__builtin_rvv_vfwnmacc_vf_rm:1176 case RISCVVector::BI__builtin_rvv_vfwmsac_vv_rm:1177 case RISCVVector::BI__builtin_rvv_vfwmsac_vf_rm:1178 case RISCVVector::BI__builtin_rvv_vfwnmsac_vv_rm:1179 case RISCVVector::BI__builtin_rvv_vfwnmsac_vf_rm:1180 case RISCVVector::BI__builtin_rvv_vfwmaccbf16_vv_rm:1181 case RISCVVector::BI__builtin_rvv_vfwmaccbf16_vf_rm:1182 case RISCVVector::BI__builtin_rvv_vfmacc_vv_rm_tu:1183 case RISCVVector::BI__builtin_rvv_vfmacc_vf_rm_tu:1184 case RISCVVector::BI__builtin_rvv_vfnmacc_vv_rm_tu:1185 case RISCVVector::BI__builtin_rvv_vfnmacc_vf_rm_tu:1186 case RISCVVector::BI__builtin_rvv_vfmsac_vv_rm_tu:1187 case RISCVVector::BI__builtin_rvv_vfmsac_vf_rm_tu:1188 case RISCVVector::BI__builtin_rvv_vfnmsac_vv_rm_tu:1189 case RISCVVector::BI__builtin_rvv_vfnmsac_vf_rm_tu:1190 case RISCVVector::BI__builtin_rvv_vfmadd_vv_rm_tu:1191 case RISCVVector::BI__builtin_rvv_vfmadd_vf_rm_tu:1192 case RISCVVector::BI__builtin_rvv_vfnmadd_vv_rm_tu:1193 case RISCVVector::BI__builtin_rvv_vfnmadd_vf_rm_tu:1194 case RISCVVector::BI__builtin_rvv_vfmsub_vv_rm_tu:1195 case RISCVVector::BI__builtin_rvv_vfmsub_vf_rm_tu:1196 case RISCVVector::BI__builtin_rvv_vfnmsub_vv_rm_tu:1197 case RISCVVector::BI__builtin_rvv_vfnmsub_vf_rm_tu:1198 case RISCVVector::BI__builtin_rvv_vfwmacc_vv_rm_tu:1199 case RISCVVector::BI__builtin_rvv_vfwmacc_vf_rm_tu:1200 case RISCVVector::BI__builtin_rvv_vfwnmacc_vv_rm_tu:1201 case RISCVVector::BI__builtin_rvv_vfwnmacc_vf_rm_tu:1202 case RISCVVector::BI__builtin_rvv_vfwmsac_vv_rm_tu:1203 case RISCVVector::BI__builtin_rvv_vfwmsac_vf_rm_tu:1204 case RISCVVector::BI__builtin_rvv_vfwnmsac_vv_rm_tu:1205 case RISCVVector::BI__builtin_rvv_vfwnmsac_vf_rm_tu:1206 case RISCVVector::BI__builtin_rvv_vfwmaccbf16_vv_rm_tu:1207 case RISCVVector::BI__builtin_rvv_vfwmaccbf16_vf_rm_tu:1208 case RISCVVector::BI__builtin_rvv_vfadd_vv_rm_m:1209 case RISCVVector::BI__builtin_rvv_vfadd_vf_rm_m:1210 case RISCVVector::BI__builtin_rvv_vfsub_vv_rm_m:1211 case RISCVVector::BI__builtin_rvv_vfsub_vf_rm_m:1212 case RISCVVector::BI__builtin_rvv_vfrsub_vf_rm_m:1213 case RISCVVector::BI__builtin_rvv_vfwadd_vv_rm_m:1214 case RISCVVector::BI__builtin_rvv_vfwadd_vf_rm_m:1215 case RISCVVector::BI__builtin_rvv_vfwsub_vv_rm_m:1216 case RISCVVector::BI__builtin_rvv_vfwsub_vf_rm_m:1217 case RISCVVector::BI__builtin_rvv_vfwadd_wv_rm_m:1218 case RISCVVector::BI__builtin_rvv_vfwadd_wf_rm_m:1219 case RISCVVector::BI__builtin_rvv_vfwsub_wv_rm_m:1220 case RISCVVector::BI__builtin_rvv_vfwsub_wf_rm_m:1221 case RISCVVector::BI__builtin_rvv_vfmul_vv_rm_m:1222 case RISCVVector::BI__builtin_rvv_vfmul_vf_rm_m:1223 case RISCVVector::BI__builtin_rvv_vfdiv_vv_rm_m:1224 case RISCVVector::BI__builtin_rvv_vfdiv_vf_rm_m:1225 case RISCVVector::BI__builtin_rvv_vfrdiv_vf_rm_m:1226 case RISCVVector::BI__builtin_rvv_vfwmul_vv_rm_m:1227 case RISCVVector::BI__builtin_rvv_vfwmul_vf_rm_m:1228 case RISCVVector::BI__builtin_rvv_vfredosum_vs_rm_m:1229 case RISCVVector::BI__builtin_rvv_vfredusum_vs_rm_m:1230 case RISCVVector::BI__builtin_rvv_vfwredosum_vs_rm_m:1231 case RISCVVector::BI__builtin_rvv_vfwredusum_vs_rm_m:1232 case RISCVVector::BI__builtin_rvv_vfsqrt_v_rm_tum:1233 case RISCVVector::BI__builtin_rvv_vfrec7_v_rm_tum:1234 case RISCVVector::BI__builtin_rvv_vfcvt_x_f_v_rm_tum:1235 case RISCVVector::BI__builtin_rvv_vfcvt_xu_f_v_rm_tum:1236 case RISCVVector::BI__builtin_rvv_vfcvt_f_x_v_rm_tum:1237 case RISCVVector::BI__builtin_rvv_vfcvt_f_xu_v_rm_tum:1238 case RISCVVector::BI__builtin_rvv_vfwcvt_x_f_v_rm_tum:1239 case RISCVVector::BI__builtin_rvv_vfwcvt_xu_f_v_rm_tum:1240 case RISCVVector::BI__builtin_rvv_vfncvt_x_f_w_rm_tum:1241 case RISCVVector::BI__builtin_rvv_vfncvt_xu_f_w_rm_tum:1242 case RISCVVector::BI__builtin_rvv_vfncvt_f_x_w_rm_tum:1243 case RISCVVector::BI__builtin_rvv_vfncvt_f_xu_w_rm_tum:1244 case RISCVVector::BI__builtin_rvv_vfncvt_f_f_w_rm_tum:1245 case RISCVVector::BI__builtin_rvv_vfncvtbf16_f_f_w_rm_tum:1246 case RISCVVector::BI__builtin_rvv_vfsqrt_v_rm_tumu:1247 case RISCVVector::BI__builtin_rvv_vfrec7_v_rm_tumu:1248 case RISCVVector::BI__builtin_rvv_vfcvt_x_f_v_rm_tumu:1249 case RISCVVector::BI__builtin_rvv_vfcvt_xu_f_v_rm_tumu:1250 case RISCVVector::BI__builtin_rvv_vfcvt_f_x_v_rm_tumu:1251 case RISCVVector::BI__builtin_rvv_vfcvt_f_xu_v_rm_tumu:1252 case RISCVVector::BI__builtin_rvv_vfwcvt_x_f_v_rm_tumu:1253 case RISCVVector::BI__builtin_rvv_vfwcvt_xu_f_v_rm_tumu:1254 case RISCVVector::BI__builtin_rvv_vfncvt_x_f_w_rm_tumu:1255 case RISCVVector::BI__builtin_rvv_vfncvt_xu_f_w_rm_tumu:1256 case RISCVVector::BI__builtin_rvv_vfncvt_f_x_w_rm_tumu:1257 case RISCVVector::BI__builtin_rvv_vfncvt_f_xu_w_rm_tumu:1258 case RISCVVector::BI__builtin_rvv_vfncvt_f_f_w_rm_tumu:1259 case RISCVVector::BI__builtin_rvv_vfncvtbf16_f_f_w_rm_tumu:1260 case RISCVVector::BI__builtin_rvv_vfsqrt_v_rm_mu:1261 case RISCVVector::BI__builtin_rvv_vfrec7_v_rm_mu:1262 case RISCVVector::BI__builtin_rvv_vfcvt_x_f_v_rm_mu:1263 case RISCVVector::BI__builtin_rvv_vfcvt_xu_f_v_rm_mu:1264 case RISCVVector::BI__builtin_rvv_vfcvt_f_x_v_rm_mu:1265 case RISCVVector::BI__builtin_rvv_vfcvt_f_xu_v_rm_mu:1266 case RISCVVector::BI__builtin_rvv_vfwcvt_x_f_v_rm_mu:1267 case RISCVVector::BI__builtin_rvv_vfwcvt_xu_f_v_rm_mu:1268 case RISCVVector::BI__builtin_rvv_vfncvt_x_f_w_rm_mu:1269 case RISCVVector::BI__builtin_rvv_vfncvt_xu_f_w_rm_mu:1270 case RISCVVector::BI__builtin_rvv_vfncvt_f_x_w_rm_mu:1271 case RISCVVector::BI__builtin_rvv_vfncvt_f_xu_w_rm_mu:1272 case RISCVVector::BI__builtin_rvv_vfncvt_f_f_w_rm_mu:1273 case RISCVVector::BI__builtin_rvv_vfncvtbf16_f_f_w_rm_mu:1274 return SemaRef.BuiltinConstantArgRange(TheCall, 3, 0, 4);1275 case RISCVVector::BI__builtin_rvv_vfmacc_vv_rm_m:1276 case RISCVVector::BI__builtin_rvv_vfmacc_vf_rm_m:1277 case RISCVVector::BI__builtin_rvv_vfnmacc_vv_rm_m:1278 case RISCVVector::BI__builtin_rvv_vfnmacc_vf_rm_m:1279 case RISCVVector::BI__builtin_rvv_vfmsac_vv_rm_m:1280 case RISCVVector::BI__builtin_rvv_vfmsac_vf_rm_m:1281 case RISCVVector::BI__builtin_rvv_vfnmsac_vv_rm_m:1282 case RISCVVector::BI__builtin_rvv_vfnmsac_vf_rm_m:1283 case RISCVVector::BI__builtin_rvv_vfmadd_vv_rm_m:1284 case RISCVVector::BI__builtin_rvv_vfmadd_vf_rm_m:1285 case RISCVVector::BI__builtin_rvv_vfnmadd_vv_rm_m:1286 case RISCVVector::BI__builtin_rvv_vfnmadd_vf_rm_m:1287 case RISCVVector::BI__builtin_rvv_vfmsub_vv_rm_m:1288 case RISCVVector::BI__builtin_rvv_vfmsub_vf_rm_m:1289 case RISCVVector::BI__builtin_rvv_vfnmsub_vv_rm_m:1290 case RISCVVector::BI__builtin_rvv_vfnmsub_vf_rm_m:1291 case RISCVVector::BI__builtin_rvv_vfwmacc_vv_rm_m:1292 case RISCVVector::BI__builtin_rvv_vfwmacc_vf_rm_m:1293 case RISCVVector::BI__builtin_rvv_vfwnmacc_vv_rm_m:1294 case RISCVVector::BI__builtin_rvv_vfwnmacc_vf_rm_m:1295 case RISCVVector::BI__builtin_rvv_vfwmsac_vv_rm_m:1296 case RISCVVector::BI__builtin_rvv_vfwmsac_vf_rm_m:1297 case RISCVVector::BI__builtin_rvv_vfwnmsac_vv_rm_m:1298 case RISCVVector::BI__builtin_rvv_vfwnmsac_vf_rm_m:1299 case RISCVVector::BI__builtin_rvv_vfwmaccbf16_vv_rm_m:1300 case RISCVVector::BI__builtin_rvv_vfwmaccbf16_vf_rm_m:1301 case RISCVVector::BI__builtin_rvv_vfadd_vv_rm_tum:1302 case RISCVVector::BI__builtin_rvv_vfadd_vf_rm_tum:1303 case RISCVVector::BI__builtin_rvv_vfsub_vv_rm_tum:1304 case RISCVVector::BI__builtin_rvv_vfsub_vf_rm_tum:1305 case RISCVVector::BI__builtin_rvv_vfrsub_vf_rm_tum:1306 case RISCVVector::BI__builtin_rvv_vfwadd_vv_rm_tum:1307 case RISCVVector::BI__builtin_rvv_vfwadd_vf_rm_tum:1308 case RISCVVector::BI__builtin_rvv_vfwsub_vv_rm_tum:1309 case RISCVVector::BI__builtin_rvv_vfwsub_vf_rm_tum:1310 case RISCVVector::BI__builtin_rvv_vfwadd_wv_rm_tum:1311 case RISCVVector::BI__builtin_rvv_vfwadd_wf_rm_tum:1312 case RISCVVector::BI__builtin_rvv_vfwsub_wv_rm_tum:1313 case RISCVVector::BI__builtin_rvv_vfwsub_wf_rm_tum:1314 case RISCVVector::BI__builtin_rvv_vfmul_vv_rm_tum:1315 case RISCVVector::BI__builtin_rvv_vfmul_vf_rm_tum:1316 case RISCVVector::BI__builtin_rvv_vfdiv_vv_rm_tum:1317 case RISCVVector::BI__builtin_rvv_vfdiv_vf_rm_tum:1318 case RISCVVector::BI__builtin_rvv_vfrdiv_vf_rm_tum:1319 case RISCVVector::BI__builtin_rvv_vfwmul_vv_rm_tum:1320 case RISCVVector::BI__builtin_rvv_vfwmul_vf_rm_tum:1321 case RISCVVector::BI__builtin_rvv_vfmacc_vv_rm_tum:1322 case RISCVVector::BI__builtin_rvv_vfmacc_vf_rm_tum:1323 case RISCVVector::BI__builtin_rvv_vfnmacc_vv_rm_tum:1324 case RISCVVector::BI__builtin_rvv_vfnmacc_vf_rm_tum:1325 case RISCVVector::BI__builtin_rvv_vfmsac_vv_rm_tum:1326 case RISCVVector::BI__builtin_rvv_vfmsac_vf_rm_tum:1327 case RISCVVector::BI__builtin_rvv_vfnmsac_vv_rm_tum:1328 case RISCVVector::BI__builtin_rvv_vfnmsac_vf_rm_tum:1329 case RISCVVector::BI__builtin_rvv_vfmadd_vv_rm_tum:1330 case RISCVVector::BI__builtin_rvv_vfmadd_vf_rm_tum:1331 case RISCVVector::BI__builtin_rvv_vfnmadd_vv_rm_tum:1332 case RISCVVector::BI__builtin_rvv_vfnmadd_vf_rm_tum:1333 case RISCVVector::BI__builtin_rvv_vfmsub_vv_rm_tum:1334 case RISCVVector::BI__builtin_rvv_vfmsub_vf_rm_tum:1335 case RISCVVector::BI__builtin_rvv_vfnmsub_vv_rm_tum:1336 case RISCVVector::BI__builtin_rvv_vfnmsub_vf_rm_tum:1337 case RISCVVector::BI__builtin_rvv_vfwmacc_vv_rm_tum:1338 case RISCVVector::BI__builtin_rvv_vfwmacc_vf_rm_tum:1339 case RISCVVector::BI__builtin_rvv_vfwnmacc_vv_rm_tum:1340 case RISCVVector::BI__builtin_rvv_vfwnmacc_vf_rm_tum:1341 case RISCVVector::BI__builtin_rvv_vfwmsac_vv_rm_tum:1342 case RISCVVector::BI__builtin_rvv_vfwmsac_vf_rm_tum:1343 case RISCVVector::BI__builtin_rvv_vfwnmsac_vv_rm_tum:1344 case RISCVVector::BI__builtin_rvv_vfwnmsac_vf_rm_tum:1345 case RISCVVector::BI__builtin_rvv_vfwmaccbf16_vv_rm_tum:1346 case RISCVVector::BI__builtin_rvv_vfwmaccbf16_vf_rm_tum:1347 case RISCVVector::BI__builtin_rvv_vfredosum_vs_rm_tum:1348 case RISCVVector::BI__builtin_rvv_vfredusum_vs_rm_tum:1349 case RISCVVector::BI__builtin_rvv_vfwredosum_vs_rm_tum:1350 case RISCVVector::BI__builtin_rvv_vfwredusum_vs_rm_tum:1351 case RISCVVector::BI__builtin_rvv_vfadd_vv_rm_tumu:1352 case RISCVVector::BI__builtin_rvv_vfadd_vf_rm_tumu:1353 case RISCVVector::BI__builtin_rvv_vfsub_vv_rm_tumu:1354 case RISCVVector::BI__builtin_rvv_vfsub_vf_rm_tumu:1355 case RISCVVector::BI__builtin_rvv_vfrsub_vf_rm_tumu:1356 case RISCVVector::BI__builtin_rvv_vfwadd_vv_rm_tumu:1357 case RISCVVector::BI__builtin_rvv_vfwadd_vf_rm_tumu:1358 case RISCVVector::BI__builtin_rvv_vfwsub_vv_rm_tumu:1359 case RISCVVector::BI__builtin_rvv_vfwsub_vf_rm_tumu:1360 case RISCVVector::BI__builtin_rvv_vfwadd_wv_rm_tumu:1361 case RISCVVector::BI__builtin_rvv_vfwadd_wf_rm_tumu:1362 case RISCVVector::BI__builtin_rvv_vfwsub_wv_rm_tumu:1363 case RISCVVector::BI__builtin_rvv_vfwsub_wf_rm_tumu:1364 case RISCVVector::BI__builtin_rvv_vfmul_vv_rm_tumu:1365 case RISCVVector::BI__builtin_rvv_vfmul_vf_rm_tumu:1366 case RISCVVector::BI__builtin_rvv_vfdiv_vv_rm_tumu:1367 case RISCVVector::BI__builtin_rvv_vfdiv_vf_rm_tumu:1368 case RISCVVector::BI__builtin_rvv_vfrdiv_vf_rm_tumu:1369 case RISCVVector::BI__builtin_rvv_vfwmul_vv_rm_tumu:1370 case RISCVVector::BI__builtin_rvv_vfwmul_vf_rm_tumu:1371 case RISCVVector::BI__builtin_rvv_vfmacc_vv_rm_tumu:1372 case RISCVVector::BI__builtin_rvv_vfmacc_vf_rm_tumu:1373 case RISCVVector::BI__builtin_rvv_vfnmacc_vv_rm_tumu:1374 case RISCVVector::BI__builtin_rvv_vfnmacc_vf_rm_tumu:1375 case RISCVVector::BI__builtin_rvv_vfmsac_vv_rm_tumu:1376 case RISCVVector::BI__builtin_rvv_vfmsac_vf_rm_tumu:1377 case RISCVVector::BI__builtin_rvv_vfnmsac_vv_rm_tumu:1378 case RISCVVector::BI__builtin_rvv_vfnmsac_vf_rm_tumu:1379 case RISCVVector::BI__builtin_rvv_vfmadd_vv_rm_tumu:1380 case RISCVVector::BI__builtin_rvv_vfmadd_vf_rm_tumu:1381 case RISCVVector::BI__builtin_rvv_vfnmadd_vv_rm_tumu:1382 case RISCVVector::BI__builtin_rvv_vfnmadd_vf_rm_tumu:1383 case RISCVVector::BI__builtin_rvv_vfmsub_vv_rm_tumu:1384 case RISCVVector::BI__builtin_rvv_vfmsub_vf_rm_tumu:1385 case RISCVVector::BI__builtin_rvv_vfnmsub_vv_rm_tumu:1386 case RISCVVector::BI__builtin_rvv_vfnmsub_vf_rm_tumu:1387 case RISCVVector::BI__builtin_rvv_vfwmacc_vv_rm_tumu:1388 case RISCVVector::BI__builtin_rvv_vfwmacc_vf_rm_tumu:1389 case RISCVVector::BI__builtin_rvv_vfwnmacc_vv_rm_tumu:1390 case RISCVVector::BI__builtin_rvv_vfwnmacc_vf_rm_tumu:1391 case RISCVVector::BI__builtin_rvv_vfwmsac_vv_rm_tumu:1392 case RISCVVector::BI__builtin_rvv_vfwmsac_vf_rm_tumu:1393 case RISCVVector::BI__builtin_rvv_vfwnmsac_vv_rm_tumu:1394 case RISCVVector::BI__builtin_rvv_vfwnmsac_vf_rm_tumu:1395 case RISCVVector::BI__builtin_rvv_vfwmaccbf16_vv_rm_tumu:1396 case RISCVVector::BI__builtin_rvv_vfwmaccbf16_vf_rm_tumu:1397 case RISCVVector::BI__builtin_rvv_vfadd_vv_rm_mu:1398 case RISCVVector::BI__builtin_rvv_vfadd_vf_rm_mu:1399 case RISCVVector::BI__builtin_rvv_vfsub_vv_rm_mu:1400 case RISCVVector::BI__builtin_rvv_vfsub_vf_rm_mu:1401 case RISCVVector::BI__builtin_rvv_vfrsub_vf_rm_mu:1402 case RISCVVector::BI__builtin_rvv_vfwadd_vv_rm_mu:1403 case RISCVVector::BI__builtin_rvv_vfwadd_vf_rm_mu:1404 case RISCVVector::BI__builtin_rvv_vfwsub_vv_rm_mu:1405 case RISCVVector::BI__builtin_rvv_vfwsub_vf_rm_mu:1406 case RISCVVector::BI__builtin_rvv_vfwadd_wv_rm_mu:1407 case RISCVVector::BI__builtin_rvv_vfwadd_wf_rm_mu:1408 case RISCVVector::BI__builtin_rvv_vfwsub_wv_rm_mu:1409 case RISCVVector::BI__builtin_rvv_vfwsub_wf_rm_mu:1410 case RISCVVector::BI__builtin_rvv_vfmul_vv_rm_mu:1411 case RISCVVector::BI__builtin_rvv_vfmul_vf_rm_mu:1412 case RISCVVector::BI__builtin_rvv_vfdiv_vv_rm_mu:1413 case RISCVVector::BI__builtin_rvv_vfdiv_vf_rm_mu:1414 case RISCVVector::BI__builtin_rvv_vfrdiv_vf_rm_mu:1415 case RISCVVector::BI__builtin_rvv_vfwmul_vv_rm_mu:1416 case RISCVVector::BI__builtin_rvv_vfwmul_vf_rm_mu:1417 case RISCVVector::BI__builtin_rvv_vfmacc_vv_rm_mu:1418 case RISCVVector::BI__builtin_rvv_vfmacc_vf_rm_mu:1419 case RISCVVector::BI__builtin_rvv_vfnmacc_vv_rm_mu:1420 case RISCVVector::BI__builtin_rvv_vfnmacc_vf_rm_mu:1421 case RISCVVector::BI__builtin_rvv_vfmsac_vv_rm_mu:1422 case RISCVVector::BI__builtin_rvv_vfmsac_vf_rm_mu:1423 case RISCVVector::BI__builtin_rvv_vfnmsac_vv_rm_mu:1424 case RISCVVector::BI__builtin_rvv_vfnmsac_vf_rm_mu:1425 case RISCVVector::BI__builtin_rvv_vfmadd_vv_rm_mu:1426 case RISCVVector::BI__builtin_rvv_vfmadd_vf_rm_mu:1427 case RISCVVector::BI__builtin_rvv_vfnmadd_vv_rm_mu:1428 case RISCVVector::BI__builtin_rvv_vfnmadd_vf_rm_mu:1429 case RISCVVector::BI__builtin_rvv_vfmsub_vv_rm_mu:1430 case RISCVVector::BI__builtin_rvv_vfmsub_vf_rm_mu:1431 case RISCVVector::BI__builtin_rvv_vfnmsub_vv_rm_mu:1432 case RISCVVector::BI__builtin_rvv_vfnmsub_vf_rm_mu:1433 case RISCVVector::BI__builtin_rvv_vfwmacc_vv_rm_mu:1434 case RISCVVector::BI__builtin_rvv_vfwmacc_vf_rm_mu:1435 case RISCVVector::BI__builtin_rvv_vfwnmacc_vv_rm_mu:1436 case RISCVVector::BI__builtin_rvv_vfwnmacc_vf_rm_mu:1437 case RISCVVector::BI__builtin_rvv_vfwmsac_vv_rm_mu:1438 case RISCVVector::BI__builtin_rvv_vfwmsac_vf_rm_mu:1439 case RISCVVector::BI__builtin_rvv_vfwnmsac_vv_rm_mu:1440 case RISCVVector::BI__builtin_rvv_vfwnmsac_vf_rm_mu:1441 case RISCVVector::BI__builtin_rvv_vfwmaccbf16_vv_rm_mu:1442 case RISCVVector::BI__builtin_rvv_vfwmaccbf16_vf_rm_mu:1443 return SemaRef.BuiltinConstantArgRange(TheCall, 4, 0, 4);1444 case RISCV::BI__builtin_riscv_ntl_load:1445 case RISCV::BI__builtin_riscv_ntl_store:1446 DeclRefExpr *DRE =1447 cast<DeclRefExpr>(TheCall->getCallee()->IgnoreParenCasts());1448 assert((BuiltinID == RISCV::BI__builtin_riscv_ntl_store ||1449 BuiltinID == RISCV::BI__builtin_riscv_ntl_load) &&1450 "Unexpected RISC-V nontemporal load/store builtin!");1451 bool IsStore = BuiltinID == RISCV::BI__builtin_riscv_ntl_store;1452 unsigned NumArgs = IsStore ? 3 : 2;1453 1454 if (SemaRef.checkArgCountAtLeast(TheCall, NumArgs - 1))1455 return true;1456 1457 if (SemaRef.checkArgCountAtMost(TheCall, NumArgs))1458 return true;1459 1460 // Domain value should be compile-time constant.1461 // 2 <= domain <= 51462 if (TheCall->getNumArgs() == NumArgs &&1463 SemaRef.BuiltinConstantArgRange(TheCall, NumArgs - 1, 2, 5))1464 return true;1465 1466 Expr *PointerArg = TheCall->getArg(0);1467 ExprResult PointerArgResult =1468 SemaRef.DefaultFunctionArrayLvalueConversion(PointerArg);1469 1470 if (PointerArgResult.isInvalid())1471 return true;1472 PointerArg = PointerArgResult.get();1473 1474 const PointerType *PtrType = PointerArg->getType()->getAs<PointerType>();1475 if (!PtrType) {1476 Diag(DRE->getBeginLoc(), diag::err_nontemporal_builtin_must_be_pointer)1477 << PointerArg->getType() << PointerArg->getSourceRange();1478 return true;1479 }1480 1481 QualType ValType = PtrType->getPointeeType();1482 ValType = ValType.getUnqualifiedType();1483 if (!ValType->isIntegerType() && !ValType->isAnyPointerType() &&1484 !ValType->isBlockPointerType() && !ValType->isFloatingType() &&1485 !ValType->isVectorType() && !ValType->isRVVSizelessBuiltinType()) {1486 Diag(DRE->getBeginLoc(),1487 diag::err_nontemporal_builtin_must_be_pointer_intfltptr_or_vector)1488 << PointerArg->getType() << PointerArg->getSourceRange();1489 return true;1490 }1491 1492 if (!IsStore) {1493 TheCall->setType(ValType);1494 return false;1495 }1496 1497 ExprResult ValArg = TheCall->getArg(1);1498 InitializedEntity Entity = InitializedEntity::InitializeParameter(1499 Context, ValType, /*consume*/ false);1500 ValArg =1501 SemaRef.PerformCopyInitialization(Entity, SourceLocation(), ValArg);1502 if (ValArg.isInvalid())1503 return true;1504 1505 TheCall->setArg(1, ValArg.get());1506 TheCall->setType(Context.VoidTy);1507 return false;1508 }1509 1510 return false;1511}1512 1513void SemaRISCV::checkRVVTypeSupport(QualType Ty, SourceLocation Loc, Decl *D,1514 const llvm::StringMap<bool> &FeatureMap) {1515 ASTContext::BuiltinVectorTypeInfo Info =1516 SemaRef.Context.getBuiltinVectorTypeInfo(Ty->castAs<BuiltinType>());1517 unsigned EltSize = SemaRef.Context.getTypeSize(Info.ElementType);1518 unsigned MinElts = Info.EC.getKnownMinValue();1519 1520 if (Info.ElementType->isSpecificBuiltinType(BuiltinType::Double) &&1521 !FeatureMap.lookup("zve64d"))1522 Diag(Loc, diag::err_riscv_type_requires_extension) << Ty << "zve64d";1523 // (ELEN, LMUL) pairs of (8, mf8), (16, mf4), (32, mf2), (64, m1) requires at1524 // least zve64x1525 else if (((EltSize == 64 && Info.ElementType->isIntegerType()) ||1526 MinElts == 1) &&1527 !FeatureMap.lookup("zve64x"))1528 Diag(Loc, diag::err_riscv_type_requires_extension) << Ty << "zve64x";1529 else if (Info.ElementType->isFloat16Type() && !FeatureMap.lookup("zvfh") &&1530 !FeatureMap.lookup("zvfhmin") &&1531 !FeatureMap.lookup("xandesvpackfph"))1532 if (DeclareAndesVectorBuiltins) {1533 Diag(Loc, diag::err_riscv_type_requires_extension)1534 << Ty << "zvfh, zvfhmin or xandesvpackfph";1535 } else {1536 Diag(Loc, diag::err_riscv_type_requires_extension)1537 << Ty << "zvfh or zvfhmin";1538 }1539 else if (Info.ElementType->isBFloat16Type() &&1540 !FeatureMap.lookup("zvfbfmin") &&1541 !FeatureMap.lookup("xandesvbfhcvt") &&1542 !FeatureMap.lookup("experimental-zvfbfa"))1543 if (DeclareAndesVectorBuiltins) {1544 Diag(Loc, diag::err_riscv_type_requires_extension)1545 << Ty << "zvfbfmin or xandesvbfhcvt";1546 } else {1547 Diag(Loc, diag::err_riscv_type_requires_extension) << Ty << "zvfbfmin";1548 }1549 else if (Info.ElementType->isSpecificBuiltinType(BuiltinType::Float) &&1550 !FeatureMap.lookup("zve32f"))1551 Diag(Loc, diag::err_riscv_type_requires_extension) << Ty << "zve32f";1552 // Given that caller already checked isRVVType() before calling this function,1553 // if we don't have at least zve32x supported, then we need to emit error.1554 else if (!FeatureMap.lookup("zve32x"))1555 Diag(Loc, diag::err_riscv_type_requires_extension) << Ty << "zve32x";1556}1557 1558/// Are the two types RVV-bitcast-compatible types? I.e. is bitcasting from the1559/// first RVV type (e.g. an RVV scalable type) to the second type (e.g. an RVV1560/// VLS type) allowed?1561///1562/// This will also return false if the two given types do not make sense from1563/// the perspective of RVV bitcasts.1564bool SemaRISCV::isValidRVVBitcast(QualType srcTy, QualType destTy) {1565 assert(srcTy->isVectorType() || destTy->isVectorType());1566 1567 auto ValidScalableConversion = [](QualType FirstType, QualType SecondType) {1568 if (!FirstType->isRVVSizelessBuiltinType())1569 return false;1570 1571 const auto *VecTy = SecondType->getAs<VectorType>();1572 return VecTy && VecTy->getVectorKind() == VectorKind::RVVFixedLengthData;1573 };1574 1575 return ValidScalableConversion(srcTy, destTy) ||1576 ValidScalableConversion(destTy, srcTy);1577}1578 1579void SemaRISCV::handleInterruptAttr(Decl *D, const ParsedAttr &AL) {1580 // Warn about repeated attributes.1581 if (const auto *A = D->getAttr<RISCVInterruptAttr>()) {1582 Diag(AL.getRange().getBegin(),1583 diag::warn_riscv_repeated_interrupt_attribute);1584 Diag(A->getLocation(), diag::note_riscv_repeated_interrupt_attribute);1585 return;1586 }1587 1588 // Semantic checks for a function with the 'interrupt' attribute:1589 // - Must be a function.1590 // - Must have no parameters.1591 // - Must have the 'void' return type.1592 // - The attribute itself must have at most 2 arguments1593 // - The attribute arguments must be string literals, and valid choices.1594 // - The attribute arguments must be a valid combination1595 // - The current target must support the right extensions for the combination.1596 1597 if (D->getFunctionType() == nullptr) {1598 Diag(D->getLocation(), diag::warn_attribute_wrong_decl_type)1599 << AL << AL.isRegularKeywordAttribute() << ExpectedFunction;1600 return;1601 }1602 1603 if (hasFunctionProto(D) && getFunctionOrMethodNumParams(D) != 0) {1604 Diag(D->getLocation(), diag::warn_interrupt_signal_attribute_invalid)1605 << /*RISC-V*/ 2 << /*interrupt*/ 0 << 0;1606 return;1607 }1608 1609 if (!getFunctionOrMethodResultType(D)->isVoidType()) {1610 Diag(D->getLocation(), diag::warn_interrupt_signal_attribute_invalid)1611 << /*RISC-V*/ 2 << /*interrupt*/ 0 << 1;1612 return;1613 }1614 1615 if (!AL.checkAtMostNumArgs(SemaRef, 2))1616 return;1617 1618 bool HasSiFiveCLICType = false;1619 bool HasUnaryType = false;1620 1621 SmallSet<RISCVInterruptAttr::InterruptType, 2> Types;1622 for (unsigned ArgIndex = 0; ArgIndex < AL.getNumArgs(); ++ArgIndex) {1623 RISCVInterruptAttr::InterruptType Type;1624 StringRef TypeString;1625 SourceLocation Loc;1626 1627 if (!SemaRef.checkStringLiteralArgumentAttr(AL, ArgIndex, TypeString, &Loc))1628 return;1629 1630 if (!RISCVInterruptAttr::ConvertStrToInterruptType(TypeString, Type)) {1631 std::string TypeLiteral = ("\"" + TypeString + "\"").str();1632 Diag(AL.getLoc(), diag::warn_attribute_type_not_supported)1633 << AL << TypeLiteral << Loc;1634 return;1635 }1636 1637 switch (Type) {1638 case RISCVInterruptAttr::machine:1639 // "machine" could be combined with the SiFive CLIC types, or could be1640 // just "machine".1641 break;1642 case RISCVInterruptAttr::SiFiveCLICPreemptible:1643 case RISCVInterruptAttr::SiFiveCLICStackSwap:1644 // SiFive-CLIC types can be combined with each other and "machine"1645 HasSiFiveCLICType = true;1646 break;1647 case RISCVInterruptAttr::supervisor:1648 case RISCVInterruptAttr::rnmi:1649 case RISCVInterruptAttr::qcinest:1650 case RISCVInterruptAttr::qcinonest:1651 // "supervisor", "rnmi" and "qci-(no)nest" cannot be combined with any1652 // other types1653 HasUnaryType = true;1654 break;1655 }1656 1657 Types.insert(Type);1658 }1659 1660 if (HasUnaryType && Types.size() > 1) {1661 Diag(AL.getLoc(), diag::err_riscv_attribute_interrupt_invalid_combination);1662 return;1663 }1664 1665 if (HasUnaryType && HasSiFiveCLICType) {1666 Diag(AL.getLoc(), diag::err_riscv_attribute_interrupt_invalid_combination);1667 return;1668 }1669 1670 // "machine" is the default, if nothing is specified.1671 if (AL.getNumArgs() == 0)1672 Types.insert(RISCVInterruptAttr::machine);1673 1674 const TargetInfo &TI = getASTContext().getTargetInfo();1675 llvm::StringMap<bool> FunctionFeatureMap;1676 getASTContext().getFunctionFeatureMap(FunctionFeatureMap,1677 dyn_cast<FunctionDecl>(D));1678 1679 auto HasFeature = [&](StringRef FeatureName) -> bool {1680 return TI.hasFeature(FeatureName) || FunctionFeatureMap.lookup(FeatureName);1681 };1682 1683 for (RISCVInterruptAttr::InterruptType Type : Types) {1684 switch (Type) {1685 // The QCI interrupt types require Xqciint1686 case RISCVInterruptAttr::qcinest:1687 case RISCVInterruptAttr::qcinonest: {1688 if (!HasFeature("experimental-xqciint")) {1689 Diag(AL.getLoc(),1690 diag::err_riscv_attribute_interrupt_requires_extension)1691 << RISCVInterruptAttr::ConvertInterruptTypeToStr(Type) << "Xqciint";1692 return;1693 }1694 } break;1695 // The SiFive CLIC interrupt types require Xsfmclic1696 case RISCVInterruptAttr::SiFiveCLICPreemptible:1697 case RISCVInterruptAttr::SiFiveCLICStackSwap: {1698 if (!HasFeature("experimental-xsfmclic")) {1699 Diag(AL.getLoc(),1700 diag::err_riscv_attribute_interrupt_requires_extension)1701 << RISCVInterruptAttr::ConvertInterruptTypeToStr(Type)1702 << "XSfmclic";1703 return;1704 }1705 } break;1706 case RISCVInterruptAttr::rnmi: {1707 if (!HasFeature("smrnmi")) {1708 Diag(AL.getLoc(),1709 diag::err_riscv_attribute_interrupt_requires_extension)1710 << RISCVInterruptAttr::ConvertInterruptTypeToStr(Type) << "Smrnmi";1711 return;1712 }1713 } break;1714 default:1715 break;1716 }1717 }1718 1719 SmallVector<RISCVInterruptAttr::InterruptType, 2> TypesVec(Types.begin(),1720 Types.end());1721 1722 D->addAttr(::new (getASTContext()) RISCVInterruptAttr(1723 getASTContext(), AL, TypesVec.data(), TypesVec.size()));1724}1725 1726bool SemaRISCV::isAliasValid(unsigned BuiltinID, StringRef AliasName) {1727 return BuiltinID >= RISCV::FirstRVVBuiltin &&1728 BuiltinID <= RISCV::LastRVVBuiltin;1729}1730 1731bool SemaRISCV::isValidFMVExtension(StringRef Ext) {1732 if (Ext.empty())1733 return false;1734 1735 if (!Ext.consume_front("+"))1736 return false;1737 1738 return -1 != RISCVISAInfo::getRISCVFeaturesBitsInfo(Ext).second;1739}1740 1741bool SemaRISCV::checkTargetVersionAttr(const StringRef Param,1742 const SourceLocation Loc) {1743 using namespace DiagAttrParams;1744 1745 llvm::SmallVector<StringRef, 8> AttrStrs;1746 Param.split(AttrStrs, ';');1747 1748 bool HasArch = false;1749 bool HasPriority = false;1750 bool HasDefault = false;1751 bool DuplicateAttr = false;1752 for (StringRef AttrStr : AttrStrs) {1753 AttrStr = AttrStr.trim();1754 // Only support arch=+ext,... syntax.1755 if (AttrStr.starts_with("arch=+")) {1756 DuplicateAttr = HasArch;1757 HasArch = true;1758 ParsedTargetAttr TargetAttr =1759 getASTContext().getTargetInfo().parseTargetAttr(AttrStr);1760 1761 if (TargetAttr.Features.empty() ||1762 llvm::any_of(TargetAttr.Features, [&](const StringRef Ext) {1763 return !isValidFMVExtension(Ext);1764 }))1765 return Diag(Loc, diag::warn_unsupported_target_attribute)1766 << Unsupported << None << AttrStr << TargetVersion;1767 } else if (AttrStr == "default") {1768 DuplicateAttr = HasDefault;1769 HasDefault = true;1770 } else if (AttrStr.consume_front("priority=")) {1771 DuplicateAttr = HasPriority;1772 HasPriority = true;1773 unsigned Digit;1774 if (AttrStr.getAsInteger(0, Digit))1775 return Diag(Loc, diag::warn_unsupported_target_attribute)1776 << Unsupported << None << AttrStr << TargetVersion;1777 } else {1778 return Diag(Loc, diag::warn_unsupported_target_attribute)1779 << Unsupported << None << AttrStr << TargetVersion;1780 }1781 }1782 1783 if (((HasPriority || HasArch) && HasDefault) || DuplicateAttr ||1784 (HasPriority && !HasArch))1785 return Diag(Loc, diag::warn_unsupported_target_attribute)1786 << Unsupported << None << Param << TargetVersion;1787 1788 return false;1789}1790 1791bool SemaRISCV::checkTargetClonesAttr(1792 SmallVectorImpl<StringRef> &Params, SmallVectorImpl<SourceLocation> &Locs,1793 SmallVectorImpl<SmallString<64>> &NewParams) {1794 using namespace DiagAttrParams;1795 1796 assert(Params.size() == Locs.size() &&1797 "Mismatch between number of string parameters and locations");1798 1799 bool HasDefault = false;1800 for (unsigned I = 0, E = Params.size(); I < E; ++I) {1801 const StringRef Param = Params[I].trim();1802 const SourceLocation &Loc = Locs[I];1803 1804 llvm::SmallVector<StringRef, 8> AttrStrs;1805 Param.split(AttrStrs, ';');1806 1807 bool IsPriority = false;1808 bool IsDefault = false;1809 for (StringRef AttrStr : AttrStrs) {1810 AttrStr = AttrStr.trim();1811 // Only support arch=+ext,... syntax.1812 if (AttrStr.starts_with("arch=+")) {1813 ParsedTargetAttr TargetAttr =1814 getASTContext().getTargetInfo().parseTargetAttr(AttrStr);1815 1816 if (TargetAttr.Features.empty() ||1817 llvm::any_of(TargetAttr.Features, [&](const StringRef Ext) {1818 return !isValidFMVExtension(Ext);1819 }))1820 return Diag(Loc, diag::warn_unsupported_target_attribute)1821 << Unsupported << None << Param << TargetClones;1822 } else if (AttrStr == "default") {1823 IsDefault = true;1824 HasDefault = true;1825 } else if (AttrStr.consume_front("priority=")) {1826 IsPriority = true;1827 unsigned Digit;1828 if (AttrStr.getAsInteger(0, Digit))1829 return Diag(Loc, diag::warn_unsupported_target_attribute)1830 << Unsupported << None << Param << TargetClones;1831 } else {1832 return Diag(Loc, diag::warn_unsupported_target_attribute)1833 << Unsupported << None << Param << TargetClones;1834 }1835 }1836 1837 if (IsPriority && IsDefault)1838 return Diag(Loc, diag::warn_unsupported_target_attribute)1839 << Unsupported << None << Param << TargetClones;1840 1841 if (llvm::is_contained(NewParams, Param))1842 Diag(Loc, diag::warn_target_clone_duplicate_options);1843 NewParams.push_back(Param);1844 }1845 if (!HasDefault)1846 return Diag(Locs[0], diag::err_target_clone_must_have_default);1847 1848 return false;1849}1850 1851SemaRISCV::SemaRISCV(Sema &S) : SemaBase(S) {}1852 1853} // namespace clang1854