775 lines · cpp
1// RUN: %clang_cc1 -std=c++11 -triple x86_64-unknown-linux-gnu -Wno-unused-value -fclangir -emit-cir %s -o %t.cir2// RUN: FileCheck --input-file=%t.cir %s -check-prefix=CIR3// RUN: %clang_cc1 -std=c++11 -triple x86_64-unknown-linux-gnu -Wno-unused-value -fclangir -emit-llvm %s -o %t-cir.ll4// RUN: FileCheck --input-file=%t-cir.ll %s -check-prefix=LLVM5// RUN: %clang_cc1 -std=c++11 -triple x86_64-unknown-linux-gnu -Wno-unused-value -emit-llvm %s -o %t.ll6// RUN: FileCheck --input-file=%t.ll %s -check-prefix=OGCG7 8void b0(int a, int b) {9 int x = a * b;10 x = x / b;11 x = x % b;12 x = x + b;13 x = x - b;14 x = x & b;15 x = x ^ b;16 x = x | b;17}18 19// CIR-LABEL: cir.func{{.*}} @_Z2b0ii(20// CIR: %{{.+}} = cir.binop(mul, %{{.+}}, %{{.+}}) nsw : !s32i21// CIR: %{{.+}} = cir.binop(div, %{{.+}}, %{{.+}}) : !s32i22// CIR: %{{.+}} = cir.binop(rem, %{{.+}}, %{{.+}}) : !s32i23// CIR: %{{.+}} = cir.binop(add, %{{.+}}, %{{.+}}) nsw : !s32i24// CIR: %{{.+}} = cir.binop(sub, %{{.+}}, %{{.+}}) nsw : !s32i25// CIR: %{{.+}} = cir.binop(and, %{{.+}}, %{{.+}}) : !s32i26// CIR: %{{.+}} = cir.binop(xor, %{{.+}}, %{{.+}}) : !s32i27// CIR: %{{.+}} = cir.binop(or, %{{.+}}, %{{.+}}) : !s32i28// CIR: cir.return29 30// LLVM-LABEL: define{{.*}} void @_Z2b0ii(31// LLVM-SAME: i32 %[[A:.*]], i32 %[[B:.*]])32// LLVM: %[[A_ADDR:.*]] = alloca i3233// LLVM: %[[B_ADDR:.*]] = alloca i3234// LLVM: %[[X:.*]] = alloca i3235// LLVM: store i32 %[[A]], ptr %[[A_ADDR]]36// LLVM: store i32 %[[B]], ptr %[[B_ADDR]]37 38// LLVM: %[[A:.*]] = load i32, ptr %[[A_ADDR]]39// LLVM: %[[B:.*]] = load i32, ptr %[[B_ADDR]]40// LLVM: %[[MUL:.*]] = mul nsw i32 %[[A]], %[[B]]41// LLVM: store i32 %[[MUL]], ptr %[[X]]42 43// LLVM: %[[X1:.*]] = load i32, ptr %[[X]]44// LLVM: %[[B1:.*]] = load i32, ptr %[[B_ADDR]]45// LLVM: %[[DIV:.*]] = sdiv i32 %[[X1]], %[[B1]]46// LLVM: store i32 %[[DIV]], ptr %[[X]]47 48// LLVM: %[[X2:.*]] = load i32, ptr %[[X]]49// LLVM: %[[B2:.*]] = load i32, ptr %[[B_ADDR]]50// LLVM: %[[REM:.*]] = srem i32 %[[X2]], %[[B2]]51// LLVM: store i32 %[[REM]], ptr %[[X]]52 53// LLVM: %[[X3:.*]] = load i32, ptr %[[X]]54// LLVM: %[[B3:.*]] = load i32, ptr %[[B_ADDR]]55// LLVM: %[[ADD:.*]] = add nsw i32 %[[X3]], %[[B3]]56// LLVM: store i32 %[[ADD]], ptr %[[X]]57 58// LLVM: %[[X4:.*]] = load i32, ptr %[[X]]59// LLVM: %[[B4:.*]] = load i32, ptr %[[B_ADDR]]60// LLVM: %[[SUB:.*]] = sub nsw i32 %[[X4]], %[[B4]]61// LLVM: store i32 %[[SUB]], ptr %[[X]]62 63// LLVM: %[[X5:.*]] = load i32, ptr %[[X]]64// LLVM: %[[B5:.*]] = load i32, ptr %[[B_ADDR]]65// LLVM: %[[AND:.*]] = and i32 %[[X5]], %[[B5]]66// LLVM: store i32 %[[AND]], ptr %[[X]]67 68// LLVM: %[[X6:.*]] = load i32, ptr %[[X]]69// LLVM: %[[B6:.*]] = load i32, ptr %[[B_ADDR]]70// LLVM: %[[XOR:.*]] = xor i32 %[[X6]], %[[B6]]71// LLVM: store i32 %[[XOR]], ptr %[[X]]72 73// LLVM: %[[X7:.*]] = load i32, ptr %[[X]]74// LLVM: %[[B7:.*]] = load i32, ptr %[[B_ADDR]]75// LLVM: %[[OR:.*]] = or i32 %[[X7]], %[[B7]]76// LLVM: store i32 %[[OR]], ptr %[[X]]77 78// LLVM: ret void79 80// OGCG-LABEL: define{{.*}} void @_Z2b0ii(i32 {{.*}} %a, i32 {{.*}} %b) {{.*}} { 81// OGCG: %[[A_ADDR:.*]] = alloca i3282// OGCG: %[[B_ADDR:.*]] = alloca i3283// OGCG: %[[X:.*]] = alloca i3284// OGCG: store i32 %a, ptr %[[A_ADDR]]85// OGCG: store i32 %b, ptr %[[B_ADDR]]86 87// OGCG: %[[A:.*]] = load i32, ptr %[[A_ADDR]]88// OGCG: %[[B:.*]] = load i32, ptr %[[B_ADDR]]89// OGCG: %[[MUL:.*]] = mul nsw i32 %[[A]], %[[B]]90// OGCG: store i32 %[[MUL]], ptr %[[X]]91 92// OGCG: %[[X1:.*]] = load i32, ptr %[[X]]93// OGCG: %[[B1:.*]] = load i32, ptr %[[B_ADDR]]94// OGCG: %[[DIV:.*]] = sdiv i32 %[[X1]], %[[B1]]95// OGCG: store i32 %[[DIV]], ptr %[[X]]96 97// OGCG: %[[X2:.*]] = load i32, ptr %[[X]]98// OGCG: %[[B2:.*]] = load i32, ptr %[[B_ADDR]]99// OGCG: %[[REM:.*]] = srem i32 %[[X2]], %[[B2]]100// OGCG: store i32 %[[REM]], ptr %[[X]]101 102// OGCG: %[[X3:.*]] = load i32, ptr %[[X]]103// OGCG: %[[B3:.*]] = load i32, ptr %[[B_ADDR]]104// OGCG: %[[ADD:.*]] = add nsw i32 %[[X3]], %[[B3]]105// OGCG: store i32 %[[ADD]], ptr %[[X]]106 107// OGCG: %[[X4:.*]] = load i32, ptr %[[X]]108// OGCG: %[[B4:.*]] = load i32, ptr %[[B_ADDR]]109// OGCG: %[[SUB:.*]] = sub nsw i32 %[[X4]], %[[B4]]110// OGCG: store i32 %[[SUB]], ptr %[[X]]111 112// OGCG: %[[X5:.*]] = load i32, ptr %[[X]]113// OGCG: %[[B5:.*]] = load i32, ptr %[[B_ADDR]]114// OGCG: %[[AND:.*]] = and i32 %[[X5]], %[[B5]]115// OGCG: store i32 %[[AND]], ptr %[[X]]116 117// OGCG: %[[X6:.*]] = load i32, ptr %[[X]]118// OGCG: %[[B6:.*]] = load i32, ptr %[[B_ADDR]]119// OGCG: %[[XOR:.*]] = xor i32 %[[X6]], %[[B6]]120// OGCG: store i32 %[[XOR]], ptr %[[X]]121 122// OGCG: %[[X7:.*]] = load i32, ptr %[[X]]123// OGCG: %[[B7:.*]] = load i32, ptr %[[B_ADDR]]124// OGCG: %[[OR:.*]] = or i32 %[[X7]], %[[B7]]125// OGCG: store i32 %[[OR]], ptr %[[X]]126 127// OGCG: ret void128 129void testFloatingPointBinOps(float a, float b) {130 a * b;131 a / b;132 a + b;133 a - b;134}135 136// CIR-LABEL: cir.func{{.*}} @_Z23testFloatingPointBinOpsff(137// CIR: cir.binop(mul, %{{.+}}, %{{.+}}) : !cir.float138// CIR: cir.binop(div, %{{.+}}, %{{.+}}) : !cir.float139// CIR: cir.binop(add, %{{.+}}, %{{.+}}) : !cir.float140// CIR: cir.binop(sub, %{{.+}}, %{{.+}}) : !cir.float141// CIR: cir.return142 143// LLVM-LABEL: define{{.*}} void @_Z23testFloatingPointBinOpsff(144// LLVM-SAME: float %[[A:.*]], float %[[B:.*]])145// LLVM: %[[A_ADDR:.*]] = alloca float, i64 1146// LLVM: %[[B_ADDR:.*]] = alloca float, i64 1147// LLVM: store float %[[A]], ptr %[[A_ADDR]]148// LLVM: store float %[[B]], ptr %[[B_ADDR]]149 150// LLVM: %[[A1:.*]] = load float, ptr %[[A_ADDR]]151// LLVM: %[[B1:.*]] = load float, ptr %[[B_ADDR]]152// LLVM: fmul float %[[A1]], %[[B1]]153 154// LLVM: %[[A2:.*]] = load float, ptr %[[A_ADDR]]155// LLVM: %[[B2:.*]] = load float, ptr %[[B_ADDR]]156// LLVM: fdiv float %[[A2]], %[[B2]]157 158// LLVM: %[[A3:.*]] = load float, ptr %[[A_ADDR]]159// LLVM: %[[B3:.*]] = load float, ptr %[[B_ADDR]]160// LLVM: fadd float %[[A3]], %[[B3]]161 162// LLVM: %[[A4:.*]] = load float, ptr %[[A_ADDR]]163// LLVM: %[[B4:.*]] = load float, ptr %[[B_ADDR]]164// LLVM: fsub float %[[A4]], %[[B4]]165 166// LLVM: ret void167 168// OGCG-LABEL: define{{.*}} void @_Z23testFloatingPointBinOpsff(float {{.*}} %a, float {{.*}} %b)169// OGCG: %a.addr = alloca float170// OGCG: %b.addr = alloca float171// OGCG: store float %a, ptr %a.addr172// OGCG: store float %b, ptr %b.addr173 174// OGCG: %[[A1:.*]] = load float, ptr %a.addr175// OGCG: %[[B1:.*]] = load float, ptr %b.addr176// OGCG: fmul float %[[A1]], %[[B1]]177 178// OGCG: %[[A2:.*]] = load float, ptr %a.addr179// OGCG: %[[B2:.*]] = load float, ptr %b.addr180// OGCG: fdiv float %[[A2]], %[[B2]]181 182// OGCG: %[[A3:.*]] = load float, ptr %a.addr183// OGCG: %[[B3:.*]] = load float, ptr %b.addr184// OGCG: fadd float %[[A3]], %[[B3]]185 186// OGCG: %[[A4:.*]] = load float, ptr %a.addr187// OGCG: %[[B4:.*]] = load float, ptr %b.addr188// OGCG: fsub float %[[A4]], %[[B4]]189 190// OGCG: ret void191 192void signed_shift(int a, int b) {193 int x = a >> b;194 x = a << b;195}196 197// CIR-LABEL: cir.func{{.*}} @_Z12signed_shiftii(198// CIR-SAME: %[[ARG0:.*]]: !s32i{{.*}}, %[[ARG1:.*]]: !s32i{{.*}})199// CIR: %[[A_PTR:.*]] = cir.alloca !s32i, !cir.ptr<!s32i>, ["a", init]200// CIR: %[[B_PTR:.*]] = cir.alloca !s32i, !cir.ptr<!s32i>, ["b", init]201// CIR: %[[X_PTR:.*]] = cir.alloca !s32i, !cir.ptr<!s32i>, ["x", init]202 203// CIR: cir.store{{.*}} %[[ARG0]], %[[A_PTR]] : !s32i, !cir.ptr<!s32i>204// CIR: cir.store{{.*}} %[[ARG1]], %[[B_PTR]] : !s32i, !cir.ptr<!s32i>205 206// CIR: %[[A1:.*]] = cir.load{{.*}} %[[A_PTR]] : !cir.ptr<!s32i>, !s32i207// CIR: %[[B1:.*]] = cir.load{{.*}} %[[B_PTR]] : !cir.ptr<!s32i>, !s32i208// CIR: %[[ASHR:.*]] = cir.shift(right, %[[A1]] : !s32i, %[[B1]] : !s32i) -> !s32i209// CIR: cir.store{{.*}} %[[ASHR]], %[[X_PTR]] : !s32i, !cir.ptr<!s32i>210 211// CIR: %[[A2:.*]] = cir.load{{.*}} %[[A_PTR]] : !cir.ptr<!s32i>, !s32i212// CIR: %[[B2:.*]] = cir.load{{.*}} %[[B_PTR]] : !cir.ptr<!s32i>, !s32i213// CIR: %[[SHL:.*]] = cir.shift(left, %[[A2]] : !s32i, %[[B2]] : !s32i) -> !s32i214// CIR: cir.store{{.*}} %[[SHL]], %[[X_PTR]] : !s32i, !cir.ptr<!s32i>215 216// CIR: cir.return217 218// LLVM-LABEL: define{{.*}} void @_Z12signed_shiftii219// LLVM-SAME: (i32 %[[A:.*]], i32 %[[B:.*]])220// LLVM: %[[A_ADDR:.*]] = alloca i32221// LLVM: %[[B_ADDR:.*]] = alloca i32222// LLVM: %[[X:.*]] = alloca i32223// LLVM: store i32 %[[A]], ptr %[[A_ADDR]]224// LLVM: store i32 %[[B]], ptr %[[B_ADDR]]225 226// LLVM: %[[A1:.*]] = load i32, ptr %[[A_ADDR]]227// LLVM: %[[B1:.*]] = load i32, ptr %[[B_ADDR]]228// LLVM: %[[ASHR:.*]] = ashr i32 %[[A1]], %[[B1]]229// LLVM: store i32 %[[ASHR]], ptr %[[X]]230 231// LLVM: %[[A2:.*]] = load i32, ptr %[[A_ADDR]]232// LLVM: %[[B2:.*]] = load i32, ptr %[[B_ADDR]]233// LLVM: %[[SHL:.*]] = shl i32 %[[A2]], %[[B2]]234// LLVM: store i32 %[[SHL]], ptr %[[X]]235 236// LLVM: ret void237 238// OGCG-LABEL: define{{.*}} void @_Z12signed_shiftii239// OGCG-SAME: (i32 {{.*}} %[[A:.*]], i32 {{.*}} %[[B:.*]])240// OGCG: %[[A_ADDR:.*]] = alloca i32241// OGCG: %[[B_ADDR:.*]] = alloca i32242// OGCG: %[[X:.*]] = alloca i32243// OGCG: store i32 %[[A]], ptr %[[A_ADDR]]244// OGCG: store i32 %[[B]], ptr %[[B_ADDR]]245 246// OGCG: %[[A1:.*]] = load i32, ptr %[[A_ADDR]]247// OGCG: %[[B1:.*]] = load i32, ptr %[[B_ADDR]]248// OGCG: %[[ASHR:.*]] = ashr i32 %[[A1]], %[[B1]]249// OGCG: store i32 %[[ASHR]], ptr %[[X]]250 251// OGCG: %[[A2:.*]] = load i32, ptr %[[A_ADDR]]252// OGCG: %[[B2:.*]] = load i32, ptr %[[B_ADDR]]253// OGCG: %[[SHL:.*]] = shl i32 %[[A2]], %[[B2]]254// OGCG: store i32 %[[SHL]], ptr %[[X]]255 256// OGCG: ret void257 258void unsigned_shift(unsigned a, unsigned b) {259 unsigned x = a >> b;260 x = a << b;261}262 263// CIR-LABEL: cir.func{{.*}} @_Z14unsigned_shiftjj(264// CIR-SAME: %[[ARG0:.*]]: !u32i{{.*}}, %[[ARG1:.*]]: !u32i{{.*}})265// CIR: %[[A_PTR:.*]] = cir.alloca !u32i, !cir.ptr<!u32i>, ["a", init]266// CIR: %[[B_PTR:.*]] = cir.alloca !u32i, !cir.ptr<!u32i>, ["b", init]267// CIR: %[[X_PTR:.*]] = cir.alloca !u32i, !cir.ptr<!u32i>, ["x", init]268 269// CIR: cir.store{{.*}} %[[ARG0]], %[[A_PTR]] : !u32i, !cir.ptr<!u32i>270// CIR: cir.store{{.*}} %[[ARG1]], %[[B_PTR]] : !u32i, !cir.ptr<!u32i>271 272// CIR: %[[A1:.*]] = cir.load{{.*}} %[[A_PTR]] : !cir.ptr<!u32i>, !u32i273// CIR: %[[B1:.*]] = cir.load{{.*}} %[[B_PTR]] : !cir.ptr<!u32i>, !u32i274// CIR: %[[ASHR:.*]] = cir.shift(right, %[[A1]] : !u32i, %[[B1]] : !u32i) -> !u32i275// CIR: cir.store{{.*}} %[[ASHR]], %[[X_PTR]] : !u32i, !cir.ptr<!u32i>276 277// CIR: %[[A2:.*]] = cir.load{{.*}} %[[A_PTR]] : !cir.ptr<!u32i>, !u32i278// CIR: %[[B2:.*]] = cir.load{{.*}} %[[B_PTR]] : !cir.ptr<!u32i>, !u32i279// CIR: %[[SHL:.*]] = cir.shift(left, %[[A2]] : !u32i, %[[B2]] : !u32i) -> !u32i280// CIR: cir.store{{.*}} %[[SHL]], %[[X_PTR]] : !u32i, !cir.ptr<!u32i>281 282// CIR: cir.return283 284// LLVM-LABEL: define{{.*}} void @_Z14unsigned_shiftjj285// LLVM-SAME: (i32 %[[A:.*]], i32 %[[B:.*]])286// LLVM: %[[A_ADDR:.*]] = alloca i32287// LLVM: %[[B_ADDR:.*]] = alloca i32288// LLVM: %[[X:.*]] = alloca i32289// LLVM: store i32 %[[A]], ptr %[[A_ADDR]]290// LLVM: store i32 %[[B]], ptr %[[B_ADDR]]291 292// LLVM: %[[A1:.*]] = load i32, ptr %[[A_ADDR]]293// LLVM: %[[B1:.*]] = load i32, ptr %[[B_ADDR]]294// LLVM: %[[ASHR:.*]] = lshr i32 %[[A1]], %[[B1]]295// LLVM: store i32 %[[ASHR]], ptr %[[X]]296 297// LLVM: %[[A2:.*]] = load i32, ptr %[[A_ADDR]]298// LLVM: %[[B2:.*]] = load i32, ptr %[[B_ADDR]]299// LLVM: %[[SHL:.*]] = shl i32 %[[A2]], %[[B2]]300// LLVM: store i32 %[[SHL]], ptr %[[X]]301 302// LLVM: ret void303 304// OGCG-LABEL: define{{.*}} void @_Z14unsigned_shiftjj305// OGCG-SAME: (i32 {{.*}} %[[A:.*]], i32 {{.*}} %[[B:.*]])306// OGCG: %[[A_ADDR:.*]] = alloca i32307// OGCG: %[[B_ADDR:.*]] = alloca i32308// OGCG: %[[X:.*]] = alloca i32309// OGCG: store i32 %[[A]], ptr %[[A_ADDR]]310// OGCG: store i32 %[[B]], ptr %[[B_ADDR]]311 312// OGCG: %[[A1:.*]] = load i32, ptr %[[A_ADDR]]313// OGCG: %[[B1:.*]] = load i32, ptr %[[B_ADDR]]314// OGCG: %[[ASHR:.*]] = lshr i32 %[[A1]], %[[B1]]315// OGCG: store i32 %[[ASHR]], ptr %[[X]]316 317// OGCG: %[[A2:.*]] = load i32, ptr %[[A_ADDR]]318// OGCG: %[[B2:.*]] = load i32, ptr %[[B_ADDR]]319// OGCG: %[[SHL:.*]] = shl i32 %[[A2]], %[[B2]]320// OGCG: store i32 %[[SHL]], ptr %[[X]]321 322// OGCG: ret void323 324void zext_shift_example(int a, unsigned char b) {325 int x = a >> b;326 x = a << b;327}328 329// CIR-LABEL: cir.func{{.*}} @_Z18zext_shift_exampleih(330// CIR-SAME: %[[ARG0:.*]]: !s32i{{.*}}, %[[ARG1:.*]]: !u8i{{.*}})331// CIR: %[[A_PTR:.*]] = cir.alloca !s32i, !cir.ptr<!s32i>, ["a", init]332// CIR: %[[B_PTR:.*]] = cir.alloca !u8i, !cir.ptr<!u8i>, ["b", init]333// CIR: %[[X_PTR:.*]] = cir.alloca !s32i, !cir.ptr<!s32i>, ["x", init]334 335// CIR: cir.store{{.*}} %[[ARG0]], %[[A_PTR]] : !s32i, !cir.ptr<!s32i>336// CIR: cir.store{{.*}} %[[ARG1]], %[[B_PTR]] : !u8i, !cir.ptr<!u8i>337 338// CIR: %[[A1:.*]] = cir.load{{.*}} %[[A_PTR]] : !cir.ptr<!s32i>, !s32i339// CIR: %[[B1:.*]] = cir.load{{.*}} %[[B_PTR]] : !cir.ptr<!u8i>, !u8i340// CIR: %[[B1_EXT:.*]] = cir.cast integral %[[B1]] : !u8i -> !s32i341// CIR: %[[ASHR:.*]] = cir.shift(right, %[[A1]] : !s32i, %[[B1_EXT]] : !s32i) -> !s32i342// CIR: cir.store{{.*}} %[[ASHR]], %[[X_PTR]] : !s32i, !cir.ptr<!s32i>343 344// CIR: %[[A2:.*]] = cir.load{{.*}} %[[A_PTR]] : !cir.ptr<!s32i>, !s32i345// CIR: %[[B2:.*]] = cir.load{{.*}} %[[B_PTR]] : !cir.ptr<!u8i>, !u8i346// CIR: %[[B2_EXT:.*]] = cir.cast integral %[[B2]] : !u8i -> !s32i347// CIR: %[[SHL:.*]] = cir.shift(left, %[[A2]] : !s32i, %[[B2_EXT]] : !s32i) -> !s32i348// CIR: cir.store{{.*}} %[[SHL]], %[[X_PTR]] : !s32i, !cir.ptr<!s32i>349 350// CIR: cir.return351 352// LLVM-LABEL: define{{.*}} void @_Z18zext_shift_exampleih353// LLVM-SAME: (i32 %[[A:.*]], i8 %[[B:.*]])354// LLVM: %[[A_ADDR:.*]] = alloca i32355// LLVM: %[[B_ADDR:.*]] = alloca i8356// LLVM: %[[X:.*]] = alloca i32357// LLVM: store i32 %[[A]], ptr %[[A_ADDR]]358// LLVM: store i8 %[[B]], ptr %[[B_ADDR]]359 360// LLVM: %[[A1:.*]] = load i32, ptr %[[A_ADDR]]361// LLVM: %[[B1:.*]] = load i8, ptr %[[B_ADDR]]362// LLVM: %[[B1_EXT:.*]] = zext i8 %[[B1]] to i32363// LLVM: %[[ASHR:.*]] = ashr i32 %[[A1]], %[[B1_EXT]]364// LLVM: store i32 %[[ASHR]], ptr %[[X]]365 366// LLVM: %[[A2:.*]] = load i32, ptr %[[A_ADDR]]367// LLVM: %[[B2:.*]] = load i8, ptr %[[B_ADDR]]368// LLVM: %[[B2_EXT:.*]] = zext i8 %[[B2]] to i32369// LLVM: %[[SHL:.*]] = shl i32 %[[A2]], %[[B2_EXT]]370// LLVM: store i32 %[[SHL]], ptr %[[X]]371 372// LLVM: ret void373 374// OGCG-LABEL: define{{.*}} void @_Z18zext_shift_exampleih375// OGCG-SAME: (i32 {{.*}} %[[A:.*]], i8 {{.*}} %[[B:.*]])376// OGCG: %[[A_ADDR:.*]] = alloca i32377// OGCG: %[[B_ADDR:.*]] = alloca i8378// OGCG: %[[X:.*]] = alloca i32379// OGCG: store i32 %[[A]], ptr %[[A_ADDR]]380// OGCG: store i8 %[[B]], ptr %[[B_ADDR]]381 382// OGCG: %[[A1:.*]] = load i32, ptr %[[A_ADDR]]383// OGCG: %[[B1:.*]] = load i8, ptr %[[B_ADDR]]384// OGCG: %[[B1_EXT:.*]] = zext i8 %[[B1]] to i32385// OGCG: %[[ASHR:.*]] = ashr i32 %[[A1]], %[[B1_EXT]]386// OGCG: store i32 %[[ASHR]], ptr %[[X]]387 388// OGCG: %[[A2:.*]] = load i32, ptr %[[A_ADDR]]389// OGCG: %[[B2:.*]] = load i8, ptr %[[B_ADDR]]390// OGCG: %[[B2_EXT:.*]] = zext i8 %[[B2]] to i32391// OGCG: %[[SHL:.*]] = shl i32 %[[A2]], %[[B2_EXT]]392// OGCG: store i32 %[[SHL]], ptr %[[X]]393 394// OGCG: ret void395 396void sext_shift_example(int a, signed char b) {397 int x = a >> b;398 x = a << b;399}400 401// CIR-LABEL: cir.func{{.*}} @_Z18sext_shift_exampleia(402// CIR-SAME: %[[ARG0:.*]]: !s32i{{.*}}, %[[ARG1:.*]]: !s8i{{.*}})403// CIR: %[[A_PTR:.*]] = cir.alloca !s32i, !cir.ptr<!s32i>, ["a", init]404// CIR: %[[B_PTR:.*]] = cir.alloca !s8i, !cir.ptr<!s8i>, ["b", init]405// CIR: %[[X_PTR:.*]] = cir.alloca !s32i, !cir.ptr<!s32i>, ["x", init]406 407// CIR: cir.store{{.*}} %[[ARG0]], %[[A_PTR]] : !s32i, !cir.ptr<!s32i>408// CIR: cir.store{{.*}} %[[ARG1]], %[[B_PTR]] : !s8i, !cir.ptr<!s8i>409 410// CIR: %[[A1:.*]] = cir.load{{.*}} %[[A_PTR]] : !cir.ptr<!s32i>, !s32i411// CIR: %[[B1:.*]] = cir.load{{.*}} %[[B_PTR]] : !cir.ptr<!s8i>, !s8i412// CIR: %[[B1_EXT:.*]] = cir.cast integral %[[B1]] : !s8i -> !s32i413// CIR: %[[ASHR:.*]] = cir.shift(right, %[[A1]] : !s32i, %[[B1_EXT]] : !s32i) -> !s32i414// CIR: cir.store{{.*}} %[[ASHR]], %[[X_PTR]] : !s32i, !cir.ptr<!s32i>415 416// CIR: %[[A2:.*]] = cir.load{{.*}} %[[A_PTR]] : !cir.ptr<!s32i>, !s32i417// CIR: %[[B2:.*]] = cir.load{{.*}} %[[B_PTR]] : !cir.ptr<!s8i>, !s8i418// CIR: %[[B2_EXT:.*]] = cir.cast integral %[[B2]] : !s8i -> !s32i419// CIR: %[[SHL:.*]] = cir.shift(left, %[[A2]] : !s32i, %[[B2_EXT]] : !s32i) -> !s32i420// CIR: cir.store{{.*}} %[[SHL]], %[[X_PTR]] : !s32i, !cir.ptr<!s32i>421 422// CIR: cir.return423 424// LLVM-LABEL: define{{.*}} void @_Z18sext_shift_exampleia425// LLVM-SAME: (i32 %[[A:.*]], i8 %[[B:.*]])426// LLVM: %[[A_ADDR:.*]] = alloca i32427// LLVM: %[[B_ADDR:.*]] = alloca i8428// LLVM: %[[X:.*]] = alloca i32429// LLVM: store i32 %[[A]], ptr %[[A_ADDR]]430// LLVM: store i8 %[[B]], ptr %[[B_ADDR]]431 432// LLVM: %[[A1:.*]] = load i32, ptr %[[A_ADDR]]433// LLVM: %[[B1:.*]] = load i8, ptr %[[B_ADDR]]434// LLVM: %[[B1_EXT:.*]] = sext i8 %[[B1]] to i32435// LLVM: %[[ASHR:.*]] = ashr i32 %[[A1]], %[[B1_EXT]]436// LLVM: store i32 %[[ASHR]], ptr %[[X]]437 438// LLVM: %[[A2:.*]] = load i32, ptr %[[A_ADDR]]439// LLVM: %[[B2:.*]] = load i8, ptr %[[B_ADDR]]440// LLVM: %[[B2_EXT:.*]] = sext i8 %[[B2]] to i32441// LLVM: %[[SHL:.*]] = shl i32 %[[A2]], %[[B2_EXT]]442// LLVM: store i32 %[[SHL]], ptr %[[X]]443 444// LLVM: ret void445 446// OGCG-LABEL: define{{.*}} void @_Z18sext_shift_exampleia447// OGCG-SAME: (i32 {{.*}} %[[A:.*]], i8 {{.*}} %[[B:.*]])448// OGCG: %[[A_ADDR:.*]] = alloca i32449// OGCG: %[[B_ADDR:.*]] = alloca i8450// OGCG: %[[X:.*]] = alloca i32451// OGCG: store i32 %[[A]], ptr %[[A_ADDR]]452// OGCG: store i8 %[[B]], ptr %[[B_ADDR]]453 454// OGCG: %[[A1:.*]] = load i32, ptr %[[A_ADDR]]455// OGCG: %[[B1:.*]] = load i8, ptr %[[B_ADDR]]456// OGCG: %[[B1_EXT:.*]] = sext i8 %[[B1]] to i32457// OGCG: %[[ASHR:.*]] = ashr i32 %[[A1]], %[[B1_EXT]]458// OGCG: store i32 %[[ASHR]], ptr %[[X]]459 460// OGCG: %[[A2:.*]] = load i32, ptr %[[A_ADDR]]461// OGCG: %[[B2:.*]] = load i8, ptr %[[B_ADDR]]462// OGCG: %[[B2_EXT:.*]] = sext i8 %[[B2]] to i32463// OGCG: %[[SHL:.*]] = shl i32 %[[A2]], %[[B2_EXT]]464// OGCG: store i32 %[[SHL]], ptr %[[X]]465 466// OGCG: ret void467 468void long_shift_example(long long a, short b) {469 long long x = a >> b;470 x = a << b;471}472 473// CIR-LABEL: cir.func{{.*}} @_Z18long_shift_examplexs(474// CIR-SAME: %[[ARG0:.*]]: !s64i{{.*}}, %[[ARG1:.*]]: !s16i{{.*}})475// CIR: %[[A_PTR:.*]] = cir.alloca !s64i, !cir.ptr<!s64i>, ["a", init]476// CIR: %[[B_PTR:.*]] = cir.alloca !s16i, !cir.ptr<!s16i>, ["b", init]477// CIR: %[[X_PTR:.*]] = cir.alloca !s64i, !cir.ptr<!s64i>, ["x", init]478 479// CIR: cir.store{{.*}} %[[ARG0]], %[[A_PTR]] : !s64i, !cir.ptr<!s64i>480// CIR: cir.store{{.*}} %[[ARG1]], %[[B_PTR]] : !s16i, !cir.ptr<!s16i>481 482// CIR: %[[A1:.*]] = cir.load{{.*}} %[[A_PTR]] : !cir.ptr<!s64i>, !s64i483// CIR: %[[B1:.*]] = cir.load{{.*}} %[[B_PTR]] : !cir.ptr<!s16i>, !s16i484// CIR: %[[B1_EXT:.*]] = cir.cast integral %[[B1]] : !s16i -> !s32i485// CIR: %[[ASHR:.*]] = cir.shift(right, %[[A1]] : !s64i, %[[B1_EXT]] : !s32i) -> !s64i486// CIR: cir.store{{.*}} %[[ASHR]], %[[X_PTR]] : !s64i, !cir.ptr<!s64i>487 488// CIR: %[[A2:.*]] = cir.load{{.*}} %[[A_PTR]] : !cir.ptr<!s64i>, !s64i489// CIR: %[[B2:.*]] = cir.load{{.*}} %[[B_PTR]] : !cir.ptr<!s16i>, !s16i490// CIR: %[[B2_EXT:.*]] = cir.cast integral %[[B2]] : !s16i -> !s32i491// CIR: %[[SHL:.*]] = cir.shift(left, %[[A2]] : !s64i, %[[B2_EXT]] : !s32i) -> !s64i492// CIR: cir.store{{.*}} %[[SHL]], %[[X_PTR]] : !s64i, !cir.ptr<!s64i>493 494// CIR: cir.return495 496// LLVM-LABEL: define{{.*}} void @_Z18long_shift_examplexs497// LLVM-SAME: (i64 %[[A:.*]], i16 %[[B:.*]])498// LLVM: %[[A_ADDR:.*]] = alloca i64499// LLVM: %[[B_ADDR:.*]] = alloca i16500// LLVM: %[[X:.*]] = alloca i64501// LLVM: store i64 %[[A]], ptr %[[A_ADDR]]502// LLVM: store i16 %[[B]], ptr %[[B_ADDR]]503 504// LLVM: %[[A1:.*]] = load i64, ptr %[[A_ADDR]]505// LLVM: %[[B1:.*]] = load i16, ptr %[[B_ADDR]]506// LLVM: %[[B1_SEXT:.*]] = sext i16 %[[B1]] to i32507// LLVM: %[[B1_ZEXT:.*]] = zext i32 %[[B1_SEXT]] to i64508// LLVM: %[[ASHR:.*]] = ashr i64 %[[A1]], %[[B1_ZEXT]]509// LLVM: store i64 %[[ASHR]], ptr %[[X]]510 511// LLVM: %[[A2:.*]] = load i64, ptr %[[A_ADDR]]512// LLVM: %[[B2:.*]] = load i16, ptr %[[B_ADDR]]513// LLVM: %[[B2_SEXT:.*]] = sext i16 %[[B2]] to i32514// LLVM: %[[B2_ZEXT:.*]] = zext i32 %[[B2_SEXT]] to i64515// LLVM: %[[SHL:.*]] = shl i64 %[[A2]], %[[B2_ZEXT]]516// LLVM: store i64 %[[SHL]], ptr %[[X]]517 518// LLVM: ret void519 520// OGCG-LABEL: define{{.*}} void @_Z18long_shift_examplexs521// OGCG-SAME: (i64 {{.*}} %[[A:.*]], i16 {{.*}} %[[B:.*]])522// OGCG: %[[A_ADDR:.*]] = alloca i64523// OGCG: %[[B_ADDR:.*]] = alloca i16524// OGCG: %[[X:.*]] = alloca i64525// OGCG: store i64 %[[A]], ptr %[[A_ADDR]]526// OGCG: store i16 %[[B]], ptr %[[B_ADDR]]527 528// OGCG: %[[A1:.*]] = load i64, ptr %[[A_ADDR]]529// OGCG: %[[B1:.*]] = load i16, ptr %[[B_ADDR]]530// OGCG: %[[B1_SEXT:.*]] = sext i16 %[[B1]] to i32531// OGCG: %[[B1_ZEXT:.*]] = zext i32 %[[B1_SEXT]] to i64532// OGCG: %[[ASHR:.*]] = ashr i64 %[[A1]], %[[B1_ZEXT]]533// OGCG: store i64 %[[ASHR]], ptr %[[X]]534 535// OGCG: %[[A2:.*]] = load i64, ptr %[[A_ADDR]]536// OGCG: %[[B2:.*]] = load i16, ptr %[[B_ADDR]]537// OGCG: %[[B2_SEXT:.*]] = sext i16 %[[B2]] to i32538// OGCG: %[[B2_ZEXT:.*]] = zext i32 %[[B2_SEXT]] to i64539// OGCG: %[[SHL:.*]] = shl i64 %[[A2]], %[[B2_ZEXT]]540// OGCG: store i64 %[[SHL]], ptr %[[X]]541 542// OGCG: ret void543 544void b1(bool a, bool b) {545 bool x = a && b;546 x = x || b;547}548 549// CIR-LABEL: cir.func{{.*}} @_Z2b1bb(550// CIR-SAME: %[[ARG0:.*]]: !cir.bool {{.*}}, %[[ARG1:.*]]: !cir.bool {{.*}})551// CIR: [[A:%[0-9]+]] = cir.alloca !cir.bool, !cir.ptr<!cir.bool>, ["a", init]552// CIR: [[B:%[0-9]+]] = cir.alloca !cir.bool, !cir.ptr<!cir.bool>, ["b", init]553// CIR: [[X:%[0-9]+]] = cir.alloca !cir.bool, !cir.ptr<!cir.bool>, ["x", init]554// CIR: cir.store %[[ARG0]], [[A]] : !cir.bool, !cir.ptr<!cir.bool>555// CIR: cir.store %[[ARG1]], [[B]] : !cir.bool, !cir.ptr<!cir.bool>556// CIR: [[AVAL:%[0-9]+]] = cir.load align(1) [[A]] : !cir.ptr<!cir.bool>, !cir.bool557// CIR: [[RES1:%[0-9]+]] = cir.ternary([[AVAL]], true {558// CIR: [[BVAL:%[0-9]+]] = cir.load align(1) [[B]] : !cir.ptr<!cir.bool>, !cir.bool559// CIR: cir.yield [[BVAL]] : !cir.bool560// CIR: }, false {561// CIR: [[FALSE:%[0-9]+]] = cir.const #false562// CIR: cir.yield [[FALSE]] : !cir.bool563// CIR: }) : (!cir.bool) -> !cir.bool564// CIR: cir.store align(1) [[RES1]], [[X]] : !cir.bool, !cir.ptr<!cir.bool>565// CIR: [[XVAL:%[0-9]+]] = cir.load align(1) [[X]] : !cir.ptr<!cir.bool>, !cir.bool566// CIR: [[RES2:%[0-9]+]] = cir.ternary([[XVAL]], true {567// CIR: [[TRUE:%[0-9]+]] = cir.const #true568// CIR: cir.yield [[TRUE]] : !cir.bool569// CIR: }, false {570// CIR: [[BVAL2:%[0-9]+]] = cir.load align(1) [[B]] : !cir.ptr<!cir.bool>, !cir.bool571// CIR: cir.yield [[BVAL2]] : !cir.bool572// CIR: }) : (!cir.bool) -> !cir.bool573// CIR: cir.store align(1) [[RES2]], [[X]] : !cir.bool, !cir.ptr<!cir.bool>574// CIR: cir.return575 576 577// LLVM-LABEL: define{{.*}} void @_Z2b1bb(578// LLVM-SAME: i1 %[[ARG0:.+]], i1 %[[ARG1:.+]])579// LLVM: %[[A_ADDR:.*]] = alloca i8580// LLVM: %[[B_ADDR:.*]] = alloca i8581// LLVM: %[[X:.*]] = alloca i8582// LLVM: %[[ZEXT0:.*]] = zext i1 %[[ARG0]] to i8583// LLVM: store i8 %[[ZEXT0]], ptr %[[A_ADDR]]584// LLVM: %[[ZEXT1:.*]] = zext i1 %[[ARG1]] to i8585// LLVM: store i8 %[[ZEXT1]], ptr %[[B_ADDR]]586// LLVM: %[[A_VAL:.*]] = load i8, ptr %[[A_ADDR]]587// LLVM: %[[A_BOOL:.*]] = trunc i8 %[[A_VAL]] to i1588// LLVM: br i1 %[[A_BOOL]], label %[[AND_TRUE:.+]], label %[[AND_FALSE:.+]]589// LLVM: [[AND_TRUE]]:590// LLVM: %[[B_VAL:.*]] = load i8, ptr %[[B_ADDR]]591// LLVM: %[[B_BOOL:.*]] = trunc i8 %[[B_VAL]] to i1592// LLVM: br label %[[AND_MERGE:.+]]593// LLVM: [[AND_FALSE]]:594// LLVM: br label %[[AND_MERGE]]595// LLVM: [[AND_MERGE]]:596// LLVM: %[[AND_PHI:.*]] = phi i1 [ false, %[[AND_FALSE]] ], [ %[[B_BOOL]], %[[AND_TRUE]] ]597// LLVM: %[[ZEXT_AND:.*]] = zext i1 %[[AND_PHI]] to i8598// LLVM: store i8 %[[ZEXT_AND]], ptr %[[X]]599// LLVM: %[[X_VAL:.*]] = load i8, ptr %[[X]]600// LLVM: %[[X_BOOL:.*]] = trunc i8 %[[X_VAL]] to i1601// LLVM: br i1 %[[X_BOOL]], label %[[OR_TRUE:.+]], label %[[OR_FALSE:.+]]602// LLVM: [[OR_TRUE]]:603// LLVM: br label %[[OR_MERGE:.+]]604// LLVM: [[OR_FALSE]]:605// LLVM: %[[B_VAL2:.*]] = load i8, ptr %[[B_ADDR]]606// LLVM: %[[B_BOOL2:.*]] = trunc i8 %[[B_VAL2]] to i1607// LLVM: br label %[[OR_MERGE]]608// LLVM: [[OR_MERGE]]:609// LLVM: %[[OR_PHI:.*]] = phi i1 [ %[[B_BOOL2]], %[[OR_FALSE]] ], [ true, %[[OR_TRUE]] ]610// LLVM: %[[ZEXT_OR:.*]] = zext i1 %[[OR_PHI]] to i8611// LLVM: store i8 %[[ZEXT_OR]], ptr %[[X]]612// LLVM: ret void613 614// OGCG-LABEL: define{{.*}} void @_Z2b1bb615// OGCG-SAME: (i1 {{.*}} %[[ARG0:.+]], i1 {{.*}} %[[ARG1:.+]])616// OGCG: [[ENTRY:.*]]:617// OGCG: %[[A_ADDR:.*]] = alloca i8618// OGCG: %[[B_ADDR:.*]] = alloca i8619// OGCG: %[[X:.*]] = alloca i8620// OGCG: %[[ZEXT0:.*]] = zext i1 %[[ARG0]] to i8621// OGCG: store i8 %[[ZEXT0]], ptr %[[A_ADDR]]622// OGCG: %[[ZEXT1:.*]] = zext i1 %[[ARG1]] to i8623// OGCG: store i8 %[[ZEXT1]], ptr %[[B_ADDR]]624// OGCG: %[[A_VAL:.*]] = load i8, ptr %[[A_ADDR]]625// OGCG: %[[A_BOOL:.*]] = trunc i8 %[[A_VAL]] to i1626// OGCG: br i1 %[[A_BOOL]], label %[[AND_TRUE:.+]], label %[[AND_MERGE:.+]]627// OGCG: [[AND_TRUE]]:628// OGCG: %[[B_VAL:.*]] = load i8, ptr %[[B_ADDR]]629// OGCG: %[[B_BOOL:.*]] = trunc i8 %[[B_VAL]] to i1630// OGCG: br label %[[AND_MERGE:.+]]631// OGCG: [[AND_MERGE]]:632// OGCG: %[[AND_PHI:.*]] = phi i1 [ false, %[[ENTRY]] ], [ %[[B_BOOL]], %[[AND_TRUE]] ]633// OGCG: %[[ZEXT_AND:.*]] = zext i1 %[[AND_PHI]] to i8634// OGCG: store i8 %[[ZEXT_AND]], ptr %[[X]]635// OGCG: %[[X_VAL:.*]] = load i8, ptr %[[X]]636// OGCG: %[[X_BOOL:.*]] = trunc i8 %[[X_VAL]] to i1637// OGCG: br i1 %[[X_BOOL]], label %[[OR_MERGE:.+]], label %[[OR_FALSE:.+]]638// OGCG: [[OR_FALSE]]:639// OGCG: %[[B_VAL2:.*]] = load i8, ptr %[[B_ADDR]]640// OGCG: %[[B_BOOL2:.*]] = trunc i8 %[[B_VAL2]] to i1641// OGCG: br label %[[OR_MERGE]]642// OGCG: [[OR_MERGE]]:643// OGCG: %[[OR_PHI:.*]] = phi i1 [ true, %[[AND_MERGE]] ], [ %[[B_BOOL2]], %[[OR_FALSE]] ]644// OGCG: %[[ZEXT_OR:.*]] = zext i1 %[[OR_PHI]] to i8645// OGCG: store i8 %[[ZEXT_OR]], ptr %[[X]]646// OGCG: ret void647 648void b3(int a, int b, int c, int d) {649 bool x = (a == b) && (c == d);650 x = (a == b) || (c == d);651}652 653// CIR-LABEL: cir.func{{.*}} @_Z2b3iiii(654// CIR-SAME: %[[ARG0:.*]]: !s32i {{.*}}, %[[ARG1:.*]]: !s32i {{.*}}, %[[ARG2:.*]]: !s32i {{.*}}, %[[ARG3:.*]]: !s32i {{.*}})655// CIR: [[A:%[0-9]+]] = cir.alloca !s32i, !cir.ptr<!s32i>, ["a", init]656// CIR: [[B:%[0-9]+]] = cir.alloca !s32i, !cir.ptr<!s32i>, ["b", init]657// CIR: [[C:%[0-9]+]] = cir.alloca !s32i, !cir.ptr<!s32i>, ["c", init]658// CIR: [[D:%[0-9]+]] = cir.alloca !s32i, !cir.ptr<!s32i>, ["d", init]659// CIR: [[X:%[0-9]+]] = cir.alloca !cir.bool, !cir.ptr<!cir.bool>, ["x", init]660// CIR: cir.store %[[ARG0]], [[A]] : !s32i, !cir.ptr<!s32i>661// CIR: cir.store %[[ARG1]], [[B]] : !s32i, !cir.ptr<!s32i>662// CIR: cir.store %[[ARG2]], [[C]] : !s32i, !cir.ptr<!s32i>663// CIR: cir.store %[[ARG3]], [[D]] : !s32i, !cir.ptr<!s32i>664// CIR: [[AVAL1:%[0-9]+]] = cir.load align(4) [[A]] : !cir.ptr<!s32i>, !s32i665// CIR: [[BVAL1:%[0-9]+]] = cir.load align(4) [[B]] : !cir.ptr<!s32i>, !s32i666// CIR: [[CMP1:%[0-9]+]] = cir.cmp(eq, [[AVAL1]], [[BVAL1]]) : !s32i, !cir.bool667// CIR: [[AND_RESULT:%[0-9]+]] = cir.ternary([[CMP1]], true {668// CIR: [[CVAL1:%[0-9]+]] = cir.load align(4) [[C]] : !cir.ptr<!s32i>, !s32i669// CIR: [[DVAL1:%[0-9]+]] = cir.load align(4) [[D]] : !cir.ptr<!s32i>, !s32i670// CIR: [[CMP2:%[0-9]+]] = cir.cmp(eq, [[CVAL1]], [[DVAL1]]) : !s32i, !cir.bool671// CIR: cir.yield [[CMP2]] : !cir.bool672// CIR: }, false {673// CIR: [[FALSE:%[0-9]+]] = cir.const #false674// CIR: cir.yield [[FALSE]] : !cir.bool675// CIR: }) : (!cir.bool) -> !cir.bool676// CIR: cir.store align(1) [[AND_RESULT]], [[X]] : !cir.bool, !cir.ptr<!cir.bool>677// CIR: [[AVAL2:%[0-9]+]] = cir.load align(4) [[A]] : !cir.ptr<!s32i>, !s32i678// CIR: [[BVAL2:%[0-9]+]] = cir.load align(4) [[B]] : !cir.ptr<!s32i>, !s32i679// CIR: [[CMP3:%[0-9]+]] = cir.cmp(eq, [[AVAL2]], [[BVAL2]]) : !s32i, !cir.bool680// CIR: [[OR_RESULT:%[0-9]+]] = cir.ternary([[CMP3]], true {681// CIR: [[TRUE:%[0-9]+]] = cir.const #true682// CIR: cir.yield [[TRUE]] : !cir.bool683// CIR: }, false {684// CIR: [[CVAL2:%[0-9]+]] = cir.load align(4) [[C]] : !cir.ptr<!s32i>, !s32i685// CIR: [[DVAL2:%[0-9]+]] = cir.load align(4) [[D]] : !cir.ptr<!s32i>, !s32i686// CIR: [[CMP4:%[0-9]+]] = cir.cmp(eq, [[CVAL2]], [[DVAL2]]) : !s32i, !cir.bool687// CIR: cir.yield [[CMP4]] : !cir.bool688// CIR: }) : (!cir.bool) -> !cir.bool689// CIR: cir.store align(1) [[OR_RESULT]], [[X]] : !cir.bool, !cir.ptr<!cir.bool>690// CIR: cir.return691 692 693// LLVM-LABEL: define{{.*}} void @_Z2b3iiii(694// LLVM-SAME: i32 %[[ARG0:.+]], i32 %[[ARG1:.+]], i32 %[[ARG2:.+]], i32 %[[ARG3:.+]])695// LLVM: %[[A_ADDR:.*]] = alloca i32, i64 1696// LLVM: %[[B_ADDR:.*]] = alloca i32, i64 1697// LLVM: %[[C_ADDR:.*]] = alloca i32, i64 1698// LLVM: %[[D_ADDR:.*]] = alloca i32, i64 1699// LLVM: %[[X:.*]] = alloca i8, i64 1700// LLVM: store i32 %[[ARG0]], ptr %[[A_ADDR]]701// LLVM: store i32 %[[ARG1]], ptr %[[B_ADDR]]702// LLVM: store i32 %[[ARG2]], ptr %[[C_ADDR]]703// LLVM: store i32 %[[ARG3]], ptr %[[D_ADDR]]704// LLVM: %[[A_VAL:.*]] = load i32, ptr %[[A_ADDR]]705// LLVM: %[[B_VAL:.*]] = load i32, ptr %[[B_ADDR]]706// LLVM: %[[CMP1:.*]] = icmp eq i32 %[[A_VAL]], %[[B_VAL]]707// LLVM: br i1 %[[CMP1]], label %[[AND_TRUE:.+]], label %[[AND_FALSE:.+]]708// LLVM: [[AND_TRUE]]:709// LLVM: %[[C_VAL:.*]] = load i32, ptr %[[C_ADDR]]710// LLVM: %[[D_VAL:.*]] = load i32, ptr %[[D_ADDR]]711// LLVM: %[[CMP2:.*]] = icmp eq i32 %[[C_VAL]], %[[D_VAL]]712// LLVM: br label %[[AND_MERGE:.+]]713// LLVM: [[AND_FALSE]]:714// LLVM: br label %[[AND_MERGE]]715// LLVM: [[AND_MERGE]]:716// LLVM: %[[AND_PHI:.*]] = phi i1 [ false, %[[AND_FALSE]] ], [ %[[CMP2]], %[[AND_TRUE]] ]717// LLVM: %[[ZEXT_AND:.*]] = zext i1 %[[AND_PHI]] to i8718// LLVM: store i8 %[[ZEXT_AND]], ptr %[[X]]719// LLVM: %[[A_VAL2:.*]] = load i32, ptr %[[A_ADDR]]720// LLVM: %[[B_VAL2:.*]] = load i32, ptr %[[B_ADDR]]721// LLVM: %[[CMP3:.*]] = icmp eq i32 %[[A_VAL2]], %[[B_VAL2]]722// LLVM: br i1 %[[CMP3]], label %[[OR_TRUE:.+]], label %[[OR_FALSE:.+]]723// LLVM: [[OR_TRUE]]:724// LLVM: br label %[[OR_MERGE:.+]]725// LLVM: [[OR_FALSE]]:726// LLVM: %[[C_VAL2:.*]] = load i32, ptr %[[C_ADDR]]727// LLVM: %[[D_VAL2:.*]] = load i32, ptr %[[D_ADDR]]728// LLVM: %[[CMP4:.*]] = icmp eq i32 %[[C_VAL2]], %[[D_VAL2]]729// LLVM: br label %[[OR_MERGE]]730// LLVM: [[OR_MERGE]]:731// LLVM: %[[OR_PHI:.*]] = phi i1 [ %[[CMP4]], %[[OR_FALSE]] ], [ true, %[[OR_TRUE]] ]732// LLVM: %[[ZEXT_OR:.*]] = zext i1 %[[OR_PHI]] to i8733// LLVM: store i8 %[[ZEXT_OR]], ptr %[[X]]734// LLVM: ret void735 736// OGCG-LABEL: define{{.*}} void @_Z2b3iiii(737// OGCG-SAME: i32 {{.*}} %[[ARG0:.+]], i32 {{.*}} %[[ARG1:.+]], i32 {{.*}} %[[ARG2:.+]], i32 {{.*}} %[[ARG3:.+]])738// OGCG: [[ENTRY:.*]]:739// OGCG: %[[A_ADDR:.*]] = alloca i32740// OGCG: %[[B_ADDR:.*]] = alloca i32741// OGCG: %[[C_ADDR:.*]] = alloca i32742// OGCG: %[[D_ADDR:.*]] = alloca i32743// OGCG: %[[X:.*]] = alloca i8744// OGCG: store i32 %[[ARG0]], ptr %[[A_ADDR]]745// OGCG: store i32 %[[ARG1]], ptr %[[B_ADDR]]746// OGCG: store i32 %[[ARG2]], ptr %[[C_ADDR]]747// OGCG: store i32 %[[ARG3]], ptr %[[D_ADDR]]748// OGCG: %[[A_VAL:.*]] = load i32, ptr %[[A_ADDR]]749// OGCG: %[[B_VAL:.*]] = load i32, ptr %[[B_ADDR]]750// OGCG: %[[CMP1:.*]] = icmp eq i32 %[[A_VAL]], %[[B_VAL]]751// OGCG: br i1 %[[CMP1]], label %[[AND_TRUE:.+]], label %[[AND_MERGE:.+]]752// OGCG: [[AND_TRUE]]:753// OGCG: %[[C_VAL:.*]] = load i32, ptr %[[C_ADDR]]754// OGCG: %[[D_VAL:.*]] = load i32, ptr %[[D_ADDR]]755// OGCG: %[[CMP2:.*]] = icmp eq i32 %[[C_VAL]], %[[D_VAL]]756// OGCG: br label %[[AND_MERGE:.+]]757// OGCG: [[AND_MERGE]]:758// OGCG: %[[AND_PHI:.*]] = phi i1 [ false, %[[ENTRY]] ], [ %[[CMP2]], %[[AND_TRUE]] ]759// OGCG: %[[ZEXT_AND:.*]] = zext i1 %[[AND_PHI]] to i8760// OGCG: store i8 %[[ZEXT_AND]], ptr %[[X]]761// OGCG: %[[A_VAL2:.*]] = load i32, ptr %[[A_ADDR]]762// OGCG: %[[B_VAL2:.*]] = load i32, ptr %[[B_ADDR]]763// OGCG: %[[CMP3:.*]] = icmp eq i32 %[[A_VAL2]], %[[B_VAL2]]764// OGCG: br i1 %[[CMP3]], label %[[OR_MERGE:.+]], label %[[OR_FALSE:.+]]765// OGCG: [[OR_FALSE]]:766// OGCG: %[[C_VAL2:.*]] = load i32, ptr %[[C_ADDR]]767// OGCG: %[[D_VAL2:.*]] = load i32, ptr %[[D_ADDR]]768// OGCG: %[[CMP4:.*]] = icmp eq i32 %[[C_VAL2]], %[[D_VAL2]]769// OGCG: br label %[[OR_MERGE]]770// OGCG: [[OR_MERGE]]:771// OGCG: %[[OR_PHI:.*]] = phi i1 [ true, %[[AND_MERGE]] ], [ %[[CMP4]], %[[OR_FALSE]] ]772// OGCG: %[[ZEXT_OR:.*]] = zext i1 %[[OR_PHI]] to i8773// OGCG: store i8 %[[ZEXT_OR]], ptr %[[X]]774// OGCG: ret void775