377 lines · c
1// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -fclangir -emit-cir %s -o %t.cir2// RUN: FileCheck --input-file=%t.cir %s --check-prefix=CIR3// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -fclangir -emit-llvm %s -o %t-cir.ll4// RUN: FileCheck --input-file=%t-cir.ll %s --check-prefix=LLVM5// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -emit-llvm %s -o %t.ll6// RUN: FileCheck --input-file=%t.ll %s --check-prefix=OGCG7 8typedef struct {9 char a, b, c;10 unsigned bits : 3;11 unsigned more_bits : 4;12 unsigned still_more_bits : 7;13} A;14 15// CIR-DAG: !rec_A = !cir.record<struct "A" packed padded {!s8i, !s8i, !s8i, !u16i, !cir.array<!u8i x 3>}>16// CIR-DAG: #bfi_more_bits = #cir.bitfield_info<name = "more_bits", storage_type = !u16i, size = 4, offset = 3, is_signed = false>17// LLVM-DAG: %struct.A = type <{ i8, i8, i8, i16, [3 x i8] }>18// OGCG-DAG: %struct.A = type <{ i8, i8, i8, i16, [3 x i8] }>19 20typedef struct {21 int a : 4;22 int b : 5;23 int c;24} D;25 26// CIR-DAG: !rec_D = !cir.record<struct "D" {!u16i, !s32i}>27// LLVM-DAG: %struct.D = type { i16, i32 }28// OGCG-DAG: %struct.D = type { i16, i32 }29 30typedef struct {31 int a : 4;32 int b : 27;33 int c : 17;34 int d : 2;35 int e : 15;36 unsigned f; // type other than int above, not a bitfield37} S;38// CIR-DAG: #bfi_c = #cir.bitfield_info<name = "c", storage_type = !u64i, size = 17, offset = 32, is_signed = true>39// CIR-DAG: !rec_S = !cir.record<struct "S" {!u64i, !u16i, !u32i}>40// LLVM-DAG: %struct.S = type { i64, i16, i32 }41// OGCG-DAG: %struct.S = type { i64, i16, i32 }42 43typedef struct {44 int a : 3; // one bitfield with size < 845 unsigned b;46} T;47 48// CIR-DAG: !rec_T = !cir.record<struct "T" {!u8i, !u32i}>49// LLVM-DAG: %struct.T = type { i8, i32 }50// OGCG-DAG: %struct.T = type { i8, i32 }51 52typedef struct {53 char a;54 char b;55 char c;56 57 // startOffset 24 bits, new storage from here58 int d: 2;59 int e: 2;60 int f: 4;61 int g: 25;62 int h: 3;63 int i: 4;64 int j: 3;65 int k: 8;66 67 int l: 14;68} U;69 70// CIR-DAG: !rec_U = !cir.record<struct "U" packed {!s8i, !s8i, !s8i, !u8i, !u64i}>71// LLVM-DAG: %struct.U = type <{ i8, i8, i8, i8, i64 }>72// OGCG-DAG: %struct.U = type <{ i8, i8, i8, i8, i64 }>73 74typedef struct{75 int a : 24;76 char b;77 int c: 30;78} Clip;79 80// CIR-DAG: !rec_Clip = !cir.record<struct "Clip" {!cir.array<!u8i x 3>, !s8i, !u32i}>81// LLVM-DAG: %struct.Clip = type { [3 x i8], i8, i32 }82// OGCG-DAG: %struct.Clip = type { [3 x i8], i8, i32 }83 84void def() {85 A a;86 D d;87 S s;88 T t;89 U u;90 Clip c;91}92 93int load_field(S* s) {94 return s->c;95}96 97// CIR: cir.func {{.*@load_field}}98// CIR: [[TMP0:%.*]] = cir.alloca !cir.ptr<!rec_S>, !cir.ptr<!cir.ptr<!rec_S>>, ["s", init]99// CIR: [[TMP1:%.*]] = cir.load{{.*}} [[TMP0]] : !cir.ptr<!cir.ptr<!rec_S>>, !cir.ptr<!rec_S>100// CIR: [[TMP2:%.*]] = cir.get_member [[TMP1]][0] {name = "c"} : !cir.ptr<!rec_S> -> !cir.ptr<!u64i>101// CIR: [[TMP3:%.*]] = cir.get_bitfield align(4) (#bfi_c, [[TMP2]] : !cir.ptr<!u64i>) -> !s32i102 103// LLVM: define dso_local i32 @load_field104// LLVM: [[TMP0:%.*]] = alloca ptr, i64 1, align 8105// LLVM: [[TMP1:%.*]] = alloca i32, i64 1, align 4106// LLVM: [[TMP2:%.*]] = load ptr, ptr [[TMP0]], align 8107// LLVM: [[TMP3:%.*]] = getelementptr %struct.S, ptr [[TMP2]], i32 0, i32 0108// LLVM: [[TMP4:%.*]] = load i64, ptr [[TMP3]], align 4109// LLVM: [[TMP5:%.*]] = shl i64 [[TMP4]], 15110// LLVM: [[TMP6:%.*]] = ashr i64 [[TMP5]], 47111// LLVM: [[TMP7:%.*]] = trunc i64 [[TMP6]] to i32112 113// OGCG: define dso_local i32 @load_field114// OGCG: [[TMP0:%.*]] = alloca ptr, align 8115// OGCG: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8116// OGCG: [[TMP2:%.*]] = load i64, ptr [[TMP1]], align 4117// OGCG: [[TMP3:%.*]] = shl i64 [[TMP2]], 15118// OGCG: [[TMP4:%.*]] = ashr i64 [[TMP3]], 47119// OGCG: [[TMP5:%.*]] = trunc i64 [[TMP4]] to i32120 121unsigned int load_field_unsigned(A* s) {122 return s->more_bits;123}124 125//CIR: cir.func dso_local @load_field_unsigned126//CIR: [[TMP0:%.*]] = cir.alloca !cir.ptr<!rec_A>, !cir.ptr<!cir.ptr<!rec_A>>, ["s", init] {alignment = 8 : i64}127//CIR: [[TMP1:%.*]] = cir.load align(8) [[TMP0]] : !cir.ptr<!cir.ptr<!rec_A>>, !cir.ptr<!rec_A>128//CIR: [[TMP2:%.*]] = cir.get_member [[TMP1]][3] {name = "more_bits"} : !cir.ptr<!rec_A> -> !cir.ptr<!u16i>129//CIR: [[TMP3:%.*]] = cir.get_bitfield align(1) (#bfi_more_bits, [[TMP2]] : !cir.ptr<!u16i>) -> !u32i130 131//LLVM: define dso_local i32 @load_field_unsigned132//LLVM: [[TMP0:%.*]] = alloca ptr, i64 1, align 8133//LLVM: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8134//LLVM: [[TMP2:%.*]] = getelementptr %struct.A, ptr [[TMP1]], i32 0, i32 3135//LLVM: [[TMP3:%.*]] = load i16, ptr [[TMP2]], align 1136//LLVM: [[TMP4:%.*]] = lshr i16 [[TMP3]], 3137//LLVM: [[TMP5:%.*]] = and i16 [[TMP4]], 15138//LLVM: [[TMP6:%.*]] = zext i16 [[TMP5]] to i32139 140//OGCG: define dso_local i32 @load_field_unsigned141//OGCG: [[TMP0:%.*]] = alloca ptr, align 8142//OGCG: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8143//OGCG: [[TMP2:%.*]] = getelementptr inbounds nuw %struct.A, ptr [[TMP1]], i32 0, i32 3144//OGCG: [[TMP3:%.*]] = load i16, ptr [[TMP2]], align 1145//OGCG: [[TMP4:%.*]] = lshr i16 [[TMP3]], 3146//OGCG: [[TMP5:%.*]] = and i16 [[TMP4]], 15147//OGCG: [[TMP6:%.*]] = zext i16 [[TMP5]] to i32148 149void store_field() {150 S s;151 s.e = 3;152}153// CIR: cir.func {{.*@store_field}}154// CIR: [[TMP0:%.*]] = cir.alloca !rec_S, !cir.ptr<!rec_S>155// CIR: [[TMP1:%.*]] = cir.const #cir.int<3> : !s32i156// CIR: [[TMP2:%.*]] = cir.get_member [[TMP0]][1] {name = "e"} : !cir.ptr<!rec_S> -> !cir.ptr<!u16i>157// CIR: cir.set_bitfield align(4) (#bfi_e, [[TMP2]] : !cir.ptr<!u16i>, [[TMP1]] : !s32i)158 159// LLVM: define dso_local void @store_field()160// LLVM: [[TMP0:%.*]] = alloca %struct.S, i64 1, align 4161// LLVM: [[TMP1:%.*]] = getelementptr %struct.S, ptr [[TMP0]], i32 0, i32 1162// LLVM: [[TMP2:%.*]] = load i16, ptr [[TMP1]], align 4163// LLVM: [[TMP3:%.*]] = and i16 [[TMP2]], -32768164// LLVM: [[TMP4:%.*]] = or i16 [[TMP3]], 3165// LLVM: store i16 [[TMP4]], ptr [[TMP1]], align 4166 167// OGCG: define dso_local void @store_field()168// OGCG: [[TMP0:%.*]] = alloca %struct.S, align 4169// OGCG: [[TMP1:%.*]] = getelementptr inbounds nuw %struct.S, ptr [[TMP0]], i32 0, i32 1170// OGCG: [[TMP2:%.*]] = load i16, ptr [[TMP1]], align 4171// OGCG: [[TMP3:%.*]] = and i16 [[TMP2]], -32768172// OGCG: [[TMP4:%.*]] = or i16 [[TMP3]], 3173// OGCG: store i16 [[TMP4]], ptr [[TMP1]], align 4174 175void store_bitfield_to_bitfield() {176 S s;177 s.a = s.c;178}179 180// CIR: cir.func {{.*@store_bitfield_to_bitfield}}181// CIR: [[TMP0:%.*]] = cir.alloca !rec_S, !cir.ptr<!rec_S>, ["s"] {alignment = 4 : i64}182// CIR: [[TMP1:%.*]] = cir.get_member [[TMP0]][0] {name = "c"} : !cir.ptr<!rec_S> -> !cir.ptr<!u64i>183// CIR: [[TMP2:%.*]] = cir.get_bitfield align(4) (#bfi_c, [[TMP1]] : !cir.ptr<!u64i>) -> !s32i184// CIR: [[TMP3:%.*]] = cir.get_member [[TMP0]][0] {name = "a"} : !cir.ptr<!rec_S> -> !cir.ptr<!u64i>185// CIR: [[TMP4:%.*]] = cir.set_bitfield align(4) (#bfi_a, [[TMP3]] : !cir.ptr<!u64i>, [[TMP2]] : !s32i) -> !s32i186 187// LLVM: define dso_local void @store_bitfield_to_bitfield()188// LLVM: [[TMP0:%.*]] = alloca %struct.S, i64 1, align 4189// LLVM: [[TMP1:%.*]] = getelementptr %struct.S, ptr [[TMP0]], i32 0, i32 0190// LLVM: [[TMP2:%.*]] = load i64, ptr [[TMP1]], align 4191// LLVM: [[TMP3:%.*]] = shl i64 [[TMP2]], 15192// LLVM: [[TMP4:%.*]] = ashr i64 [[TMP3]], 47193// LLVM: [[TMP5:%.*]] = trunc i64 [[TMP4]] to i32194// LLVM: [[TMP6:%.*]] = getelementptr %struct.S, ptr [[TMP0]], i32 0, i32 0195// LLVM: [[TMP7:%.*]] = zext i32 [[TMP5]] to i64196// LLVM: [[TMP8:%.*]] = load i64, ptr [[TMP6]], align 4197// LLVM: [[TMP9:%.*]] = and i64 [[TMP7]], 15198// LLVM: [[TMP10:%.*]] = and i64 [[TMP8]], -16199// LLVM: [[TMP11:%.*]] = or i64 [[TMP10]], [[TMP9]]200// LLVM: store i64 [[TMP11]], ptr [[TMP6]], align 4201// LLVM: [[TMP12:%.*]] = shl i64 [[TMP9]], 60202// LLVM: [[TMP13:%.*]] = ashr i64 [[TMP12]], 60203// LLVM: [[TMP15:%.*]] = trunc i64 [[TMP13]] to i32204 205// OGCG: define dso_local void @store_bitfield_to_bitfield()206// OGCG: [[TMP0:%.*]] = alloca %struct.S, align 4207// OGCG: [[TMP1:%.*]] = load i64, ptr [[TMP0]], align 4208// OGCG: [[TMP2:%.*]] = shl i64 [[TMP1]], 15209// OGCG: [[TMP3:%.*]] = ashr i64 [[TMP2]], 47210// OGCG: [[TMP4:%.*]] = trunc i64 [[TMP3]] to i32211// OGCG: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64212// OGCG: [[TMP6:%.*]] = load i64, ptr [[TMP0]], align 4213// OGCG: [[TMP7:%.*]] = and i64 [[TMP5]], 15214// OGCG: [[TMP8:%.*]] = and i64 [[TMP6]], -16215// OGCG: [[TMP9:%.*]] = or i64 [[TMP8]], [[TMP7]]216// OGCG: store i64 [[TMP9]], ptr [[TMP0]], align 4217// OGCG: [[TMP10:%.*]] = shl i64 %bf.value, 60218// OGCG: [[TMP11:%.*]] = ashr i64 [[TMP10]], 60219// OGCG: [[TMP12:%.*]] = trunc i64 [[TMP11]] to i32220 221typedef struct {222 int a : 30;223 int volatile b : 8;224 int c;225} V;226 227void get_volatile(V* v) {228 v->b = 3;229}230 231// CIR: cir.func dso_local @get_volatile232// CIR: [[TMP0:%.*]] = cir.alloca !cir.ptr<!rec_V>, !cir.ptr<!cir.ptr<!rec_V>>, ["v", init] {alignment = 8 : i64}233// CIR: [[TMP1:%.*]] = cir.const #cir.int<3> : !s32i234// CIR: [[TMP2:%.*]] = cir.load align(8) [[TMP0]] : !cir.ptr<!cir.ptr<!rec_V>>, !cir.ptr<!rec_V>235// CIR: [[TMP3:%.*]] = cir.get_member [[TMP2]][0] {name = "b"} : !cir.ptr<!rec_V> -> !cir.ptr<!u64i>236// CIR: [[TMP4:%.*]] = cir.set_bitfield align(4) (#bfi_b, [[TMP3]] : !cir.ptr<!u64i>, [[TMP1]] : !s32i) {is_volatile} -> !s32i237 238// LLVM: define dso_local void @get_volatile239// LLVM: [[TMP0:%.*]] = alloca ptr, i64 1, align 8240// LLVM: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8241// LLVM: [[TMP2:%.*]] = getelementptr %struct.V, ptr [[TMP1]], i32 0, i32 0242// LLVM: [[TMP3:%.*]] = load volatile i64, ptr [[TMP2]], align 4243// LLVM: [[TMP4:%.*]] = and i64 [[TMP3]], -1095216660481244// LLVM: [[TMP5:%.*]] = or i64 [[TMP4]], 12884901888245// LLVM: store volatile i64 [[TMP5]], ptr [[TMP2]], align 4246 247// OCGC: define dso_local void @get_volatile248// OCGC: [[TMP0:%.*]] = alloca ptr, align 8249// OCGC: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8250// OCGC: [[TMP2:%.*]] = load volatile i64, ptr [[TMP1]], align 4251// OCGC: [[TMP3:%.*]] = and i64 [[TMP2]], -1095216660481252// OCGC: [[TMP4:%.*]] = or i64 [[TMP3]], 12884901888253// OCGC: store volatile i64 [[TMP4]], ptr [[TMP1]], align 4254 255void set_volatile(V* v) {256 v->b = 3;257}258//CIR: cir.func dso_local @set_volatile259//CIR: [[TMP0:%.*]] = cir.alloca !cir.ptr<!rec_V>, !cir.ptr<!cir.ptr<!rec_V>>, ["v", init] {alignment = 8 : i64}260//CIR: [[TMP1:%.*]] = cir.const #cir.int<3> : !s32i261//CIR: [[TMP2:%.*]] = cir.load align(8) [[TMP0]] : !cir.ptr<!cir.ptr<!rec_V>>, !cir.ptr<!rec_V>262//CIR: [[TMP3:%.*]] = cir.get_member [[TMP2]][0] {name = "b"} : !cir.ptr<!rec_V> -> !cir.ptr<!u64i>263//CIR: [[TMP4:%.*]] = cir.set_bitfield align(4) (#bfi_b, [[TMP3]] : !cir.ptr<!u64i>, [[TMP1]] : !s32i) {is_volatile} -> !s32i264 265// LLVM: define dso_local void @set_volatile266// LLVM: [[TMP0:%.*]] = alloca ptr, i64 1, align 8267// LLVM: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8268// LLVM: [[TMP2:%.*]] = getelementptr %struct.V, ptr [[TMP1]], i32 0, i32 0269// LLVM: [[TMP3:%.*]] = load volatile i64, ptr [[TMP2]], align 4270// LLVM: [[TMP4:%.*]] = and i64 [[TMP3]], -1095216660481271// LLVM: [[TMP5:%.*]] = or i64 [[TMP4]], 12884901888272// LLVM: store volatile i64 [[TMP5]], ptr [[TMP2]], align 4273 274// OGCG: define dso_local void @set_volatile275// OGCG: [[TMP0:%.*]] = alloca ptr, align 8276// OGCG: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8277// OGCG: [[TMP2:%.*]] = load volatile i64, ptr [[TMP1]], align 4278// OGCG: [[TMP3:%.*]] = and i64 [[TMP2]], -1095216660481279// OGCG: [[TMP4:%.*]] = or i64 [[TMP3]], 12884901888280// OGCG: store volatile i64 [[TMP4]], ptr [[TMP1]], align 4281 282void unOp(S* s) {283 s->d++;284}285 286// CIR: cir.func {{.*@unOp}}287// CIR: [[TMP0:%.*]] = cir.alloca !cir.ptr<!rec_S>, !cir.ptr<!cir.ptr<!rec_S>>, ["s", init] {alignment = 8 : i64}288// CIR: [[TMP1:%.*]] = cir.load align(8) [[TMP0]] : !cir.ptr<!cir.ptr<!rec_S>>, !cir.ptr<!rec_S>289// CIR: [[TMP2:%.*]] = cir.get_member [[TMP1]][0] {name = "d"} : !cir.ptr<!rec_S> -> !cir.ptr<!u64i>290// CIR: [[TMP3:%.*]] = cir.get_bitfield align(4) (#bfi_d, [[TMP2]] : !cir.ptr<!u64i>) -> !s32i291// CIR: [[TMP4:%.*]] = cir.unary(inc, [[TMP3]]) nsw : !s32i, !s32i292// CIR: cir.set_bitfield align(4) (#bfi_d, [[TMP2]] : !cir.ptr<!u64i>, [[TMP4]] : !s32i)293 294// LLVM: define {{.*@unOp}}295// LLVM: [[TMP0:%.*]] = getelementptr %struct.S, ptr [[LOAD0:%.*]], i32 0, i32 0296// LLVM: [[TMP1:%.*]] = load i64, ptr [[TMP0]], align 4297// LLVM: [[TMP2:%.*]] = shl i64 [[TMP1]], 13298// LLVM: [[TMP3:%.*]] = ashr i64 [[TMP2]], 62299// LLVM: [[TMP4:%.*]] = trunc i64 [[TMP3]] to i32300// LLVM: [[TMP5:%.*]] = add nsw i32 [[TMP4]], 1301// LLVM: [[TMP6:%.*]] = zext i32 [[TMP5]] to i64302// LLVM: [[TMP7:%.*]] = load i64, ptr [[TMP0]], align 4303// LLVM: [[TMP8:%.*]] = and i64 [[TMP6]], 3304// LLVM: [[TMP9:%.*]] = shl i64 [[TMP8]], 49305// LLVM: [[TMP10:%.*]] = and i64 [[TMP7]], -1688849860263937306// LLVM: [[TMP11:%.*]] = or i64 [[TMP10]], [[TMP9]]307// LLVM: store i64 [[TMP11]], ptr [[TMP0]], align 4308// LLVM: [[TMP12:%.*]] = shl i64 [[TMP8]], 62309// LLVM: [[TMP13:%.*]] = ashr i64 [[TMP12]], 62310// LLVM: [[TMP14:%.*]] = trunc i64 [[TMP13]] to i32311 312// OGCG: define {{.*@unOp}}313// OGCG: [[TMP0:%.*]] = load ptr, ptr %s.addr, align 8314// OGCG: [[TMP1:%.*]] = load i64, ptr [[TMP0]], align 4315// OGCG: [[TMP2:%.*]] = shl i64 [[TMP1]], 13316// OGCG: [[TMP3:%.*]] = ashr i64 [[TMP2]], 62317// OGCG: [[TMP4:%.*]] = trunc i64 [[TMP3]] to i32318// OGCG: [[TMP5:%.*]] = add nsw i32 [[TMP4]], 1319// OGCG: [[TMP6:%.*]] = zext i32 [[TMP5]] to i64320// OGCG: [[TMP7:%.*]] = load i64, ptr [[TMP0]], align 4321// OGCG: [[TMP8:%.*]] = and i64 [[TMP6]], 3322// OGCG: [[TMP9:%.*]] = shl i64 [[TMP8]], 49323// OGCG: [[TMP10:%.*]] = and i64 [[TMP7]], -1688849860263937324// OGCG: [[TMP11:%.*]] = or i64 [[TMP10]], [[TMP9]]325// OGCG: store i64 [[TMP11]], ptr [[TMP0]], align 4326// OGCG: [[TMP12:%.*]] = shl i64 [[TMP8]], 62327// OGCG: [[TMP13:%.*]] = ashr i64 [[TMP12]], 62328// OGCG: [[TMP14:%.*]] = trunc i64 [[TMP13]] to i32329 330void binOp(S* s) {331 s->d |= 42;332}333 334// CIR: cir.func {{.*@binOp}}335// CIR: [[TMP0:%.*]] = cir.const #cir.int<42> : !s32i336// CIR: [[TMP1:%.*]] = cir.get_member {{.*}}[0] {name = "d"} : !cir.ptr<!rec_S> -> !cir.ptr<!u64i>337// CIR: [[TMP2:%.*]] = cir.get_bitfield align(4) (#bfi_d, [[TMP1]] : !cir.ptr<!u64i>) -> !s32i338// CIR: [[TMP3:%.*]] = cir.binop(or, [[TMP2]], [[TMP0]]) : !s32i339// CIR: cir.set_bitfield align(4) (#bfi_d, [[TMP1]] : !cir.ptr<!u64i>, [[TMP3]] : !s32i)340 341// LLVM: define {{.*@binOp}}342// LLVM: [[TMP0:%.*]] = load ptr, ptr {{.*}}, align 8343// LLVM: [[TMP1:%.*]] = getelementptr %struct.S, ptr [[TMP0]], i32 0, i32 0344// LLVM: [[TMP2:%.*]] = load i64, ptr [[TMP1]], align 4345// LLVM: [[TMP3:%.*]] = shl i64 [[TMP2]], 13346// LLVM: [[TMP4:%.*]] = ashr i64 [[TMP3]], 62347// LLVM: [[TMP5:%.*]] = trunc i64 [[TMP4]] to i32348// LLVM: [[TMP6:%.*]] = or i32 [[TMP5]], 42349// LLVM: [[TMP7:%.*]] = zext i32 [[TMP6]] to i64350// LLVM: [[TMP8:%.*]] = load i64, ptr [[TMP1]], align 4351// LLVM: [[TMP9:%.*]] = and i64 [[TMP7]], 3352// LLVM: [[TMP10:%.*]] = shl i64 [[TMP9]], 49353// LLVM: [[TMP11:%.*]] = and i64 [[TMP8]], -1688849860263937354// LLVM: [[TMP12:%.*]] = or i64 [[TMP11]], [[TMP10]]355// LLVM: store i64 [[TMP12]], ptr [[TMP1]], align 4356// LLVM: [[TMP13:%.*]] = shl i64 [[TMP9]], 62357// LLVM: [[TMP14:%.*]] = ashr i64 [[TMP13]], 62358// LLVM: [[TMP15:%.*]] = trunc i64 [[TMP14]] to i32359 360// OGCG: define {{.*@binOp}}361// OGCG: [[TMP0:%.*]] = load ptr, ptr %s.addr, align 8362// OGCG: [[TMP1:%.*]] = load i64, ptr [[TMP0]], align 4363// OGCG: [[TMP2:%.*]] = shl i64 [[TMP1]], 13364// OGCG: [[TMP3:%.*]] = ashr i64 [[TMP2]], 62365// OGCG: [[TMP4:%.*]] = trunc i64 [[TMP3]] to i32366// OGCG: [[TMP5:%.*]] = or i32 [[TMP4]], 42367// OGCG: [[TMP6:%.*]] = zext i32 [[TMP5]] to i64368// OGCG: [[TMP7:%.*]] = load i64, ptr [[TMP0]], align 4369// OGCG: [[TMP8:%.*]] = and i64 [[TMP6]], 3370// OGCG: [[TMP9:%.*]] = shl i64 [[TMP8]], 49371// OGCG: [[TMP10:%.*]] = and i64 [[TMP7]], -1688849860263937372// OGCG: [[TMP11:%.*]] = or i64 [[TMP10]], [[TMP9]]373// OGCG: store i64 [[TMP11]], ptr [[TMP0]], align 4374// OGCG: [[TMP12:%.*]] = shl i64 [[TMP8]], 62375// OGCG: [[TMP13:%.*]] = ashr i64 [[TMP12]], 62376// OGCG: [[TMP14:%.*]] = trunc i64 [[TMP13]] to i32377