272 lines · cpp
1// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -fclangir -emit-cir -ffine-grained-bitfield-accesses %s -o %t.cir2// RUN: FileCheck --input-file=%t.cir %s --check-prefix=CIR3// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -fclangir -emit-llvm -ffine-grained-bitfield-accesses %s -o %t-cir.ll4// RUN: FileCheck --input-file=%t-cir.ll %s --check-prefix=LLVM5// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -emit-llvm -ffine-grained-bitfield-accesses %s -o %t.ll6// RUN: FileCheck --input-file=%t.ll %s --check-prefix=OGCG7 8struct S1 {9 unsigned f1:2;10 unsigned f2:6;11 unsigned f3:8;12 unsigned f4:4;13 unsigned f5:8;14};15 16// CIR-DAG: !rec_S1 = !cir.record<struct "S1" {!u8i, !u8i, !u16i}>17// LLVM-DAG: %struct.S1 = type { i8, i8, i16 }18// OGCG-DAG: %struct.S1 = type { i8, i8, i16 }19 20struct S2 {21 unsigned long f1:16;22 unsigned long f2:16;23 unsigned long f3:6;24};25 26// CIR-DAG: !rec_S2 = !cir.record<struct "S2" padded {!u16i, !u16i, !u8i, !cir.array<!u8i x 3>}>27// LLVM-DAG: %struct.S2 = type { i16, i16, i8, [3 x i8] }28// OGCG-DAG: %struct.S2 = type { i16, i16, i8, [3 x i8] }29 30struct S3 {31 unsigned long f1:14;32 unsigned long f2:18;33 unsigned long f3:32;34};35 36// CIR-DAG: !rec_S3 = !cir.record<struct "S3" {!u32i, !u32i}>37// LLVM-DAG: %struct.S3 = type { i32, i32 }38// OGCG-DAG: %struct.S3 = type { i32, i32 }39 40S1 a1;41S2 a2;42S3 a3;43 44unsigned read8_1() {45 return a1.f3;46}47 48// CIR-LABEL: @_Z7read8_1v49// CIR: [[MEMBER:%.*]] = cir.get_member %1[1] {name = "f3"} : !cir.ptr<!rec_S1> -> !cir.ptr<!u8i>50// CIR: [[BITFI:%.*]] = cir.get_bitfield align(1) (#bfi_f3, [[MEMBER]] : !cir.ptr<!u8i>) -> !u32i51// CIR: cir.store [[BITFI]], {{.*}} : !u32i, !cir.ptr<!u32i>52// CIR: [[RET:%.*]] = cir.load {{.*}} : !cir.ptr<!u32i>, !u32i53// CIR: cir.return [[RET]] : !u32i54 55// LLVM-LABEL: @_Z7read8_1v56// LLVM: [[MEMBER:%.*]] = load i8, ptr getelementptr inbounds nuw (i8, ptr {{.*}}, i64 1), align 157// LLVM: [[BFCAST:%.*]] = zext i8 [[MEMBER]] to i3258// LLVM: store i32 [[BFCAST]], ptr {{.*}}, align 459// LLVM: [[RET:%.*]] = load i32, ptr {{.*}}, align 460// LLVM: ret i32 [[RET]]61 62// OGCG-LABEL: @_Z7read8_1v63// OGCG: [[BFLOAD:%.*]] = load i8, ptr getelementptr inbounds nuw (%struct.S1, ptr {{.*}}, i32 0, i32 1), align 164// OGCG-NEXT: [[BFCAST:%.*]] = zext i8 [[BFLOAD]] to i3265// OGCG-NEXT: ret i32 [[BFCAST]]66 67void write8_1() {68 a1.f3 = 3;69}70 71// CIR-LABEL: @_Z8write8_1v72// CIR: [[CONST3:%.*]] = cir.const #cir.int<3> : !s32i73// CIR: [[INT3:%.*]] = cir.cast integral [[CONST3]] : !s32i -> !u32i74// CIR: [[MEMBER:%.*]] = cir.get_member {{.*}}[1] {name = "f3"} : !cir.ptr<!rec_S1> -> !cir.ptr<!u8i>75// CIR: cir.set_bitfield align(1) (#bfi_f3, [[MEMBER]] : !cir.ptr<!u8i>, [[INT3]] : !u32i) -> !u32i76 77// LLVM-LABEL: @_Z8write8_1v78// LLVM: store i8 3, ptr getelementptr inbounds nuw (i8, ptr {{.*}}, i64 1), align 179// LLVM: ret void80 81// OGCG-LABEL: @_Z8write8_1v82// OGCG: store i8 3, ptr getelementptr inbounds nuw (%struct.S1, ptr {{.*}}, i32 0, i32 1), align 183// OGCG-NEXT: ret void84 85unsigned read8_2() {86 87 return a1.f5;88}89 90// CIR-LABEL: @_Z7read8_2v91// CIR: [[MEMBER:%.*]] = cir.get_member {{.*}}[2] {name = "f5"} : !cir.ptr<!rec_S1> -> !cir.ptr<!u16i>92// CIR: [[BITFI:%.*]] = cir.get_bitfield align(2) (#bfi_f5, [[MEMBER]] : !cir.ptr<!u16i>) -> !u32i93// CIR: cir.store [[BITFI]], {{.*}} : !u32i, !cir.ptr<!u32i>94// CIR: [[RET:%.*]] = cir.load {{.*}} : !cir.ptr<!u32i>, !u32i95// CIR: cir.return [[RET]] : !u32i96 97// LLVM-LABEL: @_Z7read8_2v98// LLVM: [[BFLOAD:%.*]] = load i16, ptr getelementptr inbounds nuw (i8, ptr {{.*}}, i64 2), align 299// LLVM: [[BFLSHR:%.*]] = lshr i16 [[BFLOAD]], 4100// LLVM: [[BFCLEAR:%.*]] = and i16 [[BFLSHR]], 255101// LLVM: [[BFCAST:%.*]] = zext i16 [[BFCLEAR]] to i32102// LLVM: store i32 [[BFCAST]], ptr {{.*}}, align 4103// LLVM: [[RET:%.*]] = load i32, ptr {{.*}}, align 4104// LLVM: ret i32 [[RET]]105 106// OGCG-LABEL: @_Z7read8_2v107// OGCG: [[BFLOAD:%.*]] = load i16, ptr getelementptr inbounds nuw (%struct.S1, ptr {{.*}}, i32 0, i32 2), align 2108// OGCG-NEXT: [[BFLSHR:%.*]] = lshr i16 [[BFLOAD]], 4109// OGCG-NEXT: [[BFCLEAR:%.*]] = and i16 [[BFLSHR]], 255110// OGCG-NEXT: [[BFCAST:%.*]] = zext i16 [[BFCLEAR]] to i32111// OGCG-NEXT: ret i32 [[BFCAST]]112 113void write8_2() {114 a1.f5 = 3;115}116 117// CIR-LABEL: @_Z8write8_2v118// CIR: [[CONST3:%.*]] = cir.const #cir.int<3> : !s32i119// CIR: [[INT3:%.*]] = cir.cast integral [[CONST3]] : !s32i -> !u32i120// CIR: [[MEMBER:%.*]] = cir.get_member {{.*}}[2] {name = "f5"} : !cir.ptr<!rec_S1> -> !cir.ptr<!u16i>121// CIR: cir.set_bitfield align(2) (#bfi_f5, %3 : !cir.ptr<!u16i>, {{.*}} : !u32i) -> !u32i122 123// LLVM-LABEL: @_Z8write8_2v124// LLVM: [[BFLOAD:%.*]] = load i16, ptr getelementptr inbounds nuw (i8, ptr {{.*}}, i64 2), align 2125// LLVM: [[BFCLEAR:%.*]] = and i16 [[BFLOAD]], -4081126// LLVM: [[BFSET:%.*]] = or i16 [[BFCLEAR]], 48127// LLVM: store i16 [[BFSET]], ptr getelementptr inbounds nuw (i8, ptr {{.*}}, i64 2), align 2128// LLVM: ret void129 130// OGCG-LABEL: @_Z8write8_2v131// OGCG: [[BFLOAD:%.*]] = load i16, ptr getelementptr inbounds nuw (%struct.S1, ptr {{.*}}, i32 0, i32 2), align 2132// OGCG-NEXT: [[BFCLEAR:%.*]] = and i16 [[BFLOAD]], -4081133// OGCG-NEXT: [[BFSET:%.*]] = or i16 [[BFCLEAR]], 48134// OGCG-NEXT: store i16 [[BFSET]], ptr getelementptr inbounds nuw (%struct.S1, ptr {{.*}}, i32 0, i32 2), align 2135// OGCG-NEXT: ret void136 137unsigned read16_1() {138 return a2.f1;139}140 141// CIR-LABEL: @_Z8read16_1v142// CIR: [[MEMBER:%.*]] = cir.get_member {{.*}}[0] {name = "f1"} : !cir.ptr<!rec_S2> -> !cir.ptr<!u16i>143// CIR: [[BITFI:%.*]] = cir.get_bitfield align(8) (#bfi_f1, [[MEMBER]] : !cir.ptr<!u16i>) -> !u64i144// CIR: [[BFCAST:%.*]] = cir.cast integral [[BITFI]] : !u64i -> !u32i145// CIR: cir.store [[BFCAST]], {{.*}} : !u32i, !cir.ptr<!u32i>146// CIR: [[RET:%.*]] = cir.load {{.*}} : !cir.ptr<!u32i>, !u32i147// CIR: cir.return [[RET]] : !u32i148 149// LLVM-LABEL: @_Z8read16_1v150// LLVM: [[BFLOAD:%.*]] = load i16, ptr {{.*}}, align 8151// LLVM: [[BFCAST:%.*]] = zext i16 [[BFLOAD]] to i64152// LLVM: [[BF:%.*]] = trunc i64 [[BFCAST]] to i32153// LLVM: store i32 [[BF]], ptr {{.*}}, align 4154// LLVM: [[RET:%.*]] = load i32, ptr {{.*}}, align 4155// LLVM: ret i32 [[RET]]156 157// OGCG-LABEL: @_Z8read16_1v158// OGCG: [[BFLOAD:%.*]] = load i16, ptr {{.*}}, align 8159// OGCG-NEXT: [[BFCAST:%.*]] = zext i16 [[BFLOAD]] to i64160// OGCG-NEXT: [[RET:%.*]] = trunc i64 [[BFCAST]] to i32161// OGCG-NEXT: ret i32 [[RET]]162 163unsigned read16_2() {164 return a2.f2;165}166 167// CIR-LABEL: @_Z8read16_2v168// CIR: [[MEMBER:%.*]] = cir.get_member {{.*}}[1] {name = "f2"} : !cir.ptr<!rec_S2> -> !cir.ptr<!u16i>169// CIR: [[BITFI:%.*]] = cir.get_bitfield align(2) (#bfi_f2, [[MEMBER]] : !cir.ptr<!u16i>) -> !u64i170// CIR: [[BFCAST:%.*]] = cir.cast integral [[BITFI]] : !u64i -> !u32i171// CIR: cir.store [[BFCAST]], {{.*}} : !u32i, !cir.ptr<!u32i>172// CIR: [[RET:%.*]] = cir.load {{.*}} : !cir.ptr<!u32i>, !u32i173// CIR: cir.return [[RET]] : !u32i174 175// LLVM-LABEL: @_Z8read16_2v176// LLVM: [[BFLOAD:%.*]] = load i16, ptr getelementptr inbounds nuw (i8, ptr {{.*}}, i64 2), align 2177// LLVM: [[BFCAST:%.*]] = zext i16 [[BFLOAD]] to i64178// LLVM: [[BF:%.*]] = trunc i64 [[BFCAST]] to i32179// LLVM: store i32 [[BF]], ptr {{.*}}, align 4180// LLVM: [[RET:%.*]] = load i32, ptr {{.*}}, align 4181// LLVM: ret i32 [[RET]]182 183// OGCG-LABEL: @_Z8read16_2v184// OGCG: [[BFLOAD:%.*]] = load i16, ptr getelementptr inbounds nuw (%struct.S2, ptr {{.*}}, i32 0, i32 1), align 2185// OGCG-NEXT: [[BFCAST:%.*]] = zext i16 [[BFLOAD]] to i64186// OGCG-NEXT: [[RET:%.*]] = trunc i64 [[BFCAST]] to i32187// OGCG-NEXT: ret i32 [[RET]]188 189void write16_1() {190 a2.f1 = 5;191}192 193// CIR-LABEL: @_Z9write16_1v194// CIR: [[CONST5:%.*]] = cir.const #cir.int<5> : !s32i195// CIR: [[INT5:%.*]] = cir.cast integral [[CONST5]] : !s32i -> !u64i196// CIR: [[MEMBER:%.*]] = cir.get_member {{.*}}[0] {name = "f1"} : !cir.ptr<!rec_S2> -> !cir.ptr<!u16i>197// CIR: cir.set_bitfield align(8) (#bfi_f1, [[MEMBER]] : !cir.ptr<!u16i>, [[INT5]] : !u64i) -> !u64i198// CIR: cir.return199 200// LLVM-LABEL: @_Z9write16_1v201// LLVM: store i16 5, ptr {{.*}}, align 8202// LLVM: ret void203 204// OGCG-LABEL: @_Z9write16_1v205// OGCG: store i16 5, ptr {{.*}}, align 8206// OGCG-NEXT: ret void207 208void write16_2() {209 210 a2.f2 = 5;211}212 213// CIR-LABEL: @_Z9write16_2v214// CIR: [[CONST5:%.*]] = cir.const #cir.int<5> : !s32i215// CIR: [[INT5:%.*]] = cir.cast integral [[CONST5]] : !s32i -> !u64i216// CIR: [[MEMBER:%.*]] = cir.get_member {{.*}}[1] {name = "f2"} : !cir.ptr<!rec_S2> -> !cir.ptr<!u16i>217// CIR: cir.set_bitfield align(2) (#bfi_f2, [[MEMBER]] : !cir.ptr<!u16i>, {{.*}} : !u64i) -> !u64i218// CIR: cir.return219 220// LLVM-LABEL: @_Z9write16_2v221// LLVM: store i16 5, ptr getelementptr inbounds nuw (i8, ptr {{.*}}, i64 2), align 2222// LLVM: ret void223 224// OGCG-LABEL: @_Z9write16_2v225// OGCG: store i16 5, ptr getelementptr inbounds nuw (%struct.S2, ptr {{.*}}, i32 0, i32 1), align 2226// OGCG-NEXT: ret void227 228unsigned read32_1() {229 230 return a3.f3;231}232// CIR-LABEL: @_Z8read32_1v233// CIR: [[MEMBER:%.*]] = cir.get_member {{.*}}[1] {name = "f3"} : !cir.ptr<!rec_S3> -> !cir.ptr<!u32i>234// CIR: [[BITFI:%.*]] = cir.get_bitfield align(4) (#bfi_f3_1, [[MEMBER]] : !cir.ptr<!u32i>) -> !u64i235// CIR: [[BFCAST:%.*]] = cir.cast integral [[BITFI]] : !u64i -> !u32i236// CIR: cir.store [[BFCAST]], {{.*}} : !u32i, !cir.ptr<!u32i>237// CIR: [[RET:%.*]] = cir.load {{.*}} : !cir.ptr<!u32i>, !u32i238// CIR: cir.return [[RET]] : !u32i239 240// LLVM-LABEL: @_Z8read32_1v241// LLVM: [[BFLOAD:%.*]] = load i32, ptr getelementptr inbounds nuw (i8, ptr {{.*}}, i64 4), align 4242// LLVM: [[BFCAST:%.*]] = zext i32 [[BFLOAD]] to i64243// LLVM: [[BF:%.*]] = trunc i64 [[BFCAST]] to i32244// LLVM: store i32 [[BF]], ptr {{.*}}, align 4245// LLVM: [[RET:%.*]] = load i32, ptr {{.*}}, align 4246// LLVM: ret i32 [[RET]]247 248// OGCG-LABEL: @_Z8read32_1v249// OGCG: [[BFLOAD:%.*]] = load i32, ptr getelementptr inbounds nuw (%struct.S3, ptr {{.*}}, i32 0, i32 1), align 4250// OGCG-NEXT: [[BFCAST:%.*]] = zext i32 %bf.load to i64251// OGCG-NEXT: [[RET:%.*]] = trunc i64 %bf.cast to i32252// OGCG-NEXT: ret i32 [[RET]]253 254void write32_1() {255 a3.f3 = 5;256}257 258// CIR-LABEL: @_Z9write32_1v259// CIR: [[CONST5:%.*]] = cir.const #cir.int<5> : !s32i260// CIR: [[INT5:%.*]] = cir.cast integral [[CONST5]] : !s32i -> !u64i261// CIR: [[MEMBER:%.*]] = cir.get_member {{.*}}[1] {name = "f3"} : !cir.ptr<!rec_S3> -> !cir.ptr<!u32i>262// CIR: cir.set_bitfield align(4) (#bfi_f3_1, [[MEMBER]] : !cir.ptr<!u32i>, [[INT5]] : !u64i) -> !u64i263// CIR: cir.return264 265// LLVM-LABEL: @_Z9write32_1v266// LLVM: store i32 5, ptr getelementptr inbounds nuw (i8, ptr {{.*}}, i64 4), align 4267// LLVM: ret void268 269// OGCG-LABEL: @_Z9write32_1v270// OGCG: store i32 5, ptr getelementptr inbounds nuw (%struct.S3, ptr {{.*}}, i32 0, i32 1), align 4271// OGCG-NEXT: ret void272