1273 lines · cpp
1// RUN: %clang_cc1 -std=c++17 -triple x86_64-unknown-linux-gnu -fclangir -emit-cir %s -o %t.cir2/// RUN: FileCheck --input-file=%t.cir %s --check-prefix=CIR3// RUN: %clang_cc1 -std=c++17 -triple x86_64-unknown-linux-gnu -fclangir -emit-llvm %s -o %t-cir.ll4// RUN: FileCheck --input-file=%t-cir.ll %s --check-prefix=LLVM5// RUN: %clang_cc1 -std=c++17 -triple x86_64-unknown-linux-gnu -emit-llvm %s -o %t.ll6// RUN: FileCheck --input-file=%t.ll %s --check-prefix=OGCG7void sw1(int a) {8 switch (int b = 1; a) {9 case 0:10 b = b + 1;11 break;12 case 1:13 break;14 case 2: {15 b = b + 1;16 int yolo = 100;17 break;18 }19 }20}21 22// CIR: cir.func{{.*}} @_Z3sw1i23// CIR: cir.switch (%[[COND:.*]] : !s32i) {24// CIR-NEXT: cir.case(equal, [#cir.int<0> : !s32i]) {25// CIR: cir.break26// CIR: cir.case(equal, [#cir.int<1> : !s32i]) {27// CIR-NEXT: cir.break28// CIR: cir.case(equal, [#cir.int<2> : !s32i]) {29// CIR: cir.scope {30// CIR: cir.alloca !s32i, !cir.ptr<!s32i>, ["yolo", init]31// CIR: cir.break32 33// LLVM: define{{.*}} void @_Z3sw1i34// LLVM: store i32 1, ptr %[[B_ADDR:.*]], align 435// LLVM: %[[A_VAL:.*]] = load i32, ptr %[[A_ADDR:.*]], align 436// LLVM: br label %[[BB7:.*]]37// LLVM: [[BB7]]:38// LLVM: switch i32 %[[A_VAL]], label %[[EXIT:.*]] [39// LLVM-DAG: i32 0, label %[[CASE0:.*]]40// LLVM-DAG: i32 1, label %[[CASE1:.*]]41// LLVM-DAG: i32 2, label %[[CASE2:.*]]42// LLVM: ]43// LLVM: [[CASE0]]:44// LLVM: %[[B:.*]] = load i32, ptr %[[B_ADDR]], align 445// LLVM: %[[INC0:.*]] = add nsw i32 %[[B]], 146// LLVM: store i32 %[[INC0]], ptr %[[B_ADDR]], align 447// LLVM: br label %[[EXIT]]48// LLVM: [[CASE1]]:49// LLVM: br label %[[EXIT]]50// LLVM: [[CASE2]]:51// LLVM: br label %[[BB14:.*]]52// LLVM: [[BB14]]:53// LLVM: %[[B2:.*]] = load i32, ptr %[[B_ADDR]], align 454// LLVM: %[[INC2:.*]] = add nsw i32 %[[B2]], 155// LLVM: store i32 %[[INC2]], ptr %[[B_ADDR]], align 456// LLVM: store i32 100, ptr %[[YOLO:.*]], align 457// LLVM: br label %[[EXIT]]58// LLVM: [[EXIT]]:59// LLVM: br label %[[DEFAULT:.*]]60// LLVM: [[DEFAULT]]:61// LLVM: ret void62 63// OGCG: define{{.*}} void @_Z3sw1i64// OGCG: entry:65// OGCG: %[[A_ADDR:.*]] = alloca i32, align 466// OGCG: %[[B:.*]] = alloca i32, align 467// OGCG: %[[YOLO:.*]] = alloca i32, align 468// OGCG: %[[A_VAL:.*]] = load i32, ptr %[[A_ADDR]], align 469// OGCG: switch i32 %[[A_VAL]], label %[[SW_EPILOG:.*]] [70// OGCG: i32 0, label %[[SW0:.*]]71// OGCG: i32 1, label %[[SW1:.*]]72// OGCG: i32 2, label %[[SW2:.*]]73// OGCG: ]74// OGCG: [[SW0]]:75// OGCG: %[[B_LOAD0:.*]] = load i32, ptr %[[B]], align 476// OGCG: %[[B_INC0:.*]] = add nsw i32 %[[B_LOAD0]], 177// OGCG: store i32 %[[B_INC0]], ptr %[[B]], align 478// OGCG: br label %[[SW_EPILOG]]79// OGCG: [[SW1]]:80// OGCG: br label %[[SW_EPILOG]]81// OGCG: [[SW2]]:82// OGCG: %[[B_LOAD2:.*]] = load i32, ptr %[[B]], align 483// OGCG: %[[B_INC2:.*]] = add nsw i32 %[[B_LOAD2]], 184// OGCG: store i32 %[[B_INC2]], ptr %[[B]], align 485// OGCG: store i32 100, ptr %[[YOLO]], align 486// OGCG: br label %[[SW_EPILOG]]87// OGCG: [[SW_EPILOG]]:88// OGCG: ret void89 90void sw2(int a) {91 switch (int yolo = 2; a) {92 case 3:93 // "fomo" has the same lifetime as "yolo"94 int fomo = 0;95 yolo = yolo + fomo;96 break;97 }98}99 100// CIR: cir.func{{.*}} @_Z3sw2i101// CIR: cir.scope {102// CIR-NEXT: %[[YOLO:.*]] = cir.alloca !s32i, !cir.ptr<!s32i>, ["yolo", init]103// CIR-NEXT: %[[FOMO:.*]] = cir.alloca !s32i, !cir.ptr<!s32i>, ["fomo", init]104// CIR: cir.switch (%[[COND:.*]] : !s32i) {105// CIR-NEXT: cir.case(equal, [#cir.int<3> : !s32i]) {106// CIR-NEXT: %[[ZERO:.*]] = cir.const #cir.int<0> : !s32i107// CIR-NEXT: cir.store{{.*}} %[[ZERO]], %[[FOMO]] : !s32i, !cir.ptr<!s32i>108 109// LLVM: define{{.*}} void @_Z3sw2i110// LLVM: store i32 2, ptr %[[YOLO_ADDR:.*]], align 4111// LLVM: %[[A_VAL:.*]] = load i32, ptr %[[A_ADDR:.*]], align 4112// LLVM: br label %[[SWITCH:.*]]113// LLVM: [[SWITCH]]:114// LLVM: switch i32 %[[A_VAL]], label %[[EXIT:.*]] [115// LLVM: i32 3, label %[[CASE3:.*]]116// LLVM: ]117// LLVM: [[CASE3]]:118// LLVM: store i32 0, ptr %[[FOMO_ADDR:.*]], align 4119// LLVM: %[[YOLO_VAL:.*]] = load i32, ptr %[[YOLO_ADDR]], align 4120// LLVM: %[[FOMO_VAL:.*]] = load i32, ptr %[[FOMO_ADDR]], align 4121// LLVM: %[[YOLO_PLUS_FOMO:.*]] = add nsw i32 %[[YOLO_VAL]], %[[FOMO_VAL]]122// LLVM: store i32 %[[YOLO_PLUS_FOMO]], ptr %[[YOLO_ADDR]], align 4123// LLVM: br label %[[EXIT]]124// LLVM: [[EXIT]]:125// LLVM: br label %[[RET:.*]]126// LLVM: [[RET]]:127// LLVM: ret void128 129// OGCG: define{{.*}} void @_Z3sw2i130// OGCG: entry:131// OGCG: %[[A_ADDR:.*]] = alloca i32, align 4132// OGCG: %[[YOLO:.*]] = alloca i32, align 4133// OGCG: %[[FOMO:.*]] = alloca i32, align 4134// OGCG: %[[A_VAL:.*]] = load i32, ptr %[[A_ADDR]], align 4135// OGCG: switch i32 %[[A_VAL]], label %[[SW_EPILOG:.*]] [136// OGCG: i32 3, label %[[SW3:.*]]137// OGCG: ]138// OGCG: [[SW3]]:139// OGCG: %[[Y:.*]] = load i32, ptr %[[YOLO]], align 4140// OGCG: %[[F:.*]] = load i32, ptr %[[FOMO]], align 4141// OGCG: %[[SUM:.*]] = add nsw i32 %[[Y]], %[[F]]142// OGCG: store i32 %[[SUM]], ptr %[[YOLO]], align 4143// OGCG: br label %[[SW_EPILOG]]144// OGCG: [[SW_EPILOG]]:145// OGCG: ret void146 147void sw3(int a) {148 switch (a) {149 default:150 break;151 }152}153 154// CIR: cir.func{{.*}} @_Z3sw3i155// CIR: cir.scope {156// CIR-NEXT: %[[COND:.*]] = cir.load{{.*}} %[[A:.*]] : !cir.ptr<!s32i>, !s32i157// CIR-NEXT: cir.switch (%[[COND]] : !s32i) {158// CIR-NEXT: cir.case(default, []) {159// CIR-NEXT: cir.break160// CIR-NEXT: }161// CIR-NEXT: cir.yield162// CIR-NEXT: }163 164// LLVM-LABEL: define{{.*}} void @_Z3sw3i165// LLVM: %[[A_VAL:.*]] = load i32, ptr %[[A_ADDR:.*]], align 4166// LLVM: br label %[[SWITCH:.*]]167// LLVM: [[SWITCH]]:168// LLVM: switch i32 %[[A_VAL]], label %[[DEFAULT:.*]] [169// LLVM: ]170// LLVM: [[DEFAULT]]:171// LLVM: br label %[[EXIT:.*]]172// LLVM: [[EXIT:.*]]:173// LLVM: br label %[[RET:.*]]174// LLVM: [[RET]]:175// LLVM: ret void176 177// OGCG: define{{.*}} void @_Z3sw3i178// OGCG: entry:179// OGCG: %[[A_ADDR:.*]] = alloca i32, align 4180// OGCG: %[[A_VAL:.*]] = load i32, ptr %[[A_ADDR]], align 4181// OGCG: switch i32 %[[A_VAL]], label %[[DEFAULT:.*]] [182// OGCG: [[DEFAULT]]:183// OGCG: br label %[[EPILOG:.*]]184// OGCG: [[EPILOG]]:185// OGCG: ret void186 187int sw4(int a) {188 switch (a) {189 case 42: {190 return 3;191 }192 default:193 return 2;194 }195 return 0;196}197 198// CIR: cir.func{{.*}} @_Z3sw4i199// CIR: cir.switch (%[[COND:.*]] : !s32i) {200// CIR-NEXT: cir.case(equal, [#cir.int<42> : !s32i]) {201// CIR-NEXT: cir.scope {202// CIR-NEXT: %[[THREE:.*]] = cir.const #cir.int<3> : !s32i203// CIR-NEXT: cir.store{{.*}} %[[THREE]], %[[RETVAL:.*]] : !s32i, !cir.ptr<!s32i>204// CIR-NEXT: %[[RET3:.*]] = cir.load{{.*}} %[[RETVAL]] : !cir.ptr<!s32i>, !s32i205// CIR-NEXT: cir.return %[[RET3]] : !s32i206// CIR-NEXT: }207// CIR-NEXT: cir.yield208// CIR-NEXT: }209// CIR-NEXT: cir.case(default, []) {210// CIR-NEXT: %[[TWO:.*]] = cir.const #cir.int<2> : !s32i211// CIR-NEXT: cir.store{{.*}} %[[TWO]], %[[RETVAL]] : !s32i, !cir.ptr<!s32i>212// CIR-NEXT: %[[RET2:.*]] = cir.load{{.*}} %[[RETVAL]] : !cir.ptr<!s32i>, !s32i213// CIR-NEXT: cir.return %[[RET2]] : !s32i214// CIR-NEXT: }215// CIR-NEXT: cir.yield216// CIR-NEXT: }217 218// LLVM: define{{.*}} i32 @_Z3sw4i219// LLVM: %[[A_ADDR:.*]] = alloca i32, i64 1, align 4220// LLVM: %[[RET_ADDR:.*]] = alloca i32, i64 1, align 4221// LLVM: br label %[[ENTRY:.*]]222// LLVM: [[ENTRY]]:223// LLVM: %[[A_VAL:.*]] = load i32, ptr %[[A_ADDR]], align 4224// LLVM: br label %[[SWITCH:.*]]225// LLVM: [[SWITCH]]:226// LLVM: switch i32 %[[A_VAL]], label %[[DEFAULT:.*]] [227// LLVM-DAG: i32 42, label %[[CASE42:.*]]228// LLVM: ]229// LLVM: [[CASE42]]:230// LLVM: br label %[[CASE42_BODY:.*]]231// LLVM: [[CASE42_BODY]]:232// LLVM: store i32 3, ptr %[[RET_ADDR]], align 4233// LLVM: %[[RET3:.*]] = load i32, ptr %[[RET_ADDR]], align 4234// LLVM: ret i32 %[[RET3]]235// LLVM: [[DEFAULT]]:236// LLVM: store i32 2, ptr %[[RET_ADDR]], align 4237// LLVM: %[[RET2:.*]] = load i32, ptr %[[RET_ADDR]], align 4238// LLVM: ret i32 %[[RET2]]239// LLVM: [[EXIT_UNRE:.*]]:240// LLVM: store i32 0, ptr %[[RET_ADDR]], align 4241// LLVM: %[[RET0:.*]] = load i32, ptr %[[RET_ADDR]], align 4242// LLVM: ret i32 %[[RET0]]243 244// OGCG: define{{.*}} i32 @_Z3sw4i245// OGCG: entry:246// OGCG: %[[RETVAL:.*]] = alloca i32, align 4247// OGCG: %[[A_ADDR:.*]] = alloca i32, align 4248// OGCG: %[[A_VAL:.*]] = load i32, ptr %[[A_ADDR]], align 4249// OGCG: switch i32 %[[A_VAL]], label %[[DEFAULT:.*]] [250// OGCG: i32 42, label %[[SW42:.*]]251// OGCG: ]252// OGCG: [[SW42]]:253// OGCG: br label %[[RETURN:.*]]254// OGCG: [[DEFAULT]]:255// OGCG: br label %[[RETURN]]256// OGCG: [[RETURN]]:257// OGCG: %[[RETVAL_LOAD:.*]] = load i32, ptr %[[RETVAL]], align 4258// OGCG: ret i32 %[[RETVAL_LOAD]]259 260void sw5(int a) {261 switch (a) {262 case 1:;263 }264}265 266// CIR: cir.func{{.*}} @_Z3sw5i267// CIR: cir.switch (%[[A:.*]] : !s32i) {268// CIR-NEXT: cir.case(equal, [#cir.int<1> : !s32i]) {269// CIR-NEXT: cir.yield270// CIR-NEXT: }271// CIR-NEXT: cir.yield272// CIR-NEXT: }273 274// LLVM-LABEL: define{{.*}} void @_Z3sw5i275// LLVM: %[[A_ADDR:.*]] = alloca i32, i64 1, align 4276// LLVM: br label %[[ENTRY:.*]]277// LLVM: [[ENTRY]]:278// LLVM: %[[A_VAL:.*]] = load i32, ptr %[[A_ADDR]], align 4279// LLVM: br label %[[SWITCH:.*]]280// LLVM: [[SWITCH]]:281// LLVM: switch i32 %[[A_VAL]], label %[[EXIT:.*]] [282// LLVM-DAG: i32 1, label %[[CASE1:.*]]283// LLVM: ]284// LLVM: [[CASE1]]:285// LLVM: br label %[[EXIT:.*]]286// LLVM: [[EXIT]]:287// LLVM: br label %[[RET:.*]]288// LLVM: [[RET]]:289// LLVM: ret void290 291// OGCG: define{{.*}} void @_Z3sw5i292// OGCG: entry:293// OGCG: %[[A_ADDR:.*]] = alloca i32, align 4294// OGCG: %[[A_VAL:.*]] = load i32, ptr %[[A_ADDR]], align 4295// OGCG: switch i32 %[[A_VAL]], label %[[SW_EPILOG:.*]] [296// OGCG: i32 1, label %[[SW1:.*]]297// OGCG: ]298// OGCG: [[SW1]]:299// OGCG: br label %[[SW_EPILOG]]300// OGCG: [[SW_EPILOG]]:301// OGCG: ret void302 303void sw6(int a) {304 switch (a) {305 case 0:306 case 1:307 case 2:308 break;309 case 3:310 case 4:311 case 5:312 break;313 }314}315 316// CIR: cir.func{{.*}} @_Z3sw6i317// CIR: cir.switch (%[[A:.*]] : !s32i) {318// CIR-NEXT: cir.case(equal, [#cir.int<0> : !s32i]) {319// CIR-NEXT: cir.yield320// CIR-NEXT: }321// CIR-NEXT: cir.case(equal, [#cir.int<1> : !s32i]) {322// CIR-NEXT: cir.yield323// CIR-NEXT: }324// CIR-NEXT: cir.case(equal, [#cir.int<2> : !s32i]) {325// CIR-NEXT: cir.break326// CIR-NEXT: }327// CIR-NEXT: cir.case(equal, [#cir.int<3> : !s32i]) {328// CIR-NEXT: cir.yield329// CIR-NEXT: }330// CIR-NEXT: cir.case(equal, [#cir.int<4> : !s32i]) {331// CIR-NEXT: cir.yield332// CIR-NEXT: }333// CIR-NEXT: cir.case(equal, [#cir.int<5> : !s32i]) {334// CIR-NEXT: cir.break335// CIR-NEXT: }336 337// LLVM: define{{.*}} void @_Z3sw6i338// LLVM: %[[A_VAL:.*]] = load i32, ptr %[[A_ADDR:.*]], align 4339// LLVM: br label %[[SWITCH:.*]]340// LLVM: [[SWITCH]]:341// LLVM: switch i32 %[[A_VAL]], label %[[EXIT:.*]] [342// LLVM-DAG: i32 0, label %[[CASE0:.*]]343// LLVM-DAG: i32 1, label %[[CASE1:.*]]344// LLVM-DAG: i32 2, label %[[CASE2:.*]]345// LLVM-DAG: i32 3, label %[[CASE3:.*]]346// LLVM-DAG: i32 4, label %[[CASE4:.*]]347// LLVM-DAG: i32 5, label %[[CASE5:.*]]348// LLVM: ]349// LLVM: [[CASE0]]:350// LLVM: br label %[[CASE0_CONT:.*]]351// LLVM: [[CASE0_CONT]]:352// LLVM: br label %[[CASE1]]353// LLVM: [[CASE1]]:354// LLVM: br label %[[CASE1_CONT:.*]]355// LLVM: [[CASE1_CONT]]:356// LLVM: br label %[[CASE2]]357// LLVM: [[CASE2]]:358// LLVM: br label %[[EXIT:.*]]359// LLVM: [[CASE3]]:360// LLVM: br label %[[CASE3_CONT:.*]]361// LLVM: [[CASE3_CONT]]:362// LLVM: br label %[[CASE4]]363// LLVM: [[CASE4]]:364// LLVM: br label %[[CASE4_CONT:.*]]365// LLVM: [[CASE4_CONT]]:366// LLVM: br label %[[CASE5]]367// LLVM: [[CASE5]]:368// LLVM: br label %[[EXIT]]369// LLVM: [[EXIT]]:370// LLVM: br label %[[RET:.*]]371// LLVM: [[RET]]:372// LLVM: ret void373 374// OGCG: define{{.*}} void @_Z3sw6i375// OGCG: entry:376// OGCG: %[[A_ADDR:.*]] = alloca i32, align 4377// OGCG: store i32 %a, ptr %[[A_ADDR]], align 4378// OGCG: %[[A_VAL:.*]] = load i32, ptr %[[A_ADDR]], align 4379// OGCG: switch i32 %[[A_VAL]], label %[[EPILOG:.*]] [380// OGCG: i32 0, label %[[BB0:.*]]381// OGCG: i32 1, label %[[BB0]]382// OGCG: i32 2, label %[[BB0]]383// OGCG: i32 3, label %[[BB1:.*]]384// OGCG: i32 4, label %[[BB1]]385// OGCG: i32 5, label %[[BB1]]386// OGCG: ]387// OGCG: [[BB0]]:388// OGCG: br label %[[EPILOG]]389// OGCG: [[BB1]]:390// OGCG: br label %[[EPILOG]]391// OGCG: [[EPILOG]]:392// OGCG: ret void393 394void sw7(int a) {395 switch (a) {396 case 0:397 case 1:398 case 2:399 int x;400 case 3:401 case 4:402 case 5:403 break;404 }405}406 407// CIR: cir.func{{.*}} @_Z3sw7i408// CIR: %[[X:.*]] = cir.alloca !s32i, !cir.ptr<!s32i>, ["x"]409// CIR: cir.switch (%[[A:.*]] : !s32i)410// CIR-NEXT: cir.case(equal, [#cir.int<0> : !s32i]) {411// CIR-NEXT: cir.yield412// CIR-NEXT: }413// CIR-NEXT: cir.case(equal, [#cir.int<1> : !s32i]) {414// CIR-NEXT: cir.yield415// CIR-NEXT: }416// CIR-NEXT: cir.case(equal, [#cir.int<2> : !s32i]) {417// CIR-NEXT: cir.yield418// CIR-NEXT: }419// CIR-NEXT: cir.case(equal, [#cir.int<3> : !s32i]) {420// CIR-NEXT: cir.yield421// CIR-NEXT: }422// CIR-NEXT: cir.case(equal, [#cir.int<4> : !s32i]) {423// CIR-NEXT: cir.yield424// CIR-NEXT: }425// CIR-NEXT: cir.case(equal, [#cir.int<5> : !s32i]) {426// CIR-NEXT: cir.break427// CIR-NEXT: }428// CIR-NEXT: cir.yield429// CIR: }430 431// LLVM: define{{.*}} void @_Z3sw7i432// LLVM: %[[A_VAL:.*]] = load i32, ptr %[[A_ADDR:.*]], align 4433// LLVM: br label %[[SWITCH:.*]]434// LLVM: [[SWITCH]]:435// LLVM: switch i32 %[[A_VAL]], label %[[EXIT:.*]] [436// LLVM-DAG: i32 0, label %[[CASE0:.*]]437// LLVM-DAG: i32 1, label %[[CASE1:.*]]438// LLVM-DAG: i32 2, label %[[CASE2:.*]]439// LLVM-DAG: i32 3, label %[[CASE3:.*]]440// LLVM-DAG: i32 4, label %[[CASE4:.*]]441// LLVM-DAG: i32 5, label %[[CASE5:.*]]442// LLVM: ]443// LLVM: [[CASE0]]:444// LLVM: br label %[[CASE0_CONT:.*]]445// LLVM: [[CASE0_CONT]]:446// LLVM: br label %[[CASE1]]447// LLVM: [[CASE1]]:448// LLVM: br label %[[CASE1_CONT:.*]]449// LLVM: [[CASE1_CONT]]:450// LLVM: br label %[[CASE2]]451// LLVM: [[CASE2]]:452// LLVM: br label %[[CASE2_CONT:.*]]453// LLVM: [[CASE2_CONT]]:454// LLVM: br label %[[CASE3]]455// LLVM: [[CASE3]]:456// LLVM: br label %[[CASE3_CONT:.*]]457// LLVM: [[CASE3_CONT]]:458// LLVM: br label %[[CASE4]]459// LLVM: [[CASE4]]:460// LLVM: br label %[[CASE4_CONT:.*]]461// LLVM: [[CASE4_CONT]]:462// LLVM: br label %[[CASE5]]463// LLVM: [[CASE5]]:464// LLVM: br label %[[EXIT]]465// LLVM: [[EXIT]]:466// LLVM: br label %[[RET:.*]]467// LLVM: [[RET]]:468// LLVM: ret void469 470// OGCG: define{{.*}} void @_Z3sw7i471// OGCG: entry:472// OGCG: %[[A_ADDR:.*]] = alloca i32, align 4473// OGCG: %[[A_VAL:.*]] = load i32, ptr %[[A_ADDR]], align 4474// OGCG: switch i32 %[[A_VAL]], label %[[EPILOG:.*]] [475// OGCG: i32 0, label %[[BB0:.*]]476// OGCG: i32 1, label %[[BB0]]477// OGCG: i32 2, label %[[BB0]]478// OGCG: i32 3, label %[[BB1:.*]]479// OGCG: i32 4, label %[[BB1]]480// OGCG: i32 5, label %[[BB1]]481// OGCG: ]482// OGCG: [[BB0]]:483// OGCG: br label %[[BB1]]484// OGCG: [[BB1]]:485// OGCG: br label %[[EPILOG]]486// OGCG: [[EPILOG]]:487// OGCG: ret void488 489 490void sw8(int a) {491 switch (a)492 {493 case 3:494 break;495 case 4:496 default:497 break;498 }499}500 501// CIR: cir.func{{.*}} @_Z3sw8i502// CIR: cir.switch (%[[A:.*]] : !s32i)503// CIR-NEXT: cir.case(equal, [#cir.int<3> : !s32i]) {504// CIR-NEXT: cir.break505// CIR-NEXT: }506// CIR-NEXT: cir.case(equal, [#cir.int<4> : !s32i]) {507// CIR-NEXT: cir.yield508// CIR-NEXT: }509// CIR-NEXT: cir.case(default, []) {510// CIR-NEXT: cir.break511// CIR-NEXT: }512 513// LLVM: define{{.*}} void @_Z3sw8i514// LLVM: switch i32 %[[COND:.*]], label %[[DEFAULT:.*]] [515// LLVM-DAG: i32 3, label %[[CASE3:.*]]516// LLVM-DAG: i32 4, label %[[CASE4:.*]]517// LLVM: ]518// LLVM: [[CASE3]]:519// LLVM: br label %[[EXIT:.*]]520// LLVM: [[CASE4]]:521// LLVM: br label %[[CASE4_CONT:.*]]522// LLVM: [[CASE4_CONT]]:523// LLVM: br label %[[DEFAULT]]524// LLVM: [[DEFAULT]]:525// LLVM: br label %[[EXIT:.*]]526// LLVM: [[EXIT]]:527// LLVM: br label %[[RET:.*]]528// LLVM: [[RET]]:529// LLVM: ret void530 531// OGCG: define{{.*}} void @_Z3sw8i532// OGCG: entry:533// OGCG: %[[A_ADDR:.*]] = alloca i32, align 4534// OGCG: %[[A_VAL:.*]] = load i32, ptr %[[A_ADDR]], align 4535// OGCG: switch i32 %[[A_VAL]], label %[[DEFAULT:.*]] [536// OGCG: i32 3, label %[[SW3:.*]]537// OGCG: i32 4, label %[[SW4:.*]]538// OGCG: ]539// OGCG: [[SW3]]:540// OGCG: br label %[[EPILOG:.*]]541// OGCG: [[SW4]]:542// OGCG: br label %[[DEFAULT]]543// OGCG: [[DEFAULT]]:544// OGCG: br label %[[EPILOG]]545// OGCG: [[EPILOG]]:546// OGCG: ret void547 548void sw9(int a) {549 switch (a)550 {551 case 3:552 break;553 default:554 case 4:555 break;556 }557}558 559// CIR: cir.func{{.*}} @_Z3sw9i560// CIR: cir.switch (%[[A:.*]] : !s32i)561// CIR-NEXT: cir.case(equal, [#cir.int<3> : !s32i]) {562// CIR-NEXT: cir.break563// CIR-NEXT: }564// CIR-NEXT: cir.case(default, []) {565// CIR-NEXT: cir.yield566// CIR-NEXT: }567// CIR-NEXT: cir.case(equal, [#cir.int<4> : !s32i]) {568// CIR-NEXT: cir.break569// CIR-NEXT: }570 571// LLVM: define{{.*}} void @_Z3sw9i572// LLVM: switch i32 %[[COND:.*]], label %[[DEFAULT:.*]] [573// LLVM-DAG: i32 3, label %[[CASE3:.*]]574// LLVM-DAG: i32 4, label %[[CASE4:.*]]575// LLVM: ]576// LLVM: [[CASE3]]:577// LLVM: br label %[[EXIT:.*]]578// LLVM: [[DEFAULT]]:579// LLVM: br label %[[DEFAULT_CONT:.*]]580// LLVM: [[DEFAULT_CONT]]:581// LLVM: br label %[[CASE4]]582// LLVM: [[CASE4]]:583// LLVM: br label %[[EXIT:.*]]584// LLVM: [[EXIT]]:585// LLVM: br label %[[RET:.*]]586// LLVM: [[RET]]:587// LLVM: ret void588 589// OGCG: define{{.*}} void @_Z3sw9i590// OGCG: entry:591// OGCG: %[[A_ADDR:.*]] = alloca i32, align 4592// OGCG: %[[A_VAL:.*]] = load i32, ptr %[[A_ADDR]], align 4593// OGCG: switch i32 %[[A_VAL]], label %[[DEFAULT:.*]] [594// OGCG: i32 3, label %[[SW3:.*]]595// OGCG: i32 4, label %[[SW4:.*]]596// OGCG: ]597// OGCG: [[SW3]]:598// OGCG: br label %[[EPILOG:.*]]599// OGCG: [[DEFAULT]]:600// OGCG: br label %[[SW4]]601// OGCG: [[SW4]]:602// OGCG: br label %[[EPILOG]]603// OGCG: [[EPILOG]]:604// OGCG: ret void605 606void sw10(int a) {607 switch (a)608 {609 case 3:610 break;611 case 4:612 default:613 case 5:614 break;615 }616}617 618// CIR: cir.func{{.*}} @_Z4sw10i619// CIR: cir.switch (%[[A:.*]] : !s32i)620// CIR-NEXT: cir.case(equal, [#cir.int<3> : !s32i]) {621// CIR-NEXT: cir.break622// CIR-NEXT: }623// CIR-NEXT: cir.case(equal, [#cir.int<4> : !s32i]) {624// CIR-NEXT: cir.yield625// CIR-NEXT: }626// CIR-NEXT: cir.case(default, []) {627// CIR-NEXT: cir.yield628// CIR-NEXT: }629// CIR-NEXT: cir.case(equal, [#cir.int<5> : !s32i]) {630// CIR-NEXT: cir.break631// CIR-NEXT: }632 633// LLVM: define{{.*}} void @_Z4sw10i634// LLVM: switch i32 %[[COND:.*]], label %[[DEFAULT:.*]] [635// LLVM-DAG: i32 3, label %[[CASE_3:.*]]636// LLVM-DAG: i32 4, label %[[CASE_4:.*]]637// LLVM-DAG: i32 5, label %[[CASE_5:.*]]638// LLVM: ]639// LLVM: [[CASE_3]]:640// LLVM: br label %[[EXIT:.*]]641// LLVM: [[CASE_4]]:642// LLVM: br label %[[CASE4_CONT:.*]]643// LLVM: [[CASE4_CONT]]:644// LLVM: br label %[[DEFAULT]]645// LLVM: [[DEFAULT]]:646// LLVM: br label %[[DEFAULT_CONT:.*]]647// LLVM: [[DEFAULT_CONT]]:648// LLVM: br label %[[CASE_5]]649// LLVM: [[CASE_5]]:650// LLVM: br label %[[EXIT]]651// LLVM: [[EXIT]]:652// LLVM: br label %[[RET:.*]]653// LLVM: [[RET]]:654// LLVM: ret void655 656// OGCG: define{{.*}} void @_Z4sw10i657// OGCG: entry:658// OGCG: %[[A_ADDR:.*]] = alloca i32, align 4659// OGCG: %[[A_VAL:.*]] = load i32, ptr %[[A_ADDR]], align 4660// OGCG: switch i32 %[[A_VAL]], label %[[DEFAULT:.*]] [661// OGCG: i32 3, label %[[BB3:.*]]662// OGCG: i32 4, label %[[BB4:.*]]663// OGCG: i32 5, label %[[BB5:.*]]664// OGCG: ]665// OGCG: [[BB3]]:666// OGCG: br label %[[EPILOG:.*]]667// OGCG: [[BB4]]:668// OGCG: br label %[[DEFAULT]]669// OGCG: [[DEFAULT]]:670// OGCG: br label %[[BB5]]671// OGCG: [[BB5]]:672// OGCG: br label %[[EPILOG]]673// OGCG: [[EPILOG]]:674// OGCG: ret void675 676void sw11(int a) {677 switch (a)678 {679 case 3:680 break;681 case 4:682 case 5:683 default:684 case 6:685 case 7:686 break;687 }688}689 690// CIR: cir.func{{.*}} @_Z4sw11i691// CIR: cir.switch (%[[A:.*]] : !s32i)692// CIR-NEXT: cir.case(equal, [#cir.int<3> : !s32i]) {693// CIR-NEXT: cir.break694// CIR-NEXT: }695// CIR-NEXT: cir.case(equal, [#cir.int<4> : !s32i]) {696// CIR-NEXT: cir.yield697// CIR-NEXT: }698// CIR-NEXT: cir.case(equal, [#cir.int<5> : !s32i]) {699// CIR-NEXT: cir.yield700// CIR-NEXT: }701// CIR-NEXT: cir.case(default, []) {702// CIR-NEXT: cir.yield703// CIR-NEXT: }704// CIR-NEXT: cir.case(equal, [#cir.int<6> : !s32i]) {705// CIR-NEXT: cir.yield706// CIR-NEXT: }707// CIR-NEXT: cir.case(equal, [#cir.int<7> : !s32i]) {708// CIR-NEXT: cir.break709// CIR-NEXT: }710 711// LLVM: define{{.*}} void @_Z4sw11i712// LLVM: switch i32 %[[COND:.*]], label %[[DEFAULT:.*]] [713// LLVM-DAG: i32 3, label %[[CASE_3:.*]]714// LLVM-DAG: i32 4, label %[[CASE_4:.*]]715// LLVM-DAG: i32 5, label %[[CASE_5:.*]]716// LLVM-DAG: i32 6, label %[[CASE_6:.*]]717// LLVM-DAG: i32 7, label %[[CASE_7:.*]]718// LLVM: ]719// LLVM: [[CASE_3]]:720// LLVM: br label %[[EXIT:.*]]721// LLVM: [[CASE_4]]:722// LLVM: br label %[[CASE4_CONT:.*]]723// LLVM: [[CASE4_CONT]]:724// LLVM: br label %[[CASE_5]]725// LLVM: [[CASE_5]]:726// LLVM: br label %[[CASE5_CONT:.*]]727// LLVM: [[CASE5_CONT]]:728// LLVM: br label %[[DEFAULT]]729// LLVM: [[DEFAULT]]:730// LLVM: br label %[[DEFAULT_CONT:.*]]731// LLVM: [[DEFAULT_CONT]]:732// LLVM: br label %[[CASE_6]]733// LLVM: [[CASE_6]]:734// LLVM: br label %[[CASE6_CONT:.*]]735// LLVM: [[CASE6_CONT]]:736// LLVM: br label %[[CASE_7]]737// LLVM: [[CASE_7]]:738// LLVM: br label %[[EXIT]]739// LLVM: [[EXIT]]:740// LLVM: br label %[[RET:.*]]741// LLVM: [[RET]]:742// LLVM: ret void743 744// OGCG: define{{.*}} void @_Z4sw11i745// OGCG: entry:746// OGCG: %[[A_ADDR:.*]] = alloca i32, align 4747// OGCG: %[[A_VAL:.*]] = load i32, ptr %[[A_ADDR]], align 4748// OGCG: switch i32 %[[A_VAL]], label %[[DEFAULT:.*]] [749// OGCG: i32 3, label %[[BB3:.*]]750// OGCG: i32 4, label %[[BB4:.*]]751// OGCG: i32 5, label %[[BB4]]752// OGCG: i32 6, label %[[BB6:.*]]753// OGCG: i32 7, label %[[BB6]]754// OGCG: ]755// OGCG: [[BB3]]:756// OGCG: br label %[[EPILOG:.*]]757// OGCG: [[BB4]]:758// OGCG: br label %[[DEFAULT]]759// OGCG: [[DEFAULT]]:760// OGCG: br label %[[BB6]]761// OGCG: [[BB6]]:762// OGCG: br label %[[EPILOG]]763// OGCG: [[EPILOG]]:764// OGCG: ret void765 766void sw12(int a) {767 switch (a)768 {769 case 3:770 return;771 break;772 }773}774 775// CIR: cir.func{{.*}} @_Z4sw12i776// CIR: cir.scope {777// CIR: cir.switch778// CIR-NEXT: cir.case(equal, [#cir.int<3> : !s32i]) {779// CIR-NEXT: cir.return780// CIR-NEXT: ^bb1: // no predecessors781// CIR-NEXT: cir.break782// CIR-NEXT: }783 784// LLVM: define{{.*}} void @_Z4sw12i785// LLVM: switch i32 %[[COND:.*]], label %[[EXIT:.*]] [786// LLVM-DAG: i32 3, label %[[CASE_3:.*]]787// LLVM: ]788// LLVM: [[CASE_3]]:789// LLVM: ret void790// LLVM: [[UNREACHABLE:.*]]:791// LLVM: br label %[[EXIT:.*]]792// LLVM: [[EXIT]]:793// LLVM: br label %[[RET:.*]]794// LLVM: [[RET]]:795// LLVM: ret void796 797// OGCG: define{{.*}} void @_Z4sw12i798// OGCG: entry:799// OGCG: %[[A_ADDR:.*]] = alloca i32, align 4800// OGCG: %[[A_VAL:.*]] = load i32, ptr %[[A_ADDR]], align 4801// OGCG: switch i32 %[[A_VAL]], label %[[SW_DEFAULT:.*]] [802// OGCG: i32 3, label %[[SW3:.*]]803// OGCG: ]804// OGCG: [[SW3]]:805// OGCG: br label %[[SW_DEFAULT]]806// OGCG: [[SW_DEFAULT]]:807// OGCG: ret void808 809void sw13(int a, int b) {810 switch (a) {811 case 1:812 switch (b) {813 case 2:814 break;815 }816 }817}818 819// CIR: cir.func{{.*}} @_Z4sw13ii820// CIR: cir.scope {821// CIR: cir.switch822// CIR-NEXT: cir.case(equal, [#cir.int<1> : !s32i]) {823// CIR-NEXT: cir.scope {824// CIR: cir.switch825// CIR-NEXT: cir.case(equal, [#cir.int<2> : !s32i]) {826// CIR-NEXT: cir.break827// CIR-NEXT: }828// CIR-NEXT: cir.yield829// CIR-NEXT: }830// CIR-NEXT: }831// CIR: cir.yield832// CIR: }833// CIR: cir.return834 835// LLVM: define{{.*}} void @_Z4sw13ii836// LLVM: switch i32 %[[COND:.*]], label %[[OUTER_EXIT:.*]] [837// LLVM-DAG: i32 1, label %[[CASE_A_1:.*]]838// LLVM: ]839// LLVM: [[CASE_A_1]]:840// LLVM: br label %[[LOAD_B:.*]]841// LLVM: [[LOAD_B]]:842// LLVM: %[[B_VAL:.*]] = load i32, ptr %[[B_ADDR:.*]], align 4843// LLVM: br label %[[INNER_SWITCH:.*]]844// LLVM: [[INNER_SWITCH]]:845// LLVM: switch i32 %[[B_VAL]], label %[[INNER_EXIT:.*]] [846// LLVM-DAG: i32 2, label %[[CASE_B_2:.*]]847// LLVM: ]848// LLVM: [[CASE_B_2]]:849// LLVM: br label %[[INNER_EXIT]]850// LLVM: [[INNER_EXIT]]:851// LLVM: br label %[[INNER_EXIT_CONT:.*]]852// LLVM: [[INNER_EXIT_CONT]]:853// LLVM: br label %[[MERGE:.*]]854// LLVM: [[MERGE]]:855// LLVM: br label %[[OUTER_EXIT]]856// LLVM: [[OUTER_EXIT]]:857// LLVM: br label %[[EXIT:.*]]858// LLVM: [[EXIT]]:859// LLVM: ret void860 861// OGCG: define{{.*}} void @_Z4sw13ii862// OGCG: entry:863// OGCG: %[[A_ADDR:.*]] = alloca i32, align 4864// OGCG: %[[B_ADDR:.*]] = alloca i32, align 4865// OGCG: %[[A_VAL:.*]] = load i32, ptr %[[A_ADDR]], align 4866// OGCG: switch i32 %[[A_VAL]], label %[[EPILOG2:.*]] [867// OGCG: i32 1, label %[[SW1:.*]]868// OGCG: ]869// OGCG: [[SW1]]:870// OGCG: %[[B_VAL:.*]] = load i32, ptr %[[B_ADDR]], align 4871// OGCG: switch i32 %[[B_VAL]], label %[[EPILOG:.*]] [872// OGCG: i32 2, label %[[SW12:.*]]873// OGCG: ]874// OGCG: [[SW12]]:875// OGCG: br label %[[EPILOG]]876// OGCG: [[EPILOG]]:877// OGCG: br label %[[EPILOG2]]878// OGCG: [[EPILOG2]]:879// OGCG: ret void880 881void sw14(int x) {882 switch (x) {883 case 1:884 case 2:885 case 3 ... 6:886 case 7:887 break;888 default:889 break;890 }891}892 893// CIR: cir.func{{.*}} @_Z4sw14i894// CIR: cir.switch895// CIR-NEXT: cir.case(equal, [#cir.int<1> : !s32i]) {896// CIR-NEXT: cir.yield897// CIR-NEXT: }898// CIR-NEXT: cir.case(equal, [#cir.int<2> : !s32i]) {899// CIR-NEXT: cir.yield900// CIR-NEXT: }901// CIR-NEXT: cir.case(range, [#cir.int<3> : !s32i, #cir.int<6> : !s32i]) {902// CIR-NEXT: cir.yield903// CIR-NEXT: }904// CIR-NEXT: cir.case(equal, [#cir.int<7> : !s32i]) {905// CIR-NEXT: cir.break906// CIR-NEXT: }907// CIR-NEXT: cir.case(default, []) {908// CIR-NEXT: cir.break909// CIR-NEXT: }910 911// LLVM: define{{.*}} void @_Z4sw14i912// LLVM: switch i32 %[[COND:.*]], label %[[DEFAULT:.*]] [913// LLVM-DAG: i32 1, label %[[CASE1:.*]]914// LLVM-DAG: i32 2, label %[[CASE2:.*]]915// LLVM-DAG: i32 3, label %[[CASE3_TO_6:.*]]916// LLVM-DAG: i32 4, label %[[CASE3_TO_6]]917// LLVM-DAG: i32 5, label %[[CASE3_TO_6]]918// LLVM-DAG: i32 6, label %[[CASE3_TO_6]]919// LLVM-DAG: i32 7, label %[[CASE7:.*]]920// LLVM: ]921// LLVM: [[CASE1]]:922// LLVM: br label %[[AFTER1:.*]]923// LLVM: [[AFTER1]]:924// LLVM: br label %[[CASE2]]925// LLVM: [[CASE2]]:926// LLVM: br label %[[AFTER2:.*]]927// LLVM: [[AFTER2]]:928// LLVM: br label %[[CASE3_TO_6]]929// LLVM: [[CASE3_TO_6]]:930// LLVM: br label %[[AFTER3_6:.*]]931// LLVM: [[AFTER3_6]]:932// LLVM: br label %[[CASE7]]933// LLVM: [[CASE7]]:934// LLVM: br label %[[EXIT1:.*]]935// LLVM: [[DEFAULT]]:936// LLVM: br label %[[EXIT1]]937// LLVM: [[EXIT1]]:938// LLVM: br label %[[RET:.*]]939// LLVM: [[RET]]:940// LLVM: ret void941 942// OGCG: define{{.*}} void @_Z4sw14i943// OGCG: entry:944// OGCG: %[[X_ADDR:.*]] = alloca i32, align 4945// OGCG: store i32 %x, ptr %[[X_ADDR]], align 4946// OGCG: %[[X_VAL:.*]] = load i32, ptr %[[X_ADDR]], align 4947// OGCG: switch i32 %[[X_VAL]], label %[[DEFAULT:.*]] [948// OGCG-DAG: i32 1, label %[[BB1:.*]]949// OGCG-DAG: i32 2, label %[[BB1]]950// OGCG-DAG: i32 3, label %[[BB2:.*]]951// OGCG-DAG: i32 4, label %[[BB2]]952// OGCG-DAG: i32 5, label %[[BB2]]953// OGCG-DAG: i32 6, label %[[BB2]]954// OGCG-DAG: i32 7, label %[[BB3:.*]]955// OGCG: ]956// OGCG: [[BB1]]:957// OGCG: br label %[[BB2]]958// OGCG: [[BB2]]:959// OGCG: br label %[[BB3]]960// OGCG: [[BB3]]:961// OGCG: br label %[[EPILOG:.*]]962// OGCG: [[DEFAULT]]:963// OGCG: br label %[[EPILOG]]964// OGCG: [[EPILOG]]:965// OGCG: ret void966 967void sw15(int x) {968 int y;969 switch (x) {970 case 1:971 case 2:972 y = 0;973 case 3:974 break;975 default:976 break;977 }978}979 980// CIR: cir.func{{.*}} @_Z4sw15i981// CIR: %[[Y:.*]] = cir.alloca !s32i, !cir.ptr<!s32i>, ["y"]982// CIR: cir.switch983// CIR-NEXT: cir.case(equal, [#cir.int<1> : !s32i]) {984// CIR-NEXT: cir.yield985// CIR-NEXT: }986// CIR-NEXT: cir.case(equal, [#cir.int<2> : !s32i]) {987// CIR-NEXT: %[[ZERO:.*]] = cir.const #cir.int<0> : !s32i988// CIR-NEXT: cir.store{{.*}} %[[ZERO]], %[[Y]] : !s32i, !cir.ptr<!s32i>989// CIR-NEXT: cir.yield990// CIR-NEXT: }991// CIR-NEXT: cir.case(equal, [#cir.int<3> : !s32i]) {992// CIR-NEXT: cir.break993// CIR-NEXT: }994// CIR-NEXT: cir.case(default, []) {995// CIR-NEXT: cir.break996// CIR-NEXT: }997 998// LLVM: define{{.*}} void @_Z4sw15i999// LLVM: switch i32 %[[COND:.*]], label %[[DEFAULT:.*]] [1000// LLVM-DAG: i32 1, label %[[CASE1:.*]]1001// LLVM-DAG: i32 2, label %[[CASE2:.*]]1002// LLVM-DAG: i32 3, label %[[CASE3:.*]]1003// LLVM: ]1004// LLVM: [[CASE1]]:1005// LLVM: br label %[[CASE1_CONT:.*]]1006// LLVM: [[CASE1_CONT]]:1007// LLVM: br label %[[CASE2]]1008// LLVM: [[CASE2]]:1009// LLVM: store i32 0, ptr %[[Y_ADDR:.*]], align 41010// LLVM: br label %[[CASE2_CONT:.*]]1011// LLVM: [[CASE2_CONT]]:1012// LLVM: br label %[[CASE3]]1013// LLVM: [[CASE3]]:1014// LLVM: br label %[[EXIT:.*]]1015// LLVM: [[DEFAULT]]:1016// LLVM: br label %[[EXIT]]1017// LLVM: [[EXIT]]:1018// LLVM: br label %[[RET:.*]]1019// LLVM: [[RET]]:1020// LLVM: ret void1021 1022// OGCG: define{{.*}} void @_Z4sw15i1023// OGCG: entry:1024// OGCG: %[[X_ADDR:.*]] = alloca i32, align 41025// OGCG: %[[Y:.*]] = alloca i32, align 41026// OGCG: store i32 %x, ptr %[[X_ADDR]], align 41027// OGCG: %[[X_VAL:.*]] = load i32, ptr %[[X_ADDR]], align 41028// OGCG: switch i32 %[[X_VAL]], label %[[DEFAULT:.*]] [1029// OGCG-DAG: i32 1, label %[[BB0:.*]]1030// OGCG-DAG: i32 2, label %[[BB0]]1031// OGCG-DAG: i32 3, label %[[BB1:.*]]1032// OGCG: ]1033// OGCG: [[BB0]]:1034// OGCG: store i32 0, ptr %[[Y]], align 41035// OGCG: br label %[[BB1]]1036// OGCG: [[BB1]]:1037// OGCG: br label %[[EPILOG:.*]]1038// OGCG: [[DEFAULT]]:1039// OGCG: br label %[[EPILOG]]1040// OGCG: [[EPILOG]]:1041// OGCG: ret void1042 1043int nested_switch(int a) {1044 switch (int b = 1; a) {1045 case 0:1046 b = b + 1;1047 case 1:1048 return b;1049 case 2: {1050 b = b + 1;1051 if (a > 1000) {1052 case 9:1053 b = a + b;1054 }1055 if (a > 500) {1056 case 7:1057 return a + b;1058 }1059 break;1060 }1061 }1062 1063 return 0;1064}1065 1066// CIR: cir.switch (%[[COND:.*]] : !s32i) {1067// CIR: cir.case(equal, [#cir.int<0> : !s32i]) {1068// CIR: cir.yield1069// CIR: }1070// CIR: cir.case(equal, [#cir.int<1> : !s32i]) {1071// CIR: cir.return1072// CIR: }1073// CIR: cir.case(equal, [#cir.int<2> : !s32i]) {1074// CIR: cir.scope {1075// CIR: cir.scope {1076// CIR: cir.if1077// CIR: cir.case(equal, [#cir.int<9> : !s32i]) {1078// CIR: cir.yield1079// CIR: cir.scope {1080// CIR: cir.if1081// CIR: cir.case(equal, [#cir.int<7> : !s32i]) {1082// CIR: cir.return1083 1084// LLVM: define{{.*}} i32 @_Z13nested_switchi1085// LLVM: %[[B_ADDR:.*]] = alloca i32, i64 1, align 41086// LLVM: %[[A_ADDR:.*]] = alloca i32, i64 1, align 41087// LLVM: %[[RES_ADDR:.*]] = alloca i32, i64 1, align 41088// LLVM: store i32 %[[ARG:.*]], ptr %[[A_ADDR]], align 41089// LLVM: br label %[[ENTRY:.*]]1090// LLVM: [[ENTRY]]:1091// LLVM: store i32 1, ptr %[[B_ADDR]], align 41092// LLVM: %[[A_VAL:.*]] = load i32, ptr %[[A_ADDR]], align 41093// LLVM: br label %[[SWITCH:.*]]1094// LLVM: [[SWITCH]]:1095// LLVM: switch i32 %[[A_VAL]], label %[[EXIT:.*]] [1096// LLVM-DAG: i32 0, label %[[CASE0:.*]]1097// LLVM-DAG: i32 1, label %[[CASE1:.*]]1098// LLVM-DAG: i32 2, label %[[CASE2:.*]]1099// LLVM-DAG: i32 9, label %[[CASE9:.*]]1100// LLVM-DAG: i32 7, label %[[CASE7:.*]]1101// LLVM: ]1102// LLVM: [[CASE0]]:1103// LLVM: %[[B0:.*]] = load i32, ptr %[[B_ADDR]], align 41104// LLVM: %[[B1:.*]] = add nsw i32 %[[B0]], 11105// LLVM: store i32 %[[B1]], ptr %[[B_ADDR]], align 41106// LLVM: br label %[[CASE0_CONT:.*]]1107// LLVM: [[CASE0_CONT]]:1108// LLVM: br label %[[CASE1]]1109// LLVM: [[CASE1]]:1110// LLVM: %[[B1a:.*]] = load i32, ptr %[[B_ADDR]], align 41111// LLVM: store i32 %[[B1a]], ptr %[[RES_ADDR]], align 41112// LLVM: %[[RET1:.*]] = load i32, ptr %[[RES_ADDR]], align 41113// LLVM: ret i32 %[[RET1]]1114// LLVM: [[CASE2]]:1115// LLVM: br label %[[CASE2_BODY:.*]]1116// LLVM: [[CASE2_BODY]]:1117// LLVM: %[[B2:.*]] = load i32, ptr %[[B_ADDR]], align 41118// LLVM: %[[B3:.*]] = add nsw i32 %[[B2]], 11119// LLVM: store i32 %[[B3]], ptr %[[B_ADDR]], align 41120// LLVM: br label %[[CASE2_CONT:.*]]1121// LLVM: [[CASE9]]:1122// LLVM: %[[A9:.*]] = load i32, ptr %[[A_ADDR]], align 41123// LLVM: %[[B4:.*]] = load i32, ptr %[[B_ADDR]], align 41124// LLVM: %[[SUM9:.*]] = add nsw i32 %[[A9]], %[[B4]]1125// LLVM: store i32 %[[SUM9]], ptr %[[B_ADDR]], align 41126// LLVM: br label %[[CASE2_CONT1:.*]]1127// LLVM: [[CASE7]]:1128// LLVM: %[[A7:.*]] = load i32, ptr %[[A_ADDR]], align 41129// LLVM: %[[B5:.*]] = load i32, ptr %[[B_ADDR]], align 41130// LLVM: %[[SUM7:.*]] = add nsw i32 %[[A7]], %[[B5]]1131// LLVM: store i32 %[[SUM7]], ptr %[[RES_ADDR]], align 41132// LLVM: %[[RET7:.*]] = load i32, ptr %[[RES_ADDR]], align 41133// LLVM: ret i32 %[[RET7]]1134// LLVM: [[EXIT]]:1135// LLVM: store i32 0, ptr %[[RES_ADDR]], align 41136// LLVM: %[[RET0:.*]] = load i32, ptr %[[RES_ADDR]], align 41137// LLVM: ret i32 %[[RET0]]1138 1139// OGCG: define{{.*}} i32 @_Z13nested_switchi1140// OGCG: entry:1141// OGCG: %[[RETVAL:.*]] = alloca i32, align 41142// OGCG: %[[A_ADDR:.*]] = alloca i32, align 41143// OGCG: %[[B:.*]] = alloca i32, align 41144// OGCG: %[[A_VAL:.*]] = load i32, ptr %[[A_ADDR]], align 41145// OGCG: switch i32 %[[A_VAL]], label %[[EPILOG:.*]] [1146// OGCG: i32 0, label %[[SW0:.*]]1147// OGCG: i32 1, label %[[SW1:.*]]1148// OGCG: i32 2, label %[[SW2:.*]]1149// OGCG: i32 9, label %[[SW4:.*]]1150// OGCG: i32 7, label %[[SW8:.*]]1151// OGCG: ]1152// OGCG: [[SW0]]:1153// OGCG: %[[B_VAL0:.*]] = load i32, ptr %[[B]], align 41154// OGCG: %[[ADD0:.*]] = add nsw i32 %[[B_VAL0]], 11155// OGCG: br label %[[SW1]]1156// OGCG: [[SW1]]:1157// OGCG: %[[B_VAL1:.*]] = load i32, ptr %[[B]], align 41158// OGCG: br label %[[RETURN:.*]]1159// OGCG: [[SW2]]:1160// OGCG: %[[B_VAL2:.*]] = load i32, ptr %[[B]], align 41161// OGCG: %[[ADD2:.*]] = add nsw i32 %[[B_VAL2]], 11162// OGCG: %[[A_VAL2:.*]] = load i32, ptr %[[A_ADDR]], align 41163// OGCG: %[[CMP1000:.*]] = icmp sgt i32 %[[A_VAL2]], 10001164// OGCG: br i1 %[[CMP1000]], label %[[IFTHEN:.*]], label %[[IFEND:.*]]1165// OGCG: [[IFTHEN]]:1166// OGCG: br label %[[SW4]]1167// OGCG: [[SW4]]:1168// OGCG: %[[A_VAL4:.*]] = load i32, ptr %[[A_ADDR]], align 41169// OGCG: %[[B_VAL4:.*]] = load i32, ptr %[[B]], align 41170// OGCG: %[[ADD4:.*]] = add nsw i32 %[[A_VAL4]], %[[B_VAL4]]1171// OGCG: br label %[[IFEND]]1172// OGCG: [[IFEND]]:1173// OGCG: %[[A_VAL5:.*]] = load i32, ptr %[[A_ADDR]], align 41174// OGCG: %[[CMP500:.*]] = icmp sgt i32 %[[A_VAL5]], 5001175// OGCG: br i1 %[[CMP500]], label %[[IFTHEN7:.*]], label %[[IFEND10:.*]]1176// OGCG: [[IFTHEN7]]:1177// OGCG: br label %[[SW8]]1178// OGCG: [[SW8]]:1179// OGCG: %[[A_VAL8:.*]] = load i32, ptr %[[A_ADDR]], align 41180// OGCG: %[[B_VAL8:.*]] = load i32, ptr %[[B]], align 41181// OGCG: %[[ADD8:.*]] = add nsw i32 %[[A_VAL8]], %[[B_VAL8]]1182// OGCG: br label %[[RETURN]]1183// OGCG: [[IFEND10]]:1184// OGCG: br label %[[EPILOG]]1185// OGCG: [[EPILOG]]:1186 1187int sw_return_multi_cases(int x) {1188 switch (x) {1189 case 0:1190 return 0;1191 case 1:1192 return 1;1193 case 2:1194 return 2;1195 default:1196 return -1;1197 }1198}1199 1200// CIR-LABEL: cir.func{{.*}} @_Z21sw_return_multi_casesi1201// CIR: cir.switch (%{{.*}} : !s32i) {1202// CIR-NEXT: cir.case(equal, [#cir.int<0> : !s32i]) {1203// CIR: %[[ZERO:.*]] = cir.const #cir.int<0> : !s32i1204// CIR: cir.store{{.*}} %[[ZERO]], %{{.*}} : !s32i, !cir.ptr<!s32i>1205// CIR: %[[RET0:.*]] = cir.load{{.*}} %{{.*}} : !cir.ptr<!s32i>, !s32i1206// CIR-NEXT: cir.return %[[RET0]] : !s32i1207// CIR-NEXT: }1208// CIR-NEXT: cir.case(equal, [#cir.int<1> : !s32i]) {1209// CIR: %[[ONE:.*]] = cir.const #cir.int<1> : !s32i1210// CIR: cir.store{{.*}} %[[ONE]], %{{.*}} : !s32i, !cir.ptr<!s32i>1211// CIR: %[[RET1:.*]] = cir.load{{.*}} %{{.*}} : !cir.ptr<!s32i>, !s32i1212// CIR-NEXT: cir.return %[[RET1]] : !s32i1213// CIR-NEXT: }1214// CIR-NEXT: cir.case(equal, [#cir.int<2> : !s32i]) {1215// CIR: %[[TWO:.*]] = cir.const #cir.int<2> : !s32i1216// CIR: cir.store{{.*}} %[[TWO]], %{{.*}} : !s32i, !cir.ptr<!s32i>1217// CIR: %[[RET2:.*]] = cir.load{{.*}} %{{.*}} : !cir.ptr<!s32i>, !s32i1218// CIR-NEXT: cir.return %[[RET2]] : !s32i1219// CIR-NEXT: }1220// CIR-NEXT: cir.case(default, []) {1221// CIR: %[[ONE:.*]] = cir.const #cir.int<1> : !s32i1222// CIR: %[[NEG:.*]] = cir.unary(minus, %[[ONE]]) {{.*}} : !s32i, !s32i1223// CIR: cir.store{{.*}} %[[NEG]], %{{.*}} : !s32i, !cir.ptr<!s32i>1224// CIR: %[[RETDEF:.*]] = cir.load{{.*}} %{{.*}} : !cir.ptr<!s32i>, !s32i1225// CIR-NEXT: cir.return %[[RETDEF]] : !s32i1226// CIR-NEXT: }1227// CIR-NEXT: cir.yield1228 1229// LLVM-LABEL: define{{.*}} i32 @_Z21sw_return_multi_casesi1230// LLVM: switch i32 %{{.*}}, label %[[DEFAULT:.*]] [1231// LLVM-DAG: i32 0, label %[[CASE0:.*]]1232// LLVM-DAG: i32 1, label %[[CASE1:.*]]1233// LLVM-DAG: i32 2, label %[[CASE2:.*]]1234// LLVM: ]1235// LLVM: [[CASE0]]:1236// LLVM: store i32 0, ptr %{{.*}}, align 41237// LLVM: %{{.*}} = load i32, ptr %{{.*}}, align 41238// LLVM: ret i32 %{{.*}}1239// LLVM: [[CASE1]]:1240// LLVM: store i32 1, ptr %{{.*}}, align 41241// LLVM: %{{.*}} = load i32, ptr %{{.*}}, align 41242// LLVM: ret i32 %{{.*}}1243// LLVM: [[CASE2]]:1244// LLVM: store i32 2, ptr %{{.*}}, align 41245// LLVM: %{{.*}} = load i32, ptr %{{.*}}, align 41246// LLVM: ret i32 %{{.*}}1247// LLVM: [[DEFAULT]]:1248// LLVM: store i32 -1, ptr %{{.*}}, align 41249// LLVM: %{{.*}} = load i32, ptr %{{.*}}, align 41250// LLVM: ret i32 %{{.*}}1251 1252// OGCG-LABEL: define{{.*}} i32 @_Z21sw_return_multi_casesi1253// OGCG: entry:1254// OGCG: %[[RETVAL:.*]] = alloca i32, align 41255// OGCG: %[[X_ADDR:.*]] = alloca i32, align 41256// OGCG: %[[X_VAL:.*]] = load i32, ptr %[[X_ADDR]], align 41257// OGCG: switch i32 %[[X_VAL]], label %[[DEFAULT:.*]] [1258// OGCG-DAG: i32 0, label %[[SW0:.*]]1259// OGCG-DAG: i32 1, label %[[SW1:.*]]1260// OGCG-DAG: i32 2, label %[[SW2:.*]]1261// OGCG: ]1262// OGCG: [[SW0]]:1263// OGCG: br label %[[RETURN:.*]]1264// OGCG: [[SW1]]:1265// OGCG: br label %[[RETURN]]1266// OGCG: [[SW2]]:1267// OGCG: br label %[[RETURN]]1268// OGCG: [[DEFAULT]]:1269// OGCG: br label %[[RETURN]]1270// OGCG: [[RETURN]]:1271// OGCG: %[[RETVAL_LOAD:.*]] = load i32, ptr %[[RETVAL]], align 41272// OGCG: ret i32 %[[RETVAL_LOAD]]1273