197 lines · cpp
1// RUN: %clang_cc1 -std=c++20 -triple x86_64-unknown-linux-gnu -fcxx-exceptions -fexceptions -fclangir -emit-cir %s -o %t.cir2// RUN: FileCheck --input-file=%t.cir %s -check-prefix=CIR3// RUN: %clang_cc1 -std=c++20 -triple x86_64-unknown-linux-gnu -fcxx-exceptions -fexceptions -fclangir -emit-llvm %s -o %t-cir.ll4// RUN: FileCheck --input-file=%t-cir.ll %s -check-prefix=LLVM5// RUN: %clang_cc1 -std=c++20 -triple x86_64-unknown-linux-gnu -fcxx-exceptions -fexceptions -emit-llvm %s -o %t.ll6// RUN: FileCheck --input-file=%t.ll %s -check-prefix=OGCG7 8void empty_try_block_with_catch_all() {9 try {} catch (...) {}10}11 12// CIR: cir.func{{.*}} @_Z30empty_try_block_with_catch_allv()13// CIR: cir.return14 15// LLVM: define{{.*}} void @_Z30empty_try_block_with_catch_allv()16// LLVM: ret void17 18// OGCG: define{{.*}} void @_Z30empty_try_block_with_catch_allv()19// OGCG: ret void20 21void empty_try_block_with_catch_with_int_exception() {22 try {} catch (int e) {}23}24 25// CIR: cir.func{{.*}} @_Z45empty_try_block_with_catch_with_int_exceptionv()26// CIR: cir.return27 28// LLVM: define{{.*}} void @_Z45empty_try_block_with_catch_with_int_exceptionv()29// LLVM: ret void30 31// OGCG: define{{.*}} void @_Z45empty_try_block_with_catch_with_int_exceptionv()32// OGCG: ret void33 34void try_catch_with_empty_catch_all() {35 int a = 1;36 try {37 return;38 ++a;39 } catch (...) {40 }41}42 43// CIR: %[[A_ADDR:.*]] = cir.alloca !s32i, !cir.ptr<!s32i>, ["a", init]44// CIR: %[[CONST_1:.*]] = cir.const #cir.int<1> : !s32i45// CIR: cir.store{{.*}} %[[CONST_1]], %[[A_ADDR]] : !s32i, !cir.ptr<!s32i46// CIR: cir.scope {47// CIR: cir.try {48// CIR: cir.return49// CIR: ^bb1: // no predecessors50// CIR: %[[TMP_A:.*]] = cir.load{{.*}} %[[A_ADDR]] : !cir.ptr<!s32i>, !s32i51// CIR: %[[RESULT:.*]] = cir.unary(inc, %[[TMP_A]]) nsw : !s32i, !s32i52// CIR: cir.store{{.*}} %[[RESULT]], %[[A_ADDR]] : !s32i, !cir.ptr<!s32i>53// CIR: cir.yield54// CIR: }55// CIR: }56 57// LLVM: %[[A_ADDR:.*]] = alloca i32, i64 1, align 458// LLVM: store i32 1, ptr %[[A_ADDR]], align 459// LLVM: br label %[[BB_2:.*]]60// LLVM: [[BB_2]]:61// LLVM: br label %[[BB_3:.*]]62// LLVM: [[BB_3]]:63// LLVM: ret void64// LLVM: [[BB_4:.*]]:65// LLVM: %[[TMP_A:.*]] = load i32, ptr %[[A_ADDR]], align 466// LLVM: %[[RESULT:.*]] = add nsw i32 %[[TMP_A]], 167// LLVM: store i32 %[[RESULT]], ptr %[[A_ADDR]], align 468// LLVM: br label %[[BB_7:.*]]69// LLVM: [[BB_7]]:70// LLVM: br label %[[BB_8:.*]]71// LLVM: [[BB_8]]:72// LLVM: ret void73 74// OGCG: %[[A_ADDR:.*]] = alloca i32, align 475// OGCG: store i32 1, ptr %[[A_ADDR]], align 476// OGCG: ret void77 78void try_catch_with_empty_catch_all_2() {79 int a = 1;80 try {81 ++a;82 return;83 } catch (...) {84 }85}86 87// CIR: %[[A_ADDR:.*]] = cir.alloca !s32i, !cir.ptr<!s32i>, ["a", init]88// CIR: %[[CONST_1:.*]] = cir.const #cir.int<1> : !s32i89// CIR: cir.store{{.*}} %[[CONST_1]], %[[A_ADDR]] : !s32i, !cir.ptr<!s32i>90// CIR: cir.scope {91// CIR: cir.try {92// CIR: %[[TMP_A:.*]] = cir.load{{.*}} %[[A_ADDR]] : !cir.ptr<!s32i>, !s32i93// CIR: %[[RESULT:.*]] = cir.unary(inc, %[[TMP_A]]) nsw : !s32i, !s32i94// CIR: cir.store{{.*}} %[[RESULT]], %[[A_ADDR]] : !s32i, !cir.ptr<!s32i>95// CIR: cir.return96// CIR: }97// CIR: }98 99// LLVM: %[[A_ADDR]] = alloca i32, i64 1, align 4100// LLVM: store i32 1, ptr %[[A_ADDR]], align 4101// LLVM: br label %[[BB_2:.*]]102// LLVM: [[BB_2]]:103// LLVM: br label %[[BB_3:.*]]104// LLVM: [[BB_3]]:105// LLVM: %[[TMP_A:.*]] = load i32, ptr %[[A_ADDR]], align 4106// LLVM: %[[RESULT:.*]] = add nsw i32 %[[TMP_A:.*]], 1107// LLVM: store i32 %[[RESULT]], ptr %[[A_ADDR]], align 4108// LLVM: ret void109// LLVM: [[BB_6:.*]]:110// LLVM: br label %[[BB_7:.*]]111// LLVM: [[BB_7]]:112// LLVM: ret void113 114// OGCG: %[[A_ADDR:.*]] = alloca i32, align 4115// OGCG: store i32 1, ptr %[[A_ADDR]], align 4116// OGCG: %[[TMP_A:.*]] = load i32, ptr %[[A_ADDR]], align 4117// OGCG: %[[RESULT:.*]] = add nsw i32 %[[TMP_A]], 1118// OGCG: store i32 %[[RESULT]], ptr %[[A_ADDR]], align 4119// OGCG: ret void120 121void try_catch_with_alloca() {122 try {123 int a;124 int b;125 int c = a + b;126 } catch (...) {127 }128}129 130// CIR: cir.scope {131// CIR: %[[A_ADDR:.*]] = cir.alloca !s32i, !cir.ptr<!s32i>, ["a"]132// CIR: %[[B_ADDR:.*]] = cir.alloca !s32i, !cir.ptr<!s32i>, ["b"]133// CIR: %[[C_ADDR:.*]] = cir.alloca !s32i, !cir.ptr<!s32i>, ["c", init]134// CIR: cir.try {135// CIR: %[[TMP_A:.*]] = cir.load{{.*}} %[[A_ADDR]] : !cir.ptr<!s32i>, !s32i136// CIR: %[[TMP_B:.*]] = cir.load{{.*}} %[[B_ADDR]] : !cir.ptr<!s32i>, !s32i137// CIR: %[[RESULT:.*]] = cir.binop(add, %[[TMP_A]], %[[TMP_B]]) nsw : !s32i138// CIR: cir.store{{.*}} %[[RESULT]], %[[C_ADDR]] : !s32i, !cir.ptr<!s32i>139// CIR: cir.yield140// CIR: }141// CIR: }142 143// LLVM: %[[A_ADDR:.*]] = alloca i32, i64 1, align 4144// LLVM: %[[B_ADDR:.*]] = alloca i32, i64 1, align 4145// LLVM: %[[C_ADDR:.*]] = alloca i32, i64 1, align 4146// LLVM: br label %[[LABEL_1:.*]]147// LLVM: [[LABEL_1]]:148// LLVM: br label %[[LABEL_2:.*]]149// LLVM: [[LABEL_2]]:150// LLVM: %[[TMP_A:.*]] = load i32, ptr %[[A_ADDR]], align 4151// LLVM: %[[TMP_B:.*]] = load i32, ptr %[[B_ADDR]], align 4152// LLVM: %[[RESULT:.*]] = add nsw i32 %[[TMP_A]], %[[TMP_B]]153// LLVM: store i32 %[[RESULT]], ptr %[[C_ADDR]], align 4154// LLVM: br label %[[LABEL_3:.*]]155// LLVM: [[LABEL_3]]:156// LLVM: br label %[[LABEL_4:.*]]157// LLVM: [[LABEL_4]]:158// LLVM: ret void159 160// OGCG: %[[A_ADDR:.*]] = alloca i32, align 4161// OGCG: %[[B_ADDR:.*]] = alloca i32, align 4162// OGCG: %[[C_ADDR:.*]] = alloca i32, align 4163// OGCG: %[[TMP_A:.*]] = load i32, ptr %[[A_ADDR]], align 4164// OGCG: %[[TMP_B:.*]] = load i32, ptr %[[B_ADDR]], align 4165// OGCG: %[[RESULT:.*]] = add nsw i32 %[[TMP_A]], %[[TMP_B]]166// OGCG: store i32 %[[RESULT]], ptr %[[C_ADDR]], align 4167 168void function_with_noexcept() noexcept;169 170void calling_noexcept_function_inside_try_block() {171 try {172 function_with_noexcept();173 } catch (...) {174 }175}176 177// CIR: cir.scope {178// CIR: cir.try {179// CIR: cir.call @_Z22function_with_noexceptv() nothrow : () -> ()180// CIR: cir.yield181// CIR: }182// CIR: }183 184// LLVM: br label %[[LABEL_1:.*]]185// LLVM: [[LABEL_1]]:186// LLVM: br label %[[LABEL_2:.*]]187// LLVM: [[LABEL_2]]:188// LLVM: call void @_Z22function_with_noexceptv()189// LLVM: br label %[[LABEL_3:.*]]190// LLVM: [[LABEL_3]]:191// LLVM: br label %[[LABEL_4:.*]]192// LLVM: [[LABEL_4]]:193// LLVM: ret void194 195// OGCG: call void @_Z22function_with_noexceptv()196// OGCG: ret void197