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1// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -fclangir -emit-cir %s -o %t.cir2// RUN: FileCheck --input-file=%t.cir %s --check-prefix=CIR3// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -fclangir -emit-llvm %s -o %t-cir.ll4// RUN: FileCheck --input-file=%t-cir.ll %s -check-prefix=LLVM5// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -emit-llvm %s -o %t.ll6// RUN: FileCheck --input-file=%t.ll %s -check-prefix=OGCG7 8typedef float __m128 __attribute__((__vector_size__(16), __aligned__(16)));9typedef double __m128d __attribute__((__vector_size__(16), __aligned__(16)));10 11__m128 test_cmpnleps(__m128 A, __m128 B) {12  // CIR-LABEL:   cir.func dso_local @test_cmpnleps(13  // CIR:           %[[ARG0:.*]]: !cir.vector<4 x !cir.float> {{.*}}, %[[ARG1:.*]]: !cir.vector<4 x !cir.float> {{.*}}) -> !cir.vector<4 x !cir.float> inline(never) {14  // CIR:           %[[ALLOCA_0:.*]] = cir.alloca !cir.vector<4 x !cir.float>, !cir.ptr<!cir.vector<4 x !cir.float>>, ["A", init] {alignment = 16 : i64}15  // CIR:           %[[ALLOCA_1:.*]] = cir.alloca !cir.vector<4 x !cir.float>, !cir.ptr<!cir.vector<4 x !cir.float>>, ["B", init] {alignment = 16 : i64}16  // CIR:           %[[ALLOCA_2:.*]] = cir.alloca !cir.vector<4 x !cir.float>, !cir.ptr<!cir.vector<4 x !cir.float>>, ["__retval"] {alignment = 16 : i64}17  // CIR:           cir.store %[[ARG0]], %[[ALLOCA_0]] : !cir.vector<4 x !cir.float>, !cir.ptr<!cir.vector<4 x !cir.float>>18  // CIR:           cir.store %[[ARG1]], %[[ALLOCA_1]] : !cir.vector<4 x !cir.float>, !cir.ptr<!cir.vector<4 x !cir.float>>19  // CIR:           %[[LOAD_0:.*]] = cir.load align(16) %[[ALLOCA_0]] : !cir.ptr<!cir.vector<4 x !cir.float>>, !cir.vector<4 x !cir.float>20  // CIR:           %[[LOAD_1:.*]] = cir.load align(16) %[[ALLOCA_1]] : !cir.ptr<!cir.vector<4 x !cir.float>>, !cir.vector<4 x !cir.float>21  // CIR:           %[[VEC_0:.*]] = cir.vec.cmp(le, %[[LOAD_0]], %[[LOAD_1]]) : !cir.vector<4 x !cir.float>, !cir.vector<4 x !s32i>22  // CIR:           %[[UNARY_0:.*]] = cir.unary(not, %[[VEC_0]]) : !cir.vector<4 x !s32i>, !cir.vector<4 x !s32i>23  // CIR:           %[[CAST_0:.*]] = cir.cast bitcast %[[UNARY_0]] : !cir.vector<4 x !s32i> -> !cir.vector<4 x !cir.float>24  // CIR:           cir.store %[[CAST_0]], %[[ALLOCA_2]] : !cir.vector<4 x !cir.float>, !cir.ptr<!cir.vector<4 x !cir.float>>25  // CIR:           %[[LOAD_2:.*]] = cir.load %[[ALLOCA_2]] : !cir.ptr<!cir.vector<4 x !cir.float>>, !cir.vector<4 x !cir.float>26  // CIR:           cir.return %[[LOAD_2]] : !cir.vector<4 x !cir.float>27  // CIR:         } 28 29  // LLVM-LABEL: define dso_local <4 x float> @test_cmpnleps(30  // LLVM-SAME: <4 x float> [[TMP0:%.*]], <4 x float> [[TMP1:%.*]]) #[[ATTR0:[0-9]+]] {31  // LLVM-NEXT:    [[TMP3:%.*]] = alloca <4 x float>, i64 1, align 1632  // LLVM-NEXT:    [[TMP4:%.*]] = alloca <4 x float>, i64 1, align 1633  // LLVM-NEXT:    [[TMP5:%.*]] = alloca <4 x float>, i64 1, align 1634  // LLVM-NEXT:    store <4 x float> [[TMP0]], ptr [[TMP3]], align 1635  // LLVM-NEXT:    store <4 x float> [[TMP1]], ptr [[TMP4]], align 1636  // LLVM-NEXT:    [[TMP6:%.*]] = load <4 x float>, ptr [[TMP3]], align 1637  // LLVM-NEXT:    [[TMP7:%.*]] = load <4 x float>, ptr [[TMP4]], align 1638  // LLVM-NEXT:    [[TMP8:%.*]] = fcmp ole <4 x float> [[TMP6]], [[TMP7]]39  // LLVM-NEXT:    [[TMP9:%.*]] = sext <4 x i1> [[TMP8]] to <4 x i32>40  // LLVM-NEXT:    [[TMP10:%.*]] = xor <4 x i32> [[TMP9]], splat (i32 -1)41  // LLVM-NEXT:    [[TMP11:%.*]] = bitcast <4 x i32> [[TMP10]] to <4 x float>42  // LLVM-NEXT:    store <4 x float> [[TMP11]], ptr [[TMP5]], align 1643  // LLVM-NEXT:    [[TMP12:%.*]] = load <4 x float>, ptr [[TMP5]], align 1644  // LLVM-NEXT:    ret <4 x float> [[TMP12]]45 46  // OGCG-LABEL: define dso_local <4 x float> @test_cmpnleps(47  // OGCG-SAME: <4 x float> noundef [[A:%.*]], <4 x float> noundef [[B:%.*]]) #[[ATTR0:[0-9]+]] {48  // OGCG-NEXT:  [[ENTRY:.*:]]49  // OGCG-NEXT:    [[A_ADDR:%.*]] = alloca <4 x float>, align 1650  // OGCG-NEXT:    [[B_ADDR:%.*]] = alloca <4 x float>, align 1651  // OGCG-NEXT:    store <4 x float> [[A]], ptr [[A_ADDR]], align 1652  // OGCG-NEXT:    store <4 x float> [[B]], ptr [[B_ADDR]], align 1653  // OGCG-NEXT:    [[TMP0:%.*]] = load <4 x float>, ptr [[A_ADDR]], align 1654  // OGCG-NEXT:    [[TMP1:%.*]] = load <4 x float>, ptr [[B_ADDR]], align 1655  // OGCG-NEXT:    [[TMP2:%.*]] = fcmp ugt <4 x float> [[TMP0]], [[TMP1]]56  // OGCG-NEXT:    [[TMP3:%.*]] = sext <4 x i1> [[TMP2]] to <4 x i32>57  // OGCG-NEXT:    [[TMP4:%.*]] = bitcast <4 x i32> [[TMP3]] to <4 x float>58  // OGCG-NEXT:    ret <4 x float> [[TMP4]]59  return __builtin_ia32_cmpnleps(A, B);60}61 62__m128d test_cmpnlepd(__m128d A, __m128d B) {63  // CIR-LABEL:   cir.func dso_local @test_cmpnlepd(64  // CIR:          %[[ARG0:.*]]: !cir.vector<2 x !cir.double> {{.*}}, %[[ARG1:.*]]: !cir.vector<2 x !cir.double> {{.*}}) -> !cir.vector<2 x !cir.double> inline(never) {65  // CIR:           %[[ALLOCA_0:.*]] = cir.alloca !cir.vector<2 x !cir.double>, !cir.ptr<!cir.vector<2 x !cir.double>>, ["A", init] {alignment = 16 : i64} 66  // CIR:           %[[ALLOCA_1:.*]] = cir.alloca !cir.vector<2 x !cir.double>, !cir.ptr<!cir.vector<2 x !cir.double>>, ["B", init] {alignment = 16 : i64} 67  // CIR:           %[[ALLOCA_2:.*]] = cir.alloca !cir.vector<2 x !cir.double>, !cir.ptr<!cir.vector<2 x !cir.double>>, ["__retval"] {alignment = 16 : i64} 68  // CIR:           cir.store %[[ARG0]], %[[ALLOCA_0]] : !cir.vector<2 x !cir.double>, !cir.ptr<!cir.vector<2 x !cir.double>> 69  // CIR:           cir.store %[[ARG1]], %[[ALLOCA_1]] : !cir.vector<2 x !cir.double>, !cir.ptr<!cir.vector<2 x !cir.double>> 70  // CIR:           %[[LOAD_0:.*]] = cir.load align(16) %[[ALLOCA_0]] : !cir.ptr<!cir.vector<2 x !cir.double>>, !cir.vector<2 x !cir.double> 71  // CIR:           %[[LOAD_1:.*]] = cir.load align(16) %[[ALLOCA_1]] : !cir.ptr<!cir.vector<2 x !cir.double>>, !cir.vector<2 x !cir.double> 72  // CIR:           %[[VEC_0:.*]] = cir.vec.cmp(le, %[[LOAD_0]], %[[LOAD_1]]) : !cir.vector<2 x !cir.double>, !cir.vector<2 x !s64i> 73  // CIR:           %[[UNARY_0:.*]] = cir.unary(not, %[[VEC_0]]) : !cir.vector<2 x !s64i>, !cir.vector<2 x !s64i> 74  // CIR:           %[[CAST_0:.*]] = cir.cast bitcast %[[UNARY_0]] : !cir.vector<2 x !s64i> -> !cir.vector<2 x !cir.double> 75  // CIR:           cir.store %[[CAST_0]], %[[ALLOCA_2]] : !cir.vector<2 x !cir.double>, !cir.ptr<!cir.vector<2 x !cir.double>> 76  // CIR:           %[[LOAD_2:.*]] = cir.load %[[ALLOCA_2]] : !cir.ptr<!cir.vector<2 x !cir.double>>, !cir.vector<2 x !cir.double> 77  // CIR:           cir.return %[[LOAD_2]] : !cir.vector<2 x !cir.double> 78  // CIR:         } 79 80  // LLVM-LABEL: define dso_local <2 x double> @test_cmpnlepd(81  // LLVM-SAME: <2 x double> [[TMP0:%.*]], <2 x double> [[TMP1:%.*]]) #[[ATTR0:[0-9]+]] {82  // LLVM-NEXT:    [[TMP3:%.*]] = alloca <2 x double>, i64 1, align 1683  // LLVM-NEXT:    [[TMP4:%.*]] = alloca <2 x double>, i64 1, align 1684  // LLVM-NEXT:    [[TMP5:%.*]] = alloca <2 x double>, i64 1, align 1685  // LLVM-NEXT:    store <2 x double> [[TMP0]], ptr [[TMP3]], align 1686  // LLVM-NEXT:    store <2 x double> [[TMP1]], ptr [[TMP4]], align 1687  // LLVM-NEXT:    [[TMP6:%.*]] = load <2 x double>, ptr [[TMP3]], align 1688  // LLVM-NEXT:    [[TMP7:%.*]] = load <2 x double>, ptr [[TMP4]], align 1689  // LLVM-NEXT:    [[TMP8:%.*]] = fcmp ole <2 x double> [[TMP6]], [[TMP7]]90  // LLVM-NEXT:    [[TMP9:%.*]] = sext <2 x i1> [[TMP8]] to <2 x i64>91  // LLVM-NEXT:    [[TMP10:%.*]] = xor <2 x i64> [[TMP9]], splat (i64 -1)92  // LLVM-NEXT:    [[TMP11:%.*]] = bitcast <2 x i64> [[TMP10]] to <2 x double>93  // LLVM-NEXT:    store <2 x double> [[TMP11]], ptr [[TMP5]], align 1694  // LLVM-NEXT:    [[TMP12:%.*]] = load <2 x double>, ptr [[TMP5]], align 1695  // LLVM-NEXT:    ret <2 x double> [[TMP12]]96 97  // OGCG-LABEL: define dso_local <2 x double> @test_cmpnlepd(98  // OGCG-SAME: <2 x double> noundef [[A:%.*]], <2 x double> noundef [[B:%.*]]) #[[ATTR0:[0-9]+]] {99  // OGCG-NEXT:  [[ENTRY:.*:]]100  // OGCG-NEXT:    [[A_ADDR:%.*]] = alloca <2 x double>, align 16101  // OGCG-NEXT:    [[B_ADDR:%.*]] = alloca <2 x double>, align 16102  // OGCG-NEXT:    store <2 x double> [[A]], ptr [[A_ADDR]], align 16103  // OGCG-NEXT:    store <2 x double> [[B]], ptr [[B_ADDR]], align 16104  // OGCG-NEXT:    [[TMP0:%.*]] = load <2 x double>, ptr [[A_ADDR]], align 16105  // OGCG-NEXT:    [[TMP1:%.*]] = load <2 x double>, ptr [[B_ADDR]], align 16106  // OGCG-NEXT:    [[TMP2:%.*]] = fcmp ugt <2 x double> [[TMP0]], [[TMP1]]107  // OGCG-NEXT:    [[TMP3:%.*]] = sext <2 x i1> [[TMP2]] to <2 x i64>108  // OGCG-NEXT:    [[TMP4:%.*]] = bitcast <2 x i64> [[TMP3]] to <2 x double>109  // OGCG-NEXT:    ret <2 x double> [[TMP4]]110 return  __builtin_ia32_cmpnlepd(A, B);111}112 113__m128 test_cmpnltps(__m128 A, __m128 B) {114  // CIR-LABEL:   cir.func dso_local @test_cmpnltps(115  // CIR-SAME:      %[[ARG0:.*]]: !cir.vector<4 x !cir.float> {{.*}}, %[[ARG1:.*]]: !cir.vector<4 x !cir.float> {{.*}}) -> !cir.vector<4 x !cir.float> inline(never) {116  // CIR:           %[[ALLOCA_0:.*]] = cir.alloca !cir.vector<4 x !cir.float>, !cir.ptr<!cir.vector<4 x !cir.float>>, ["A", init] {alignment = 16 : i64} 117  // CIR:           %[[ALLOCA_1:.*]] = cir.alloca !cir.vector<4 x !cir.float>, !cir.ptr<!cir.vector<4 x !cir.float>>, ["B", init] {alignment = 16 : i64} 118  // CIR:           %[[ALLOCA_2:.*]] = cir.alloca !cir.vector<4 x !cir.float>, !cir.ptr<!cir.vector<4 x !cir.float>>, ["__retval"] {alignment = 16 : i64} 119  // CIR:           cir.store %[[ARG0]], %[[ALLOCA_0]] : !cir.vector<4 x !cir.float>, !cir.ptr<!cir.vector<4 x !cir.float>> 120  // CIR:           cir.store %[[ARG1]], %[[ALLOCA_1]] : !cir.vector<4 x !cir.float>, !cir.ptr<!cir.vector<4 x !cir.float>> 121  // CIR:           %[[LOAD_0:.*]] = cir.load align(16) %[[ALLOCA_0]] : !cir.ptr<!cir.vector<4 x !cir.float>>, !cir.vector<4 x !cir.float> 122  // CIR:           %[[LOAD_1:.*]] = cir.load align(16) %[[ALLOCA_1]] : !cir.ptr<!cir.vector<4 x !cir.float>>, !cir.vector<4 x !cir.float> 123  // CIR:           %[[VEC_0:.*]] = cir.vec.cmp(lt, %[[LOAD_0]], %[[LOAD_1]]) : !cir.vector<4 x !cir.float>, !cir.vector<4 x !s32i> 124  // CIR:           %[[UNARY_0:.*]] = cir.unary(not, %[[VEC_0]]) : !cir.vector<4 x !s32i>, !cir.vector<4 x !s32i> 125  // CIR:           %[[CAST_0:.*]] = cir.cast bitcast %[[UNARY_0]] : !cir.vector<4 x !s32i> -> !cir.vector<4 x !cir.float> 126  // CIR:           cir.store %[[CAST_0]], %[[ALLOCA_2]] : !cir.vector<4 x !cir.float>, !cir.ptr<!cir.vector<4 x !cir.float>> 127  // CIR:           %[[LOAD_2:.*]] = cir.load %[[ALLOCA_2]] : !cir.ptr<!cir.vector<4 x !cir.float>>, !cir.vector<4 x !cir.float> 128  // CIR:           cir.return %[[LOAD_2]] : !cir.vector<4 x !cir.float> 129  // CIR:         } 130 131  // LLVM-LABEL: define dso_local <4 x float> @test_cmpnltps(132  // LLVM-SAME: <4 x float> [[TMP0:%.*]], <4 x float> [[TMP1:%.*]]) #[[ATTR0:[0-9]+]] {133  // LLVM-NEXT:    [[TMP3:%.*]] = alloca <4 x float>, i64 1, align 16134  // LLVM-NEXT:    [[TMP4:%.*]] = alloca <4 x float>, i64 1, align 16135  // LLVM-NEXT:    [[TMP5:%.*]] = alloca <4 x float>, i64 1, align 16136  // LLVM-NEXT:    store <4 x float> [[TMP0]], ptr [[TMP3]], align 16137  // LLVM-NEXT:    store <4 x float> [[TMP1]], ptr [[TMP4]], align 16138  // LLVM-NEXT:    [[TMP6:%.*]] = load <4 x float>, ptr [[TMP3]], align 16139  // LLVM-NEXT:    [[TMP7:%.*]] = load <4 x float>, ptr [[TMP4]], align 16140  // LLVM-NEXT:    [[TMP8:%.*]] = fcmp olt <4 x float> [[TMP6]], [[TMP7]]141  // LLVM-NEXT:    [[TMP9:%.*]] = sext <4 x i1> [[TMP8]] to <4 x i32>142  // LLVM-NEXT:    [[TMP10:%.*]] = xor <4 x i32> [[TMP9]], splat (i32 -1)143  // LLVM-NEXT:    [[TMP11:%.*]] = bitcast <4 x i32> [[TMP10]] to <4 x float>144  // LLVM-NEXT:    store <4 x float> [[TMP11]], ptr [[TMP5]], align 16145  // LLVM-NEXT:    [[TMP12:%.*]] = load <4 x float>, ptr [[TMP5]], align 16146  // LLVM-NEXT:    ret <4 x float> [[TMP12]]147 148  // OGCG-LABEL: define dso_local <4 x float> @test_cmpnltps(149  // OGCG-SAME: <4 x float> noundef [[A:%.*]], <4 x float> noundef [[B:%.*]]) #[[ATTR0:[0-9]+]] {150  // OGCG-NEXT:  [[ENTRY:.*:]]151  // OGCG-NEXT:    [[A_ADDR:%.*]] = alloca <4 x float>, align 16152  // OGCG-NEXT:    [[B_ADDR:%.*]] = alloca <4 x float>, align 16153  // OGCG-NEXT:    store <4 x float> [[A]], ptr [[A_ADDR]], align 16154  // OGCG-NEXT:    store <4 x float> [[B]], ptr [[B_ADDR]], align 16155  // OGCG-NEXT:    [[TMP0:%.*]] = load <4 x float>, ptr [[A_ADDR]], align 16156  // OGCG-NEXT:    [[TMP1:%.*]] = load <4 x float>, ptr [[B_ADDR]], align 16157  // OGCG-NEXT:    [[TMP2:%.*]] = fcmp uge <4 x float> [[TMP0]], [[TMP1]]158  // OGCG-NEXT:    [[TMP3:%.*]] = sext <4 x i1> [[TMP2]] to <4 x i32>159  // OGCG-NEXT:    [[TMP4:%.*]] = bitcast <4 x i32> [[TMP3]] to <4 x float>160  // OGCG-NEXT:    ret <4 x float> [[TMP4]]161  return __builtin_ia32_cmpnltps(A, B);162}163 164__m128d test_cmpnltpd(__m128d A, __m128d B) {165  // CIR-LABEL:   cir.func dso_local @test_cmpnltpd(166  // CIR:           %[[ARG0:.*]]: !cir.vector<2 x !cir.double> {{.*}}, %[[ARG1:.*]]: !cir.vector<2 x !cir.double> {{.*}}) -> !cir.vector<2 x !cir.double> inline(never) {167  // CIR:           %[[ALLOCA_0:.*]] = cir.alloca !cir.vector<2 x !cir.double>, !cir.ptr<!cir.vector<2 x !cir.double>>, ["A", init] {alignment = 16 : i64} 168  // CIR:           %[[ALLOCA_1:.*]] = cir.alloca !cir.vector<2 x !cir.double>, !cir.ptr<!cir.vector<2 x !cir.double>>, ["B", init] {alignment = 16 : i64} 169  // CIR:           %[[ALLOCA_2:.*]] = cir.alloca !cir.vector<2 x !cir.double>, !cir.ptr<!cir.vector<2 x !cir.double>>, ["__retval"] {alignment = 16 : i64} 170  // CIR:           cir.store %[[ARG0]], %[[ALLOCA_0]] : !cir.vector<2 x !cir.double>, !cir.ptr<!cir.vector<2 x !cir.double>> 171  // CIR:           cir.store %[[ARG1]], %[[ALLOCA_1]] : !cir.vector<2 x !cir.double>, !cir.ptr<!cir.vector<2 x !cir.double>> 172  // CIR:           %[[LOAD_0:.*]] = cir.load align(16) %[[ALLOCA_0]] : !cir.ptr<!cir.vector<2 x !cir.double>>, !cir.vector<2 x !cir.double> 173  // CIR:           %[[LOAD_1:.*]] = cir.load align(16) %[[ALLOCA_1]] : !cir.ptr<!cir.vector<2 x !cir.double>>, !cir.vector<2 x !cir.double> 174  // CIR:           %[[VEC_0:.*]] = cir.vec.cmp(lt, %[[LOAD_0]], %[[LOAD_1]]) : !cir.vector<2 x !cir.double>, !cir.vector<2 x !s64i> 175  // CIR:           %[[UNARY_0:.*]] = cir.unary(not, %[[VEC_0]]) : !cir.vector<2 x !s64i>, !cir.vector<2 x !s64i> 176  // CIR:           %[[CAST_0:.*]] = cir.cast bitcast %[[UNARY_0]] : !cir.vector<2 x !s64i> -> !cir.vector<2 x !cir.double> 177  // CIR:           cir.store %[[CAST_0]], %[[ALLOCA_2]] : !cir.vector<2 x !cir.double>, !cir.ptr<!cir.vector<2 x !cir.double>> 178  // CIR:           %[[LOAD_2:.*]] = cir.load %[[ALLOCA_2]] : !cir.ptr<!cir.vector<2 x !cir.double>>, !cir.vector<2 x !cir.double> 179  // CIR:           cir.return %[[LOAD_2]] : !cir.vector<2 x !cir.double> 180  // CIR:         } 181 182  // LLVM-LABEL: define dso_local <2 x double> @test_cmpnltpd(183  // LLVM-SAME: <2 x double> [[TMP0:%.*]], <2 x double> [[TMP1:%.*]]) #[[ATTR0:[0-9]+]] {184  // LLVM-NEXT:    [[TMP3:%.*]] = alloca <2 x double>, i64 1, align 16185  // LLVM-NEXT:    [[TMP4:%.*]] = alloca <2 x double>, i64 1, align 16186  // LLVM-NEXT:    [[TMP5:%.*]] = alloca <2 x double>, i64 1, align 16187  // LLVM-NEXT:    store <2 x double> [[TMP0]], ptr [[TMP3]], align 16188  // LLVM-NEXT:    store <2 x double> [[TMP1]], ptr [[TMP4]], align 16189  // LLVM-NEXT:    [[TMP6:%.*]] = load <2 x double>, ptr [[TMP3]], align 16190  // LLVM-NEXT:    [[TMP7:%.*]] = load <2 x double>, ptr [[TMP4]], align 16191  // LLVM-NEXT:    [[TMP8:%.*]] = fcmp olt <2 x double> [[TMP6]], [[TMP7]]192  // LLVM-NEXT:    [[TMP9:%.*]] = sext <2 x i1> [[TMP8]] to <2 x i64>193  // LLVM-NEXT:    [[TMP10:%.*]] = xor <2 x i64> [[TMP9]], splat (i64 -1)194  // LLVM-NEXT:    [[TMP11:%.*]] = bitcast <2 x i64> [[TMP10]] to <2 x double>195  // LLVM-NEXT:    store <2 x double> [[TMP11]], ptr [[TMP5]], align 16196  // LLVM-NEXT:    [[TMP12:%.*]] = load <2 x double>, ptr [[TMP5]], align 16197  // LLVM-NEXT:    ret <2 x double> [[TMP12]]198 199  // OGCG-LABEL: define dso_local <2 x double> @test_cmpnltpd(200  // OGCG-SAME: <2 x double> noundef [[A:%.*]], <2 x double> noundef [[B:%.*]]) #[[ATTR0:[0-9]+]] {201  // OGCG-NEXT:  [[ENTRY:.*:]]202  // OGCG-NEXT:    [[A_ADDR:%.*]] = alloca <2 x double>, align 16203  // OGCG-NEXT:    [[B_ADDR:%.*]] = alloca <2 x double>, align 16204  // OGCG-NEXT:    store <2 x double> [[A]], ptr [[A_ADDR]], align 16205  // OGCG-NEXT:    store <2 x double> [[B]], ptr [[B_ADDR]], align 16206  // OGCG-NEXT:    [[TMP0:%.*]] = load <2 x double>, ptr [[A_ADDR]], align 16207  // OGCG-NEXT:    [[TMP1:%.*]] = load <2 x double>, ptr [[B_ADDR]], align 16208  // OGCG-NEXT:    [[TMP2:%.*]] = fcmp uge <2 x double> [[TMP0]], [[TMP1]]209  // OGCG-NEXT:    [[TMP3:%.*]] = sext <2 x i1> [[TMP2]] to <2 x i64>210  // OGCG-NEXT:    [[TMP4:%.*]] = bitcast <2 x i64> [[TMP3]] to <2 x double>211  // OGCG-NEXT:    ret <2 x double> [[TMP4]]212  return  __builtin_ia32_cmpnltpd(A, B);213}214