174 lines · c
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py2// RUN: %clang_cc1 -triple aarch64 -target-feature +neon -target-feature +bf16 \3// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg,sroa | FileCheck %s4 5// REQUIRES: aarch64-registered-target || arm-registered-target6 7#include <arm_neon.h>8 9// CHECK-LABEL: @test_vcreate_bf16(10// CHECK-NEXT: entry:11// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A:%.*]] to <4 x bfloat>12// CHECK-NEXT: ret <4 x bfloat> [[TMP0]]13//14bfloat16x4_t test_vcreate_bf16(uint64_t a) {15 return vcreate_bf16(a);16}17 18// CHECK-LABEL: @test_vdup_n_bf16(19// CHECK-NEXT: entry:20// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x bfloat> poison, bfloat [[V:%.*]], i32 021// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x bfloat> [[VECINIT_I]], bfloat [[V]], i32 122// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x bfloat> [[VECINIT1_I]], bfloat [[V]], i32 223// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x bfloat> [[VECINIT2_I]], bfloat [[V]], i32 324// CHECK-NEXT: ret <4 x bfloat> [[VECINIT3_I]]25//26bfloat16x4_t test_vdup_n_bf16(bfloat16_t v) {27 return vdup_n_bf16(v);28}29 30// CHECK-LABEL: @test_vdupq_n_bf16(31// CHECK-NEXT: entry:32// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <8 x bfloat> poison, bfloat [[V:%.*]], i32 033// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <8 x bfloat> [[VECINIT_I]], bfloat [[V]], i32 134// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <8 x bfloat> [[VECINIT1_I]], bfloat [[V]], i32 235// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <8 x bfloat> [[VECINIT2_I]], bfloat [[V]], i32 336// CHECK-NEXT: [[VECINIT4_I:%.*]] = insertelement <8 x bfloat> [[VECINIT3_I]], bfloat [[V]], i32 437// CHECK-NEXT: [[VECINIT5_I:%.*]] = insertelement <8 x bfloat> [[VECINIT4_I]], bfloat [[V]], i32 538// CHECK-NEXT: [[VECINIT6_I:%.*]] = insertelement <8 x bfloat> [[VECINIT5_I]], bfloat [[V]], i32 639// CHECK-NEXT: [[VECINIT7_I:%.*]] = insertelement <8 x bfloat> [[VECINIT6_I]], bfloat [[V]], i32 740// CHECK-NEXT: ret <8 x bfloat> [[VECINIT7_I]]41//42bfloat16x8_t test_vdupq_n_bf16(bfloat16_t v) {43 return vdupq_n_bf16(v);44}45 46// CHECK-LABEL: @test_vdup_lane_bf16(47// CHECK-NEXT: entry:48// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x bfloat> [[V:%.*]] to <4 x i16>49// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[TMP0]] to <8 x i8>50// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x bfloat>51// CHECK-NEXT: [[LANE:%.*]] = shufflevector <4 x bfloat> [[TMP2]], <4 x bfloat> [[TMP2]], <4 x i32> <i32 1, i32 1, i32 1, i32 1>52// CHECK-NEXT: ret <4 x bfloat> [[LANE]]53//54bfloat16x4_t test_vdup_lane_bf16(bfloat16x4_t v) {55 return vdup_lane_bf16(v, 1);56}57 58// CHECK-LABEL: @test_vdupq_lane_bf16(59// CHECK-NEXT: entry:60// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x bfloat> [[V:%.*]] to <4 x i16>61// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[TMP0]] to <8 x i8>62// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x bfloat>63// CHECK-NEXT: [[LANE:%.*]] = shufflevector <4 x bfloat> [[TMP2]], <4 x bfloat> [[TMP2]], <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>64// CHECK-NEXT: ret <8 x bfloat> [[LANE]]65//66bfloat16x8_t test_vdupq_lane_bf16(bfloat16x4_t v) {67 return vdupq_lane_bf16(v, 1);68}69 70// CHECK-LABEL: @test_vdup_laneq_bf16(71// CHECK-NEXT: entry:72// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x bfloat> [[V:%.*]] to <8 x i16>73// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[TMP0]] to <16 x i8>74// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x bfloat>75// CHECK-NEXT: [[LANE:%.*]] = shufflevector <8 x bfloat> [[TMP2]], <8 x bfloat> [[TMP2]], <4 x i32> <i32 7, i32 7, i32 7, i32 7>76// CHECK-NEXT: ret <4 x bfloat> [[LANE]]77//78bfloat16x4_t test_vdup_laneq_bf16(bfloat16x8_t v) {79 return vdup_laneq_bf16(v, 7);80}81 82// CHECK-LABEL: @test_vdupq_laneq_bf16(83// CHECK-NEXT: entry:84// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x bfloat> [[V:%.*]] to <8 x i16>85// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[TMP0]] to <16 x i8>86// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x bfloat>87// CHECK-NEXT: [[LANE:%.*]] = shufflevector <8 x bfloat> [[TMP2]], <8 x bfloat> [[TMP2]], <8 x i32> <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7>88// CHECK-NEXT: ret <8 x bfloat> [[LANE]]89//90bfloat16x8_t test_vdupq_laneq_bf16(bfloat16x8_t v) {91 return vdupq_laneq_bf16(v, 7);92}93 94// CHECK-LABEL: @test_vcombine_bf16(95// CHECK-NEXT: entry:96// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x bfloat> [[LOW:%.*]], <4 x bfloat> [[HIGH:%.*]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>97// CHECK-NEXT: ret <8 x bfloat> [[SHUFFLE_I]]98//99bfloat16x8_t test_vcombine_bf16(bfloat16x4_t low, bfloat16x4_t high) {100 return vcombine_bf16(low, high);101}102 103// CHECK-LABEL: @test_vget_high_bf16(104// CHECK-NEXT: entry:105// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x bfloat> [[A:%.*]], <8 x bfloat> [[A]], <4 x i32> <i32 4, i32 5, i32 6, i32 7>106// CHECK-NEXT: ret <4 x bfloat> [[SHUFFLE_I]]107//108bfloat16x4_t test_vget_high_bf16(bfloat16x8_t a) {109 return vget_high_bf16(a);110}111 112// CHECK-LABEL: @test_vget_low_bf16(113// CHECK-NEXT: entry:114// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x bfloat> [[A:%.*]], <8 x bfloat> [[A]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>115// CHECK-NEXT: ret <4 x bfloat> [[SHUFFLE_I]]116//117bfloat16x4_t test_vget_low_bf16(bfloat16x8_t a) {118 return vget_low_bf16(a);119}120 121// CHECK-LABEL: @test_vget_lane_bf16(122// CHECK-NEXT: entry:123// CHECK-NEXT: [[VGET_LANE:%.*]] = extractelement <4 x bfloat> [[V:%.*]], i32 1124// CHECK-NEXT: ret bfloat [[VGET_LANE]]125//126bfloat16_t test_vget_lane_bf16(bfloat16x4_t v) {127 return vget_lane_bf16(v, 1);128}129 130// CHECK-LABEL: @test_vgetq_lane_bf16(131// CHECK-NEXT: entry:132// CHECK-NEXT: [[VGETQ_LANE:%.*]] = extractelement <8 x bfloat> [[V:%.*]], i32 7133// CHECK-NEXT: ret bfloat [[VGETQ_LANE]]134//135bfloat16_t test_vgetq_lane_bf16(bfloat16x8_t v) {136 return vgetq_lane_bf16(v, 7);137}138 139// CHECK-LABEL: @test_vset_lane_bf16(140// CHECK-NEXT: entry:141// CHECK-NEXT: [[VSET_LANE:%.*]] = insertelement <4 x bfloat> [[V:%.*]], bfloat [[A:%.*]], i32 1142// CHECK-NEXT: ret <4 x bfloat> [[VSET_LANE]]143//144bfloat16x4_t test_vset_lane_bf16(bfloat16_t a, bfloat16x4_t v) {145 return vset_lane_bf16(a, v, 1);146}147 148// CHECK-LABEL: @test_vsetq_lane_bf16(149// CHECK-NEXT: entry:150// CHECK-NEXT: [[VSET_LANE:%.*]] = insertelement <8 x bfloat> [[V:%.*]], bfloat [[A:%.*]], i32 7151// CHECK-NEXT: ret <8 x bfloat> [[VSET_LANE]]152//153bfloat16x8_t test_vsetq_lane_bf16(bfloat16_t a, bfloat16x8_t v) {154 return vsetq_lane_bf16(a, v, 7);155}156 157// CHECK-LABEL: @test_vduph_lane_bf16(158// CHECK-NEXT: entry:159// CHECK-NEXT: [[VGET_LANE:%.*]] = extractelement <4 x bfloat> [[V:%.*]], i32 1160// CHECK-NEXT: ret bfloat [[VGET_LANE]]161//162bfloat16_t test_vduph_lane_bf16(bfloat16x4_t v) {163 return vduph_lane_bf16(v, 1);164}165 166// CHECK-LABEL: @test_vduph_laneq_bf16(167// CHECK-NEXT: entry:168// CHECK-NEXT: [[VGETQ_LANE:%.*]] = extractelement <8 x bfloat> [[V:%.*]], i32 7169// CHECK-NEXT: ret bfloat [[VGETQ_LANE]]170//171bfloat16_t test_vduph_laneq_bf16(bfloat16x8_t v) {172 return vduph_laneq_bf16(v, 7);173}174