817 lines · c
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --check-attributes --check-globals --include-generated-funcs --global-value-regex ".*"2 3// Test all of the AArch64 feature detection bitmasks in the resolver.4// Use -target-feature +fp-armv8 on the command line to show that features5// specified on cmd are not exempt from runtime detection.6 7// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -emit-llvm -o - %s | FileCheck %s8// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +fp-armv8 -emit-llvm -o - %s | FileCheck %s9 10__attribute__((target_clones("aes", "bf16"))) int fmv(void) { return 0; }11 12__attribute__((target_version("bti"))) int fmv(void) { return 0; }13 14__attribute__((target_version("crc"))) int fmv(void) { return 0; }15 16__attribute__((target_version("cssc"))) int fmv(void) { return 0; }17 18__attribute__((target_version("dit"))) int fmv(void) { return 0; }19 20__attribute__((target_version("dotprod"))) int fmv(void) { return 0; }21 22__attribute__((target_version("dpb"))) int fmv(void) { return 0; }23 24__attribute__((target_version("dpb2"))) int fmv(void) { return 0; }25 26__attribute__((target_version("f32mm"))) int fmv(void) { return 0; }27 28__attribute__((target_version("f64mm"))) int fmv(void) { return 0; }29 30__attribute__((target_version("fcma"))) int fmv(void) { return 0; }31 32__attribute__((target_version("flagm"))) int fmv(void) { return 0; }33 34__attribute__((target_version("flagm2"))) int fmv(void) { return 0; }35 36__attribute__((target_version("fp"))) int fmv(void) { return 0; }37 38__attribute__((target_version("fp16"))) int fmv(void) { return 0; }39 40__attribute__((target_version("fp16fml"))) int fmv(void) { return 0; }41 42__attribute__((target_version("frintts"))) int fmv(void) { return 0; }43 44__attribute__((target_version("i8mm"))) int fmv(void) { return 0; }45 46__attribute__((target_version("jscvt"))) int fmv(void) { return 0; }47 48__attribute__((target_version("lse"))) int fmv(void) { return 0; }49 50__attribute__((target_version("memtag"))) int fmv(void) { return 0; }51 52__attribute__((target_version("mops"))) int fmv(void) { return 0; }53 54__attribute__((target_version("rcpc"))) int fmv(void) { return 0; }55 56__attribute__((target_version("rcpc2"))) int fmv(void) { return 0; }57 58__attribute__((target_version("rcpc3"))) int fmv(void) { return 0; }59 60__attribute__((target_version("rdm"))) int fmv(void) { return 0; }61 62__attribute__((target_version("rng"))) int fmv(void) { return 0; }63 64__attribute__((target_version("sb"))) int fmv(void) { return 0; }65 66__attribute__((target_version("sha2"))) int fmv(void) { return 0; }67 68__attribute__((target_version("sha3"))) int fmv(void) { return 0; }69 70__attribute__((target_version("simd"))) int fmv(void) { return 0; }71 72__attribute__((target_version("sm4"))) int fmv(void) { return 0; }73 74__attribute__((target_version("sme"))) int fmv(void) { return 0; }75 76__attribute__((target_version("sme-f64f64"))) int fmv(void) { return 0; }77 78__attribute__((target_version("sme-i16i64"))) int fmv(void) { return 0; }79 80__attribute__((target_version("sme2"))) int fmv(void) { return 0; }81 82__attribute__((target_version("ssbs"))) int fmv(void) { return 0; }83 84__attribute__((target_version("sve"))) int fmv(void) { return 0; }85 86__attribute__((target_version("sve2"))) int fmv(void) { return 0; }87 88__attribute__((target_version("sve2-aes"))) int fmv(void) { return 0; }89 90__attribute__((target_version("sve2-bitperm"))) int fmv(void) { return 0; }91 92__attribute__((target_version("sve2-sha3"))) int fmv(void) { return 0; }93 94__attribute__((target_version("sve2-sm4"))) int fmv(void) { return 0; }95 96__attribute__((target_version("wfxt"))) int fmv(void) { return 0; }97 98__attribute__((target_version("cssc+fp"))) int fmv(void);99 100__attribute__((target_version("default"))) int fmv(void) { return 0; }101 102int caller() {103 return fmv();104}105 106//.107// CHECK: @__aarch64_cpu_features = external dso_local global { i64 }108// CHECK: @fmv = weak_odr ifunc i32 (), ptr @fmv.resolver109//.110// CHECK: Function Attrs: noinline nounwind optnone111// CHECK-LABEL: define {{[^@]+}}@fmv._Maes112// CHECK-SAME: () #[[ATTR0:[0-9]+]] {113// CHECK-NEXT: entry:114// CHECK-NEXT: ret i32 0115//116//117// CHECK: Function Attrs: noinline nounwind optnone118// CHECK-LABEL: define {{[^@]+}}@fmv._Mbf16119// CHECK-SAME: () #[[ATTR1:[0-9]+]] {120// CHECK-NEXT: entry:121// CHECK-NEXT: ret i32 0122//123//124// CHECK: Function Attrs: noinline nounwind optnone125// CHECK-LABEL: define {{[^@]+}}@fmv._Mbti126// CHECK-SAME: () #[[ATTR2:[0-9]+]] {127// CHECK-NEXT: entry:128// CHECK-NEXT: ret i32 0129//130//131// CHECK: Function Attrs: noinline nounwind optnone132// CHECK-LABEL: define {{[^@]+}}@fmv._Mcrc133// CHECK-SAME: () #[[ATTR3:[0-9]+]] {134// CHECK-NEXT: entry:135// CHECK-NEXT: ret i32 0136//137//138// CHECK: Function Attrs: noinline nounwind optnone139// CHECK-LABEL: define {{[^@]+}}@fmv._Mcssc140// CHECK-SAME: () #[[ATTR4:[0-9]+]] {141// CHECK-NEXT: entry:142// CHECK-NEXT: ret i32 0143//144//145// CHECK: Function Attrs: noinline nounwind optnone146// CHECK-LABEL: define {{[^@]+}}@fmv._Mdit147// CHECK-SAME: () #[[ATTR5:[0-9]+]] {148// CHECK-NEXT: entry:149// CHECK-NEXT: ret i32 0150//151//152// CHECK: Function Attrs: noinline nounwind optnone153// CHECK-LABEL: define {{[^@]+}}@fmv._Mdotprod154// CHECK-SAME: () #[[ATTR6:[0-9]+]] {155// CHECK-NEXT: entry:156// CHECK-NEXT: ret i32 0157//158//159// CHECK: Function Attrs: noinline nounwind optnone160// CHECK-LABEL: define {{[^@]+}}@fmv._Mdpb161// CHECK-SAME: () #[[ATTR7:[0-9]+]] {162// CHECK-NEXT: entry:163// CHECK-NEXT: ret i32 0164//165//166// CHECK: Function Attrs: noinline nounwind optnone167// CHECK-LABEL: define {{[^@]+}}@fmv._Mdpb2168// CHECK-SAME: () #[[ATTR8:[0-9]+]] {169// CHECK-NEXT: entry:170// CHECK-NEXT: ret i32 0171//172//173// CHECK: Function Attrs: noinline nounwind optnone vscale_range(1,16)174// CHECK-LABEL: define {{[^@]+}}@fmv._Mf32mm175// CHECK-SAME: () #[[ATTR9:[0-9]+]] {176// CHECK-NEXT: entry:177// CHECK-NEXT: ret i32 0178//179//180// CHECK: Function Attrs: noinline nounwind optnone vscale_range(1,16)181// CHECK-LABEL: define {{[^@]+}}@fmv._Mf64mm182// CHECK-SAME: () #[[ATTR10:[0-9]+]] {183// CHECK-NEXT: entry:184// CHECK-NEXT: ret i32 0185//186//187// CHECK: Function Attrs: noinline nounwind optnone188// CHECK-LABEL: define {{[^@]+}}@fmv._Mfcma189// CHECK-SAME: () #[[ATTR11:[0-9]+]] {190// CHECK-NEXT: entry:191// CHECK-NEXT: ret i32 0192//193//194// CHECK: Function Attrs: noinline nounwind optnone195// CHECK-LABEL: define {{[^@]+}}@fmv._Mflagm196// CHECK-SAME: () #[[ATTR12:[0-9]+]] {197// CHECK-NEXT: entry:198// CHECK-NEXT: ret i32 0199//200//201// CHECK: Function Attrs: noinline nounwind optnone202// CHECK-LABEL: define {{[^@]+}}@fmv._Mflagm2203// CHECK-SAME: () #[[ATTR13:[0-9]+]] {204// CHECK-NEXT: entry:205// CHECK-NEXT: ret i32 0206//207//208// CHECK: Function Attrs: noinline nounwind optnone209// CHECK-LABEL: define {{[^@]+}}@fmv._Mfp210// CHECK-SAME: () #[[ATTR14:[0-9]+]] {211// CHECK-NEXT: entry:212// CHECK-NEXT: ret i32 0213//214//215// CHECK: Function Attrs: noinline nounwind optnone216// CHECK-LABEL: define {{[^@]+}}@fmv._Mfp16217// CHECK-SAME: () #[[ATTR15:[0-9]+]] {218// CHECK-NEXT: entry:219// CHECK-NEXT: ret i32 0220//221//222// CHECK: Function Attrs: noinline nounwind optnone223// CHECK-LABEL: define {{[^@]+}}@fmv._Mfp16fml224// CHECK-SAME: () #[[ATTR16:[0-9]+]] {225// CHECK-NEXT: entry:226// CHECK-NEXT: ret i32 0227//228//229// CHECK: Function Attrs: noinline nounwind optnone230// CHECK-LABEL: define {{[^@]+}}@fmv._Mfrintts231// CHECK-SAME: () #[[ATTR17:[0-9]+]] {232// CHECK-NEXT: entry:233// CHECK-NEXT: ret i32 0234//235//236// CHECK: Function Attrs: noinline nounwind optnone237// CHECK-LABEL: define {{[^@]+}}@fmv._Mi8mm238// CHECK-SAME: () #[[ATTR18:[0-9]+]] {239// CHECK-NEXT: entry:240// CHECK-NEXT: ret i32 0241//242//243// CHECK: Function Attrs: noinline nounwind optnone244// CHECK-LABEL: define {{[^@]+}}@fmv._Mjscvt245// CHECK-SAME: () #[[ATTR19:[0-9]+]] {246// CHECK-NEXT: entry:247// CHECK-NEXT: ret i32 0248//249//250// CHECK: Function Attrs: noinline nounwind optnone251// CHECK-LABEL: define {{[^@]+}}@fmv._Mlse252// CHECK-SAME: () #[[ATTR20:[0-9]+]] {253// CHECK-NEXT: entry:254// CHECK-NEXT: ret i32 0255//256//257// CHECK: Function Attrs: noinline nounwind optnone258// CHECK-LABEL: define {{[^@]+}}@fmv._Mmemtag259// CHECK-SAME: () #[[ATTR21:[0-9]+]] {260// CHECK-NEXT: entry:261// CHECK-NEXT: ret i32 0262//263//264// CHECK: Function Attrs: noinline nounwind optnone265// CHECK-LABEL: define {{[^@]+}}@fmv._Mmops266// CHECK-SAME: () #[[ATTR22:[0-9]+]] {267// CHECK-NEXT: entry:268// CHECK-NEXT: ret i32 0269//270//271// CHECK: Function Attrs: noinline nounwind optnone272// CHECK-LABEL: define {{[^@]+}}@fmv._Mrcpc273// CHECK-SAME: () #[[ATTR23:[0-9]+]] {274// CHECK-NEXT: entry:275// CHECK-NEXT: ret i32 0276//277//278// CHECK: Function Attrs: noinline nounwind optnone279// CHECK-LABEL: define {{[^@]+}}@fmv._Mrcpc2280// CHECK-SAME: () #[[ATTR24:[0-9]+]] {281// CHECK-NEXT: entry:282// CHECK-NEXT: ret i32 0283//284//285// CHECK: Function Attrs: noinline nounwind optnone286// CHECK-LABEL: define {{[^@]+}}@fmv._Mrcpc3287// CHECK-SAME: () #[[ATTR25:[0-9]+]] {288// CHECK-NEXT: entry:289// CHECK-NEXT: ret i32 0290//291//292// CHECK: Function Attrs: noinline nounwind optnone293// CHECK-LABEL: define {{[^@]+}}@fmv._Mrdm294// CHECK-SAME: () #[[ATTR26:[0-9]+]] {295// CHECK-NEXT: entry:296// CHECK-NEXT: ret i32 0297//298//299// CHECK: Function Attrs: noinline nounwind optnone300// CHECK-LABEL: define {{[^@]+}}@fmv._Mrng301// CHECK-SAME: () #[[ATTR27:[0-9]+]] {302// CHECK-NEXT: entry:303// CHECK-NEXT: ret i32 0304//305//306// CHECK: Function Attrs: noinline nounwind optnone307// CHECK-LABEL: define {{[^@]+}}@fmv._Msb308// CHECK-SAME: () #[[ATTR28:[0-9]+]] {309// CHECK-NEXT: entry:310// CHECK-NEXT: ret i32 0311//312//313// CHECK: Function Attrs: noinline nounwind optnone314// CHECK-LABEL: define {{[^@]+}}@fmv._Msha2315// CHECK-SAME: () #[[ATTR29:[0-9]+]] {316// CHECK-NEXT: entry:317// CHECK-NEXT: ret i32 0318//319//320// CHECK: Function Attrs: noinline nounwind optnone321// CHECK-LABEL: define {{[^@]+}}@fmv._Msha3322// CHECK-SAME: () #[[ATTR30:[0-9]+]] {323// CHECK-NEXT: entry:324// CHECK-NEXT: ret i32 0325//326//327// CHECK: Function Attrs: noinline nounwind optnone328// CHECK-LABEL: define {{[^@]+}}@fmv._Msimd329// CHECK-SAME: () #[[ATTR31:[0-9]+]] {330// CHECK-NEXT: entry:331// CHECK-NEXT: ret i32 0332//333//334// CHECK: Function Attrs: noinline nounwind optnone335// CHECK-LABEL: define {{[^@]+}}@fmv._Msm4336// CHECK-SAME: () #[[ATTR32:[0-9]+]] {337// CHECK-NEXT: entry:338// CHECK-NEXT: ret i32 0339//340//341// CHECK: Function Attrs: noinline nounwind optnone342// CHECK-LABEL: define {{[^@]+}}@fmv._Msme343// CHECK-SAME: () #[[ATTR33:[0-9]+]] {344// CHECK-NEXT: entry:345// CHECK-NEXT: ret i32 0346//347//348// CHECK: Function Attrs: noinline nounwind optnone349// CHECK-LABEL: define {{[^@]+}}@fmv._Msme-f64f64350// CHECK-SAME: () #[[ATTR34:[0-9]+]] {351// CHECK-NEXT: entry:352// CHECK-NEXT: ret i32 0353//354//355// CHECK: Function Attrs: noinline nounwind optnone356// CHECK-LABEL: define {{[^@]+}}@fmv._Msme-i16i64357// CHECK-SAME: () #[[ATTR35:[0-9]+]] {358// CHECK-NEXT: entry:359// CHECK-NEXT: ret i32 0360//361//362// CHECK: Function Attrs: noinline nounwind optnone363// CHECK-LABEL: define {{[^@]+}}@fmv._Msme2364// CHECK-SAME: () #[[ATTR36:[0-9]+]] {365// CHECK-NEXT: entry:366// CHECK-NEXT: ret i32 0367//368//369// CHECK: Function Attrs: noinline nounwind optnone370// CHECK-LABEL: define {{[^@]+}}@fmv._Mssbs371// CHECK-SAME: () #[[ATTR37:[0-9]+]] {372// CHECK-NEXT: entry:373// CHECK-NEXT: ret i32 0374//375//376// CHECK: Function Attrs: noinline nounwind optnone vscale_range(1,16)377// CHECK-LABEL: define {{[^@]+}}@fmv._Msve378// CHECK-SAME: () #[[ATTR38:[0-9]+]] {379// CHECK-NEXT: entry:380// CHECK-NEXT: ret i32 0381//382//383// CHECK: Function Attrs: noinline nounwind optnone vscale_range(1,16)384// CHECK-LABEL: define {{[^@]+}}@fmv._Msve2385// CHECK-SAME: () #[[ATTR39:[0-9]+]] {386// CHECK-NEXT: entry:387// CHECK-NEXT: ret i32 0388//389//390// CHECK: Function Attrs: noinline nounwind optnone vscale_range(1,16)391// CHECK-LABEL: define {{[^@]+}}@fmv._Msve2-aes392// CHECK-SAME: () #[[ATTR40:[0-9]+]] {393// CHECK-NEXT: entry:394// CHECK-NEXT: ret i32 0395//396//397// CHECK: Function Attrs: noinline nounwind optnone vscale_range(1,16)398// CHECK-LABEL: define {{[^@]+}}@fmv._Msve2-bitperm399// CHECK-SAME: () #[[ATTR41:[0-9]+]] {400// CHECK-NEXT: entry:401// CHECK-NEXT: ret i32 0402//403//404// CHECK: Function Attrs: noinline nounwind optnone vscale_range(1,16)405// CHECK-LABEL: define {{[^@]+}}@fmv._Msve2-sha3406// CHECK-SAME: () #[[ATTR42:[0-9]+]] {407// CHECK-NEXT: entry:408// CHECK-NEXT: ret i32 0409//410//411// CHECK: Function Attrs: noinline nounwind optnone vscale_range(1,16)412// CHECK-LABEL: define {{[^@]+}}@fmv._Msve2-sm4413// CHECK-SAME: () #[[ATTR43:[0-9]+]] {414// CHECK-NEXT: entry:415// CHECK-NEXT: ret i32 0416//417//418// CHECK: Function Attrs: noinline nounwind optnone419// CHECK-LABEL: define {{[^@]+}}@fmv._Mwfxt420// CHECK-SAME: () #[[ATTR44:[0-9]+]] {421// CHECK-NEXT: entry:422// CHECK-NEXT: ret i32 0423//424//425// CHECK: Function Attrs: noinline nounwind optnone426// CHECK-LABEL: define {{[^@]+}}@fmv.default427// CHECK-SAME: () #[[ATTR45:[0-9]+]] {428// CHECK-NEXT: entry:429// CHECK-NEXT: ret i32 0430//431//432// CHECK: Function Attrs: noinline nounwind optnone433// CHECK-LABEL: define {{[^@]+}}@caller434// CHECK-SAME: () #[[ATTR46:[0-9]+]] {435// CHECK-NEXT: entry:436// CHECK-NEXT: [[CALL:%.*]] = call i32 @fmv()437// CHECK-NEXT: ret i32 [[CALL]]438//439//440// CHECK-LABEL: define {{[^@]+}}@fmv.resolver() {{[#0-9]* }}comdat {441// CHECK-NEXT: resolver_entry:442// CHECK-NEXT: call void @__init_cpu_features_resolver()443// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8444// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 2304445// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 2304446// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]447// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]448// CHECK: resolver_return:449// CHECK-NEXT: ret ptr @fmv._McsscMfp450// CHECK: resolver_else:451// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8452// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 2048453// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 2048454// CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]]455// CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]456// CHECK: resolver_return1:457// CHECK-NEXT: ret ptr @fmv._Mcssc458// CHECK: resolver_else2:459// CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8460// CHECK-NEXT: [[TMP9:%.*]] = and i64 [[TMP8]], 576460752303423488461// CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP9]], 576460752303423488462// CHECK-NEXT: [[TMP11:%.*]] = and i1 true, [[TMP10]]463// CHECK-NEXT: br i1 [[TMP11]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]]464// CHECK: resolver_return3:465// CHECK-NEXT: ret ptr @fmv._Mmops466// CHECK: resolver_else4:467// CHECK-NEXT: [[TMP12:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8468// CHECK-NEXT: [[TMP13:%.*]] = and i64 [[TMP12]], 144119586256651008469// CHECK-NEXT: [[TMP14:%.*]] = icmp eq i64 [[TMP13]], 144119586256651008470// CHECK-NEXT: [[TMP15:%.*]] = and i1 true, [[TMP14]]471// CHECK-NEXT: br i1 [[TMP15]], label [[RESOLVER_RETURN5:%.*]], label [[RESOLVER_ELSE6:%.*]]472// CHECK: resolver_return5:473// CHECK-NEXT: ret ptr @fmv._Msme2474// CHECK: resolver_else6:475// CHECK-NEXT: [[TMP16:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8476// CHECK-NEXT: [[TMP17:%.*]] = and i64 [[TMP16]], 72061992218723072477// CHECK-NEXT: [[TMP18:%.*]] = icmp eq i64 [[TMP17]], 72061992218723072478// CHECK-NEXT: [[TMP19:%.*]] = and i1 true, [[TMP18]]479// CHECK-NEXT: br i1 [[TMP19]], label [[RESOLVER_RETURN7:%.*]], label [[RESOLVER_ELSE8:%.*]]480// CHECK: resolver_return7:481// CHECK-NEXT: ret ptr @fmv._Msme-i16i64482// CHECK: resolver_else8:483// CHECK-NEXT: [[TMP20:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8484// CHECK-NEXT: [[TMP21:%.*]] = and i64 [[TMP20]], 36033195199759104485// CHECK-NEXT: [[TMP22:%.*]] = icmp eq i64 [[TMP21]], 36033195199759104486// CHECK-NEXT: [[TMP23:%.*]] = and i1 true, [[TMP22]]487// CHECK-NEXT: br i1 [[TMP23]], label [[RESOLVER_RETURN9:%.*]], label [[RESOLVER_ELSE10:%.*]]488// CHECK: resolver_return9:489// CHECK-NEXT: ret ptr @fmv._Msme-f64f64490// CHECK: resolver_else10:491// CHECK-NEXT: [[TMP24:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8492// CHECK-NEXT: [[TMP25:%.*]] = and i64 [[TMP24]], 18014398509481984493// CHECK-NEXT: [[TMP26:%.*]] = icmp eq i64 [[TMP25]], 18014398509481984494// CHECK-NEXT: [[TMP27:%.*]] = and i1 true, [[TMP26]]495// CHECK-NEXT: br i1 [[TMP27]], label [[RESOLVER_RETURN11:%.*]], label [[RESOLVER_ELSE12:%.*]]496// CHECK: resolver_return11:497// CHECK-NEXT: ret ptr @fmv._Mwfxt498// CHECK: resolver_else12:499// CHECK-NEXT: [[TMP28:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8500// CHECK-NEXT: [[TMP29:%.*]] = and i64 [[TMP28]], 1125899906842624501// CHECK-NEXT: [[TMP30:%.*]] = icmp eq i64 [[TMP29]], 1125899906842624502// CHECK-NEXT: [[TMP31:%.*]] = and i1 true, [[TMP30]]503// CHECK-NEXT: br i1 [[TMP31]], label [[RESOLVER_RETURN13:%.*]], label [[RESOLVER_ELSE14:%.*]]504// CHECK: resolver_return13:505// CHECK-NEXT: ret ptr @fmv._Mbti506// CHECK: resolver_else14:507// CHECK-NEXT: [[TMP32:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8508// CHECK-NEXT: [[TMP33:%.*]] = and i64 [[TMP32]], 562949953421312509// CHECK-NEXT: [[TMP34:%.*]] = icmp eq i64 [[TMP33]], 562949953421312510// CHECK-NEXT: [[TMP35:%.*]] = and i1 true, [[TMP34]]511// CHECK-NEXT: br i1 [[TMP35]], label [[RESOLVER_RETURN15:%.*]], label [[RESOLVER_ELSE16:%.*]]512// CHECK: resolver_return15:513// CHECK-NEXT: ret ptr @fmv._Mssbs514// CHECK: resolver_else16:515// CHECK-NEXT: [[TMP36:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8516// CHECK-NEXT: [[TMP37:%.*]] = and i64 [[TMP36]], 70368744177664517// CHECK-NEXT: [[TMP38:%.*]] = icmp eq i64 [[TMP37]], 70368744177664518// CHECK-NEXT: [[TMP39:%.*]] = and i1 true, [[TMP38]]519// CHECK-NEXT: br i1 [[TMP39]], label [[RESOLVER_RETURN17:%.*]], label [[RESOLVER_ELSE18:%.*]]520// CHECK: resolver_return17:521// CHECK-NEXT: ret ptr @fmv._Msb522// CHECK: resolver_else18:523// CHECK-NEXT: [[TMP40:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8524// CHECK-NEXT: [[TMP41:%.*]] = and i64 [[TMP40]], 17592186044416525// CHECK-NEXT: [[TMP42:%.*]] = icmp eq i64 [[TMP41]], 17592186044416526// CHECK-NEXT: [[TMP43:%.*]] = and i1 true, [[TMP42]]527// CHECK-NEXT: br i1 [[TMP43]], label [[RESOLVER_RETURN19:%.*]], label [[RESOLVER_ELSE20:%.*]]528// CHECK: resolver_return19:529// CHECK-NEXT: ret ptr @fmv._Mmemtag530// CHECK: resolver_else20:531// CHECK-NEXT: [[TMP44:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8532// CHECK-NEXT: [[TMP45:%.*]] = and i64 [[TMP44]], 4398180795136533// CHECK-NEXT: [[TMP46:%.*]] = icmp eq i64 [[TMP45]], 4398180795136534// CHECK-NEXT: [[TMP47:%.*]] = and i1 true, [[TMP46]]535// CHECK-NEXT: br i1 [[TMP47]], label [[RESOLVER_RETURN21:%.*]], label [[RESOLVER_ELSE22:%.*]]536// CHECK: resolver_return21:537// CHECK-NEXT: ret ptr @fmv._Msme538// CHECK: resolver_else22:539// CHECK-NEXT: [[TMP48:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8540// CHECK-NEXT: [[TMP49:%.*]] = and i64 [[TMP48]], 2268816540448541// CHECK-NEXT: [[TMP50:%.*]] = icmp eq i64 [[TMP49]], 2268816540448542// CHECK-NEXT: [[TMP51:%.*]] = and i1 true, [[TMP50]]543// CHECK-NEXT: br i1 [[TMP51]], label [[RESOLVER_RETURN23:%.*]], label [[RESOLVER_ELSE24:%.*]]544// CHECK: resolver_return23:545// CHECK-NEXT: ret ptr @fmv._Msve2-sm4546// CHECK: resolver_else24:547// CHECK-NEXT: [[TMP52:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8548// CHECK-NEXT: [[TMP53:%.*]] = and i64 [[TMP52]], 1169304924928549// CHECK-NEXT: [[TMP54:%.*]] = icmp eq i64 [[TMP53]], 1169304924928550// CHECK-NEXT: [[TMP55:%.*]] = and i1 true, [[TMP54]]551// CHECK-NEXT: br i1 [[TMP55]], label [[RESOLVER_RETURN25:%.*]], label [[RESOLVER_ELSE26:%.*]]552// CHECK: resolver_return25:553// CHECK-NEXT: ret ptr @fmv._Msve2-sha3554// CHECK: resolver_else26:555// CHECK-NEXT: [[TMP56:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8556// CHECK-NEXT: [[TMP57:%.*]] = and i64 [[TMP56]], 619549098240557// CHECK-NEXT: [[TMP58:%.*]] = icmp eq i64 [[TMP57]], 619549098240558// CHECK-NEXT: [[TMP59:%.*]] = and i1 true, [[TMP58]]559// CHECK-NEXT: br i1 [[TMP59]], label [[RESOLVER_RETURN27:%.*]], label [[RESOLVER_ELSE28:%.*]]560// CHECK: resolver_return27:561// CHECK-NEXT: ret ptr @fmv._Msve2-bitperm562// CHECK: resolver_else28:563// CHECK-NEXT: [[TMP60:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8564// CHECK-NEXT: [[TMP61:%.*]] = and i64 [[TMP60]], 344671224576565// CHECK-NEXT: [[TMP62:%.*]] = icmp eq i64 [[TMP61]], 344671224576566// CHECK-NEXT: [[TMP63:%.*]] = and i1 true, [[TMP62]]567// CHECK-NEXT: br i1 [[TMP63]], label [[RESOLVER_RETURN29:%.*]], label [[RESOLVER_ELSE30:%.*]]568// CHECK: resolver_return29:569// CHECK-NEXT: ret ptr @fmv._Msve2-aes570// CHECK: resolver_else30:571// CHECK-NEXT: [[TMP64:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8572// CHECK-NEXT: [[TMP65:%.*]] = and i64 [[TMP64]], 69793284352573// CHECK-NEXT: [[TMP66:%.*]] = icmp eq i64 [[TMP65]], 69793284352574// CHECK-NEXT: [[TMP67:%.*]] = and i1 true, [[TMP66]]575// CHECK-NEXT: br i1 [[TMP67]], label [[RESOLVER_RETURN31:%.*]], label [[RESOLVER_ELSE32:%.*]]576// CHECK: resolver_return31:577// CHECK-NEXT: ret ptr @fmv._Msve2578// CHECK: resolver_else32:579// CHECK-NEXT: [[TMP68:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8580// CHECK-NEXT: [[TMP69:%.*]] = and i64 [[TMP68]], 35433545984581// CHECK-NEXT: [[TMP70:%.*]] = icmp eq i64 [[TMP69]], 35433545984582// CHECK-NEXT: [[TMP71:%.*]] = and i1 true, [[TMP70]]583// CHECK-NEXT: br i1 [[TMP71]], label [[RESOLVER_RETURN33:%.*]], label [[RESOLVER_ELSE34:%.*]]584// CHECK: resolver_return33:585// CHECK-NEXT: ret ptr @fmv._Mf64mm586// CHECK: resolver_else34:587// CHECK-NEXT: [[TMP72:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8588// CHECK-NEXT: [[TMP73:%.*]] = and i64 [[TMP72]], 18253676800589// CHECK-NEXT: [[TMP74:%.*]] = icmp eq i64 [[TMP73]], 18253676800590// CHECK-NEXT: [[TMP75:%.*]] = and i1 true, [[TMP74]]591// CHECK-NEXT: br i1 [[TMP75]], label [[RESOLVER_RETURN35:%.*]], label [[RESOLVER_ELSE36:%.*]]592// CHECK: resolver_return35:593// CHECK-NEXT: ret ptr @fmv._Mf32mm594// CHECK: resolver_else36:595// CHECK-NEXT: [[TMP76:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8596// CHECK-NEXT: [[TMP77:%.*]] = and i64 [[TMP76]], 1073807616597// CHECK-NEXT: [[TMP78:%.*]] = icmp eq i64 [[TMP77]], 1073807616598// CHECK-NEXT: [[TMP79:%.*]] = and i1 true, [[TMP78]]599// CHECK-NEXT: br i1 [[TMP79]], label [[RESOLVER_RETURN37:%.*]], label [[RESOLVER_ELSE38:%.*]]600// CHECK: resolver_return37:601// CHECK-NEXT: ret ptr @fmv._Msve602// CHECK: resolver_else38:603// CHECK-NEXT: [[TMP80:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8604// CHECK-NEXT: [[TMP81:%.*]] = and i64 [[TMP80]], 134218496605// CHECK-NEXT: [[TMP82:%.*]] = icmp eq i64 [[TMP81]], 134218496606// CHECK-NEXT: [[TMP83:%.*]] = and i1 true, [[TMP82]]607// CHECK-NEXT: br i1 [[TMP83]], label [[RESOLVER_RETURN39:%.*]], label [[RESOLVER_ELSE40:%.*]]608// CHECK: resolver_return39:609// CHECK-NEXT: ret ptr @fmv._Mbf16610// CHECK: resolver_else40:611// CHECK-NEXT: [[TMP84:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8612// CHECK-NEXT: [[TMP85:%.*]] = and i64 [[TMP84]], 67109632613// CHECK-NEXT: [[TMP86:%.*]] = icmp eq i64 [[TMP85]], 67109632614// CHECK-NEXT: [[TMP87:%.*]] = and i1 true, [[TMP86]]615// CHECK-NEXT: br i1 [[TMP87]], label [[RESOLVER_RETURN41:%.*]], label [[RESOLVER_ELSE42:%.*]]616// CHECK: resolver_return41:617// CHECK-NEXT: ret ptr @fmv._Mi8mm618// CHECK: resolver_else42:619// CHECK-NEXT: [[TMP88:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8620// CHECK-NEXT: [[TMP89:%.*]] = and i64 [[TMP88]], 16777472621// CHECK-NEXT: [[TMP90:%.*]] = icmp eq i64 [[TMP89]], 16777472622// CHECK-NEXT: [[TMP91:%.*]] = and i1 true, [[TMP90]]623// CHECK-NEXT: br i1 [[TMP91]], label [[RESOLVER_RETURN43:%.*]], label [[RESOLVER_ELSE44:%.*]]624// CHECK: resolver_return43:625// CHECK-NEXT: ret ptr @fmv._Mfrintts626// CHECK: resolver_else44:627// CHECK-NEXT: [[TMP92:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8628// CHECK-NEXT: [[TMP93:%.*]] = and i64 [[TMP92]], 288230376164294656629// CHECK-NEXT: [[TMP94:%.*]] = icmp eq i64 [[TMP93]], 288230376164294656630// CHECK-NEXT: [[TMP95:%.*]] = and i1 true, [[TMP94]]631// CHECK-NEXT: br i1 [[TMP95]], label [[RESOLVER_RETURN45:%.*]], label [[RESOLVER_ELSE46:%.*]]632// CHECK: resolver_return45:633// CHECK-NEXT: ret ptr @fmv._Mrcpc3634// CHECK: resolver_else46:635// CHECK-NEXT: [[TMP96:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8636// CHECK-NEXT: [[TMP97:%.*]] = and i64 [[TMP96]], 12582912637// CHECK-NEXT: [[TMP98:%.*]] = icmp eq i64 [[TMP97]], 12582912638// CHECK-NEXT: [[TMP99:%.*]] = and i1 true, [[TMP98]]639// CHECK-NEXT: br i1 [[TMP99]], label [[RESOLVER_RETURN47:%.*]], label [[RESOLVER_ELSE48:%.*]]640// CHECK: resolver_return47:641// CHECK-NEXT: ret ptr @fmv._Mrcpc2642// CHECK: resolver_else48:643// CHECK-NEXT: [[TMP100:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8644// CHECK-NEXT: [[TMP101:%.*]] = and i64 [[TMP100]], 4194304645// CHECK-NEXT: [[TMP102:%.*]] = icmp eq i64 [[TMP101]], 4194304646// CHECK-NEXT: [[TMP103:%.*]] = and i1 true, [[TMP102]]647// CHECK-NEXT: br i1 [[TMP103]], label [[RESOLVER_RETURN49:%.*]], label [[RESOLVER_ELSE50:%.*]]648// CHECK: resolver_return49:649// CHECK-NEXT: ret ptr @fmv._Mrcpc650// CHECK: resolver_else50:651// CHECK-NEXT: [[TMP104:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8652// CHECK-NEXT: [[TMP105:%.*]] = and i64 [[TMP104]], 2097920653// CHECK-NEXT: [[TMP106:%.*]] = icmp eq i64 [[TMP105]], 2097920654// CHECK-NEXT: [[TMP107:%.*]] = and i1 true, [[TMP106]]655// CHECK-NEXT: br i1 [[TMP107]], label [[RESOLVER_RETURN51:%.*]], label [[RESOLVER_ELSE52:%.*]]656// CHECK: resolver_return51:657// CHECK-NEXT: ret ptr @fmv._Mfcma658// CHECK: resolver_else52:659// CHECK-NEXT: [[TMP108:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8660// CHECK-NEXT: [[TMP109:%.*]] = and i64 [[TMP108]], 1048832661// CHECK-NEXT: [[TMP110:%.*]] = icmp eq i64 [[TMP109]], 1048832662// CHECK-NEXT: [[TMP111:%.*]] = and i1 true, [[TMP110]]663// CHECK-NEXT: br i1 [[TMP111]], label [[RESOLVER_RETURN53:%.*]], label [[RESOLVER_ELSE54:%.*]]664// CHECK: resolver_return53:665// CHECK-NEXT: ret ptr @fmv._Mjscvt666// CHECK: resolver_else54:667// CHECK-NEXT: [[TMP112:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8668// CHECK-NEXT: [[TMP113:%.*]] = and i64 [[TMP112]], 786432669// CHECK-NEXT: [[TMP114:%.*]] = icmp eq i64 [[TMP113]], 786432670// CHECK-NEXT: [[TMP115:%.*]] = and i1 true, [[TMP114]]671// CHECK-NEXT: br i1 [[TMP115]], label [[RESOLVER_RETURN55:%.*]], label [[RESOLVER_ELSE56:%.*]]672// CHECK: resolver_return55:673// CHECK-NEXT: ret ptr @fmv._Mdpb2674// CHECK: resolver_else56:675// CHECK-NEXT: [[TMP116:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8676// CHECK-NEXT: [[TMP117:%.*]] = and i64 [[TMP116]], 262144677// CHECK-NEXT: [[TMP118:%.*]] = icmp eq i64 [[TMP117]], 262144678// CHECK-NEXT: [[TMP119:%.*]] = and i1 true, [[TMP118]]679// CHECK-NEXT: br i1 [[TMP119]], label [[RESOLVER_RETURN57:%.*]], label [[RESOLVER_ELSE58:%.*]]680// CHECK: resolver_return57:681// CHECK-NEXT: ret ptr @fmv._Mdpb682// CHECK: resolver_else58:683// CHECK-NEXT: [[TMP120:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8684// CHECK-NEXT: [[TMP121:%.*]] = and i64 [[TMP120]], 131072685// CHECK-NEXT: [[TMP122:%.*]] = icmp eq i64 [[TMP121]], 131072686// CHECK-NEXT: [[TMP123:%.*]] = and i1 true, [[TMP122]]687// CHECK-NEXT: br i1 [[TMP123]], label [[RESOLVER_RETURN59:%.*]], label [[RESOLVER_ELSE60:%.*]]688// CHECK: resolver_return59:689// CHECK-NEXT: ret ptr @fmv._Mdit690// CHECK: resolver_else60:691// CHECK-NEXT: [[TMP124:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8692// CHECK-NEXT: [[TMP125:%.*]] = and i64 [[TMP124]], 66312693// CHECK-NEXT: [[TMP126:%.*]] = icmp eq i64 [[TMP125]], 66312694// CHECK-NEXT: [[TMP127:%.*]] = and i1 true, [[TMP126]]695// CHECK-NEXT: br i1 [[TMP127]], label [[RESOLVER_RETURN61:%.*]], label [[RESOLVER_ELSE62:%.*]]696// CHECK: resolver_return61:697// CHECK-NEXT: ret ptr @fmv._Mfp16fml698// CHECK: resolver_else62:699// CHECK-NEXT: [[TMP128:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8700// CHECK-NEXT: [[TMP129:%.*]] = and i64 [[TMP128]], 65792701// CHECK-NEXT: [[TMP130:%.*]] = icmp eq i64 [[TMP129]], 65792702// CHECK-NEXT: [[TMP131:%.*]] = and i1 true, [[TMP130]]703// CHECK-NEXT: br i1 [[TMP131]], label [[RESOLVER_RETURN63:%.*]], label [[RESOLVER_ELSE64:%.*]]704// CHECK: resolver_return63:705// CHECK-NEXT: ret ptr @fmv._Mfp16706// CHECK: resolver_else64:707// CHECK-NEXT: [[TMP132:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8708// CHECK-NEXT: [[TMP133:%.*]] = and i64 [[TMP132]], 33536709// CHECK-NEXT: [[TMP134:%.*]] = icmp eq i64 [[TMP133]], 33536710// CHECK-NEXT: [[TMP135:%.*]] = and i1 true, [[TMP134]]711// CHECK-NEXT: br i1 [[TMP135]], label [[RESOLVER_RETURN65:%.*]], label [[RESOLVER_ELSE66:%.*]]712// CHECK: resolver_return65:713// CHECK-NEXT: ret ptr @fmv._Maes714// CHECK: resolver_else66:715// CHECK-NEXT: [[TMP136:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8716// CHECK-NEXT: [[TMP137:%.*]] = and i64 [[TMP136]], 13056717// CHECK-NEXT: [[TMP138:%.*]] = icmp eq i64 [[TMP137]], 13056718// CHECK-NEXT: [[TMP139:%.*]] = and i1 true, [[TMP138]]719// CHECK-NEXT: br i1 [[TMP139]], label [[RESOLVER_RETURN67:%.*]], label [[RESOLVER_ELSE68:%.*]]720// CHECK: resolver_return67:721// CHECK-NEXT: ret ptr @fmv._Msha3722// CHECK: resolver_else68:723// CHECK-NEXT: [[TMP140:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8724// CHECK-NEXT: [[TMP141:%.*]] = and i64 [[TMP140]], 4864725// CHECK-NEXT: [[TMP142:%.*]] = icmp eq i64 [[TMP141]], 4864726// CHECK-NEXT: [[TMP143:%.*]] = and i1 true, [[TMP142]]727// CHECK-NEXT: br i1 [[TMP143]], label [[RESOLVER_RETURN69:%.*]], label [[RESOLVER_ELSE70:%.*]]728// CHECK: resolver_return69:729// CHECK-NEXT: ret ptr @fmv._Msha2730// CHECK: resolver_else70:731// CHECK-NEXT: [[TMP144:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8732// CHECK-NEXT: [[TMP145:%.*]] = and i64 [[TMP144]], 1024733// CHECK-NEXT: [[TMP146:%.*]] = icmp eq i64 [[TMP145]], 1024734// CHECK-NEXT: [[TMP147:%.*]] = and i1 true, [[TMP146]]735// CHECK-NEXT: br i1 [[TMP147]], label [[RESOLVER_RETURN71:%.*]], label [[RESOLVER_ELSE72:%.*]]736// CHECK: resolver_return71:737// CHECK-NEXT: ret ptr @fmv._Mcrc738// CHECK: resolver_else72:739// CHECK-NEXT: [[TMP148:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8740// CHECK-NEXT: [[TMP149:%.*]] = and i64 [[TMP148]], 832741// CHECK-NEXT: [[TMP150:%.*]] = icmp eq i64 [[TMP149]], 832742// CHECK-NEXT: [[TMP151:%.*]] = and i1 true, [[TMP150]]743// CHECK-NEXT: br i1 [[TMP151]], label [[RESOLVER_RETURN73:%.*]], label [[RESOLVER_ELSE74:%.*]]744// CHECK: resolver_return73:745// CHECK-NEXT: ret ptr @fmv._Mrdm746// CHECK: resolver_else74:747// CHECK-NEXT: [[TMP152:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8748// CHECK-NEXT: [[TMP153:%.*]] = and i64 [[TMP152]], 800749// CHECK-NEXT: [[TMP154:%.*]] = icmp eq i64 [[TMP153]], 800750// CHECK-NEXT: [[TMP155:%.*]] = and i1 true, [[TMP154]]751// CHECK-NEXT: br i1 [[TMP155]], label [[RESOLVER_RETURN75:%.*]], label [[RESOLVER_ELSE76:%.*]]752// CHECK: resolver_return75:753// CHECK-NEXT: ret ptr @fmv._Msm4754// CHECK: resolver_else76:755// CHECK-NEXT: [[TMP156:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8756// CHECK-NEXT: [[TMP157:%.*]] = and i64 [[TMP156]], 784757// CHECK-NEXT: [[TMP158:%.*]] = icmp eq i64 [[TMP157]], 784758// CHECK-NEXT: [[TMP159:%.*]] = and i1 true, [[TMP158]]759// CHECK-NEXT: br i1 [[TMP159]], label [[RESOLVER_RETURN77:%.*]], label [[RESOLVER_ELSE78:%.*]]760// CHECK: resolver_return77:761// CHECK-NEXT: ret ptr @fmv._Mdotprod762// CHECK: resolver_else78:763// CHECK-NEXT: [[TMP160:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8764// CHECK-NEXT: [[TMP161:%.*]] = and i64 [[TMP160]], 768765// CHECK-NEXT: [[TMP162:%.*]] = icmp eq i64 [[TMP161]], 768766// CHECK-NEXT: [[TMP163:%.*]] = and i1 true, [[TMP162]]767// CHECK-NEXT: br i1 [[TMP163]], label [[RESOLVER_RETURN79:%.*]], label [[RESOLVER_ELSE80:%.*]]768// CHECK: resolver_return79:769// CHECK-NEXT: ret ptr @fmv._Msimd770// CHECK: resolver_else80:771// CHECK-NEXT: [[TMP164:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8772// CHECK-NEXT: [[TMP165:%.*]] = and i64 [[TMP164]], 256773// CHECK-NEXT: [[TMP166:%.*]] = icmp eq i64 [[TMP165]], 256774// CHECK-NEXT: [[TMP167:%.*]] = and i1 true, [[TMP166]]775// CHECK-NEXT: br i1 [[TMP167]], label [[RESOLVER_RETURN81:%.*]], label [[RESOLVER_ELSE82:%.*]]776// CHECK: resolver_return81:777// CHECK-NEXT: ret ptr @fmv._Mfp778// CHECK: resolver_else82:779// CHECK-NEXT: [[TMP168:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8780// CHECK-NEXT: [[TMP169:%.*]] = and i64 [[TMP168]], 128781// CHECK-NEXT: [[TMP170:%.*]] = icmp eq i64 [[TMP169]], 128782// CHECK-NEXT: [[TMP171:%.*]] = and i1 true, [[TMP170]]783// CHECK-NEXT: br i1 [[TMP171]], label [[RESOLVER_RETURN83:%.*]], label [[RESOLVER_ELSE84:%.*]]784// CHECK: resolver_return83:785// CHECK-NEXT: ret ptr @fmv._Mlse786// CHECK: resolver_else84:787// CHECK-NEXT: [[TMP172:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8788// CHECK-NEXT: [[TMP173:%.*]] = and i64 [[TMP172]], 6789// CHECK-NEXT: [[TMP174:%.*]] = icmp eq i64 [[TMP173]], 6790// CHECK-NEXT: [[TMP175:%.*]] = and i1 true, [[TMP174]]791// CHECK-NEXT: br i1 [[TMP175]], label [[RESOLVER_RETURN85:%.*]], label [[RESOLVER_ELSE86:%.*]]792// CHECK: resolver_return85:793// CHECK-NEXT: ret ptr @fmv._Mflagm2794// CHECK: resolver_else86:795// CHECK-NEXT: [[TMP176:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8796// CHECK-NEXT: [[TMP177:%.*]] = and i64 [[TMP176]], 2797// CHECK-NEXT: [[TMP178:%.*]] = icmp eq i64 [[TMP177]], 2798// CHECK-NEXT: [[TMP179:%.*]] = and i1 true, [[TMP178]]799// CHECK-NEXT: br i1 [[TMP179]], label [[RESOLVER_RETURN87:%.*]], label [[RESOLVER_ELSE88:%.*]]800// CHECK: resolver_return87:801// CHECK-NEXT: ret ptr @fmv._Mflagm802// CHECK: resolver_else88:803// CHECK-NEXT: [[TMP180:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8804// CHECK-NEXT: [[TMP181:%.*]] = and i64 [[TMP180]], 1805// CHECK-NEXT: [[TMP182:%.*]] = icmp eq i64 [[TMP181]], 1806// CHECK-NEXT: [[TMP183:%.*]] = and i1 true, [[TMP182]]807// CHECK-NEXT: br i1 [[TMP183]], label [[RESOLVER_RETURN89:%.*]], label [[RESOLVER_ELSE90:%.*]]808// CHECK: resolver_return89:809// CHECK-NEXT: ret ptr @fmv._Mrng810// CHECK: resolver_else90:811// CHECK-NEXT: ret ptr @fmv.default812//813//.814// CHECK: [[META0:![0-9]+]] = !{i32 1, !"wchar_size", i32 4}815// CHECK: [[META1:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"}816//.817