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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 52 3// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +bf16 -target-feature +fp8 -target-feature +fp8dot2 -target-feature +fp8dot4 -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,sroa | FileCheck %s4// RUN: %clang_cc1 -x c++ -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +bf16 -target-feature +fp8 -target-feature +fp8dot2 -target-feature +fp8dot4 -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,sroa | FileCheck %s -check-prefix CHECK-CXX5 6// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +bf16 -target-feature +fp8 -target-feature +fp8dot2 -target-feature +fp8dot4 -O3 -Werror -Wall -S -o /dev/null %s7 8// REQUIRES: aarch64-registered-target9 10#include <arm_neon.h>11 12// CHECK-LABEL: define dso_local <4 x half> @test_vdot_f16(13// CHECK-SAME: <4 x half> noundef [[VD:%.*]], <8 x i8> [[VN:%.*]], <8 x i8> [[VM:%.*]], i64 noundef [[FPMR:%.*]]) #[[ATTR0:[0-9]+]] {14// CHECK-NEXT: [[ENTRY:.*:]]15// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x half> [[VD]] to <4 x i16>16// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[TMP0]] to <8 x i8>17// CHECK-NEXT: call void @llvm.aarch64.set.fpmr(i64 [[FPMR]])18// CHECK-NEXT: [[FDOT2_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x half>19// CHECK-NEXT: [[FDOT21_I:%.*]] = call <4 x half> @llvm.aarch64.neon.fp8.fdot2.v4f16.v8i8(<4 x half> [[FDOT2_I]], <8 x i8> [[VN]], <8 x i8> [[VM]])20// CHECK-NEXT: ret <4 x half> [[FDOT21_I]]21//22// CHECK-CXX-LABEL: define dso_local noundef <4 x half> @_Z13test_vdot_f1613__Float16x4_t13__Mfloat8x8_tS0_m(23// CHECK-CXX-SAME: <4 x half> noundef [[VD:%.*]], <8 x i8> [[VN:%.*]], <8 x i8> [[VM:%.*]], i64 noundef [[FPMR:%.*]]) #[[ATTR0:[0-9]+]] {24// CHECK-CXX-NEXT: [[ENTRY:.*:]]25// CHECK-CXX-NEXT: [[TMP0:%.*]] = bitcast <4 x half> [[VD]] to <4 x i16>26// CHECK-CXX-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[TMP0]] to <8 x i8>27// CHECK-CXX-NEXT: call void @llvm.aarch64.set.fpmr(i64 [[FPMR]])28// CHECK-CXX-NEXT: [[FDOT2_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x half>29// CHECK-CXX-NEXT: [[FDOT21_I:%.*]] = call <4 x half> @llvm.aarch64.neon.fp8.fdot2.v4f16.v8i8(<4 x half> [[FDOT2_I]], <8 x i8> [[VN]], <8 x i8> [[VM]])30// CHECK-CXX-NEXT: ret <4 x half> [[FDOT21_I]]31//32float16x4_t test_vdot_f16(float16x4_t vd, mfloat8x8_t vn, mfloat8x8_t vm, fpm_t fpmr) {33 return vdot_f16_mf8_fpm(vd, vn, vm, fpmr);34}35 36// CHECK-LABEL: define dso_local <8 x half> @test_vdotq_f16(37// CHECK-SAME: <8 x half> noundef [[VD:%.*]], <16 x i8> [[VN:%.*]], <16 x i8> [[VM:%.*]], i64 noundef [[FPMR:%.*]]) #[[ATTR0]] {38// CHECK-NEXT: [[ENTRY:.*:]]39// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x half> [[VD]] to <8 x i16>40// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[TMP0]] to <16 x i8>41// CHECK-NEXT: call void @llvm.aarch64.set.fpmr(i64 [[FPMR]])42// CHECK-NEXT: [[FDOT2_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x half>43// CHECK-NEXT: [[FDOT21_I:%.*]] = call <8 x half> @llvm.aarch64.neon.fp8.fdot2.v8f16.v16i8(<8 x half> [[FDOT2_I]], <16 x i8> [[VN]], <16 x i8> [[VM]])44// CHECK-NEXT: ret <8 x half> [[FDOT21_I]]45//46// CHECK-CXX-LABEL: define dso_local noundef <8 x half> @_Z14test_vdotq_f1613__Float16x8_t14__Mfloat8x16_tS0_m(47// CHECK-CXX-SAME: <8 x half> noundef [[VD:%.*]], <16 x i8> [[VN:%.*]], <16 x i8> [[VM:%.*]], i64 noundef [[FPMR:%.*]]) #[[ATTR0]] {48// CHECK-CXX-NEXT: [[ENTRY:.*:]]49// CHECK-CXX-NEXT: [[TMP0:%.*]] = bitcast <8 x half> [[VD]] to <8 x i16>50// CHECK-CXX-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[TMP0]] to <16 x i8>51// CHECK-CXX-NEXT: call void @llvm.aarch64.set.fpmr(i64 [[FPMR]])52// CHECK-CXX-NEXT: [[FDOT2_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x half>53// CHECK-CXX-NEXT: [[FDOT21_I:%.*]] = call <8 x half> @llvm.aarch64.neon.fp8.fdot2.v8f16.v16i8(<8 x half> [[FDOT2_I]], <16 x i8> [[VN]], <16 x i8> [[VM]])54// CHECK-CXX-NEXT: ret <8 x half> [[FDOT21_I]]55//56float16x8_t test_vdotq_f16(float16x8_t vd, mfloat8x16_t vn, mfloat8x16_t vm, fpm_t fpmr) {57 return vdotq_f16_mf8_fpm(vd, vn, vm, fpmr);58}59 60// CHECK-LABEL: define dso_local <4 x half> @test_vdot_lane_f16(61// CHECK-SAME: <4 x half> noundef [[VD:%.*]], <8 x i8> [[VN:%.*]], <8 x i8> [[VM:%.*]], i64 noundef [[FPMR:%.*]]) #[[ATTR0]] {62// CHECK-NEXT: [[ENTRY:.*:]]63// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x half> [[VD]] to <4 x i16>64// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[TMP0]] to <8 x i8>65// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.vector.insert.v16i8.v8i8(<16 x i8> poison, <8 x i8> [[VM]], i64 0)66// CHECK-NEXT: call void @llvm.aarch64.set.fpmr(i64 [[FPMR]])67// CHECK-NEXT: [[FDOT2_LANE:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x half>68// CHECK-NEXT: [[FDOT2_LANE1:%.*]] = call <4 x half> @llvm.aarch64.neon.fp8.fdot2.lane.v4f16.v8i8(<4 x half> [[FDOT2_LANE]], <8 x i8> [[VN]], <16 x i8> [[TMP2]], i32 3)69// CHECK-NEXT: ret <4 x half> [[FDOT2_LANE1]]70//71// CHECK-CXX-LABEL: define dso_local noundef <4 x half> @_Z18test_vdot_lane_f1613__Float16x4_t13__Mfloat8x8_tS0_m(72// CHECK-CXX-SAME: <4 x half> noundef [[VD:%.*]], <8 x i8> [[VN:%.*]], <8 x i8> [[VM:%.*]], i64 noundef [[FPMR:%.*]]) #[[ATTR0]] {73// CHECK-CXX-NEXT: [[ENTRY:.*:]]74// CHECK-CXX-NEXT: [[TMP0:%.*]] = bitcast <4 x half> [[VD]] to <4 x i16>75// CHECK-CXX-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[TMP0]] to <8 x i8>76// CHECK-CXX-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.vector.insert.v16i8.v8i8(<16 x i8> poison, <8 x i8> [[VM]], i64 0)77// CHECK-CXX-NEXT: call void @llvm.aarch64.set.fpmr(i64 [[FPMR]])78// CHECK-CXX-NEXT: [[FDOT2_LANE:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x half>79// CHECK-CXX-NEXT: [[FDOT2_LANE1:%.*]] = call <4 x half> @llvm.aarch64.neon.fp8.fdot2.lane.v4f16.v8i8(<4 x half> [[FDOT2_LANE]], <8 x i8> [[VN]], <16 x i8> [[TMP2]], i32 3)80// CHECK-CXX-NEXT: ret <4 x half> [[FDOT2_LANE1]]81//82float16x4_t test_vdot_lane_f16(float16x4_t vd, mfloat8x8_t vn, mfloat8x8_t vm, fpm_t fpmr) {83 return vdot_lane_f16_mf8_fpm(vd, vn, vm, 3, fpmr);84}85 86// CHECK-LABEL: define dso_local <4 x half> @test_vdot_laneq_f16(87// CHECK-SAME: <4 x half> noundef [[VD:%.*]], <8 x i8> [[VN:%.*]], <16 x i8> [[VM:%.*]], i64 noundef [[FPMR:%.*]]) #[[ATTR0]] {88// CHECK-NEXT: [[ENTRY:.*:]]89// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x half> [[VD]] to <4 x i16>90// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[TMP0]] to <8 x i8>91// CHECK-NEXT: call void @llvm.aarch64.set.fpmr(i64 [[FPMR]])92// CHECK-NEXT: [[FDOT2_LANE:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x half>93// CHECK-NEXT: [[FDOT2_LANE1:%.*]] = call <4 x half> @llvm.aarch64.neon.fp8.fdot2.lane.v4f16.v8i8(<4 x half> [[FDOT2_LANE]], <8 x i8> [[VN]], <16 x i8> [[VM]], i32 7)94// CHECK-NEXT: ret <4 x half> [[FDOT2_LANE1]]95//96// CHECK-CXX-LABEL: define dso_local noundef <4 x half> @_Z19test_vdot_laneq_f1613__Float16x4_t13__Mfloat8x8_t14__Mfloat8x16_tm(97// CHECK-CXX-SAME: <4 x half> noundef [[VD:%.*]], <8 x i8> [[VN:%.*]], <16 x i8> [[VM:%.*]], i64 noundef [[FPMR:%.*]]) #[[ATTR0]] {98// CHECK-CXX-NEXT: [[ENTRY:.*:]]99// CHECK-CXX-NEXT: [[TMP0:%.*]] = bitcast <4 x half> [[VD]] to <4 x i16>100// CHECK-CXX-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[TMP0]] to <8 x i8>101// CHECK-CXX-NEXT: call void @llvm.aarch64.set.fpmr(i64 [[FPMR]])102// CHECK-CXX-NEXT: [[FDOT2_LANE:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x half>103// CHECK-CXX-NEXT: [[FDOT2_LANE1:%.*]] = call <4 x half> @llvm.aarch64.neon.fp8.fdot2.lane.v4f16.v8i8(<4 x half> [[FDOT2_LANE]], <8 x i8> [[VN]], <16 x i8> [[VM]], i32 7)104// CHECK-CXX-NEXT: ret <4 x half> [[FDOT2_LANE1]]105//106float16x4_t test_vdot_laneq_f16(float16x4_t vd, mfloat8x8_t vn, mfloat8x16_t vm, fpm_t fpmr) {107 return vdot_laneq_f16_mf8_fpm(vd, vn, vm, 7, fpmr);108}109 110// CHECK-LABEL: define dso_local <8 x half> @test_vdotq_lane_f16(111// CHECK-SAME: <8 x half> noundef [[VD:%.*]], <16 x i8> [[VN:%.*]], <8 x i8> [[VM:%.*]], i64 noundef [[FPMR:%.*]]) #[[ATTR0]] {112// CHECK-NEXT: [[ENTRY:.*:]]113// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x half> [[VD]] to <8 x i16>114// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[TMP0]] to <16 x i8>115// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.vector.insert.v16i8.v8i8(<16 x i8> poison, <8 x i8> [[VM]], i64 0)116// CHECK-NEXT: call void @llvm.aarch64.set.fpmr(i64 [[FPMR]])117// CHECK-NEXT: [[FDOT2_LANE:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x half>118// CHECK-NEXT: [[FDOT2_LANE1:%.*]] = call <8 x half> @llvm.aarch64.neon.fp8.fdot2.lane.v8f16.v16i8(<8 x half> [[FDOT2_LANE]], <16 x i8> [[VN]], <16 x i8> [[TMP2]], i32 3)119// CHECK-NEXT: ret <8 x half> [[FDOT2_LANE1]]120//121// CHECK-CXX-LABEL: define dso_local noundef <8 x half> @_Z19test_vdotq_lane_f1613__Float16x8_t14__Mfloat8x16_t13__Mfloat8x8_tm(122// CHECK-CXX-SAME: <8 x half> noundef [[VD:%.*]], <16 x i8> [[VN:%.*]], <8 x i8> [[VM:%.*]], i64 noundef [[FPMR:%.*]]) #[[ATTR0]] {123// CHECK-CXX-NEXT: [[ENTRY:.*:]]124// CHECK-CXX-NEXT: [[TMP0:%.*]] = bitcast <8 x half> [[VD]] to <8 x i16>125// CHECK-CXX-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[TMP0]] to <16 x i8>126// CHECK-CXX-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.vector.insert.v16i8.v8i8(<16 x i8> poison, <8 x i8> [[VM]], i64 0)127// CHECK-CXX-NEXT: call void @llvm.aarch64.set.fpmr(i64 [[FPMR]])128// CHECK-CXX-NEXT: [[FDOT2_LANE:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x half>129// CHECK-CXX-NEXT: [[FDOT2_LANE1:%.*]] = call <8 x half> @llvm.aarch64.neon.fp8.fdot2.lane.v8f16.v16i8(<8 x half> [[FDOT2_LANE]], <16 x i8> [[VN]], <16 x i8> [[TMP2]], i32 3)130// CHECK-CXX-NEXT: ret <8 x half> [[FDOT2_LANE1]]131//132float16x8_t test_vdotq_lane_f16(float16x8_t vd, mfloat8x16_t vn, mfloat8x8_t vm, fpm_t fpmr) {133 return vdotq_lane_f16_mf8_fpm(vd, vn, vm, 3, fpmr);134}135 136// CHECK-LABEL: define dso_local <8 x half> @test_vdotq_laneq_f16(137// CHECK-SAME: <8 x half> noundef [[VD:%.*]], <16 x i8> [[VN:%.*]], <16 x i8> [[VM:%.*]], i64 noundef [[FPMR:%.*]]) #[[ATTR0]] {138// CHECK-NEXT: [[ENTRY:.*:]]139// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x half> [[VD]] to <8 x i16>140// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[TMP0]] to <16 x i8>141// CHECK-NEXT: call void @llvm.aarch64.set.fpmr(i64 [[FPMR]])142// CHECK-NEXT: [[FDOT2_LANE:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x half>143// CHECK-NEXT: [[FDOT2_LANE1:%.*]] = call <8 x half> @llvm.aarch64.neon.fp8.fdot2.lane.v8f16.v16i8(<8 x half> [[FDOT2_LANE]], <16 x i8> [[VN]], <16 x i8> [[VM]], i32 7)144// CHECK-NEXT: ret <8 x half> [[FDOT2_LANE1]]145//146// CHECK-CXX-LABEL: define dso_local noundef <8 x half> @_Z20test_vdotq_laneq_f1613__Float16x8_t14__Mfloat8x16_tS0_m(147// CHECK-CXX-SAME: <8 x half> noundef [[VD:%.*]], <16 x i8> [[VN:%.*]], <16 x i8> [[VM:%.*]], i64 noundef [[FPMR:%.*]]) #[[ATTR0]] {148// CHECK-CXX-NEXT: [[ENTRY:.*:]]149// CHECK-CXX-NEXT: [[TMP0:%.*]] = bitcast <8 x half> [[VD]] to <8 x i16>150// CHECK-CXX-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[TMP0]] to <16 x i8>151// CHECK-CXX-NEXT: call void @llvm.aarch64.set.fpmr(i64 [[FPMR]])152// CHECK-CXX-NEXT: [[FDOT2_LANE:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x half>153// CHECK-CXX-NEXT: [[FDOT2_LANE1:%.*]] = call <8 x half> @llvm.aarch64.neon.fp8.fdot2.lane.v8f16.v16i8(<8 x half> [[FDOT2_LANE]], <16 x i8> [[VN]], <16 x i8> [[VM]], i32 7)154// CHECK-CXX-NEXT: ret <8 x half> [[FDOT2_LANE1]]155//156float16x8_t test_vdotq_laneq_f16(float16x8_t vd, mfloat8x16_t vn, mfloat8x16_t vm, fpm_t fpmr) {157 return vdotq_laneq_f16_mf8_fpm(vd, vn, vm, 7, fpmr);158}159 160// CHECK-LABEL: define dso_local <2 x float> @test_vdot_f32(161// CHECK-SAME: <2 x float> noundef [[VD:%.*]], <8 x i8> [[VN:%.*]], <8 x i8> [[VM:%.*]], i64 noundef [[FPMR:%.*]]) #[[ATTR0]] {162// CHECK-NEXT: [[ENTRY:.*:]]163// CHECK-NEXT: call void @llvm.aarch64.set.fpmr(i64 [[FPMR]])164// CHECK-NEXT: [[FDOT4_I:%.*]] = call <2 x float> @llvm.aarch64.neon.fp8.fdot4.v2f32.v8i8(<2 x float> [[VD]], <8 x i8> [[VN]], <8 x i8> [[VM]])165// CHECK-NEXT: ret <2 x float> [[FDOT4_I]]166//167// CHECK-CXX-LABEL: define dso_local noundef <2 x float> @_Z13test_vdot_f3213__Float32x2_t13__Mfloat8x8_tS0_m(168// CHECK-CXX-SAME: <2 x float> noundef [[VD:%.*]], <8 x i8> [[VN:%.*]], <8 x i8> [[VM:%.*]], i64 noundef [[FPMR:%.*]]) #[[ATTR0]] {169// CHECK-CXX-NEXT: [[ENTRY:.*:]]170// CHECK-CXX-NEXT: call void @llvm.aarch64.set.fpmr(i64 [[FPMR]])171// CHECK-CXX-NEXT: [[FDOT4_I:%.*]] = call <2 x float> @llvm.aarch64.neon.fp8.fdot4.v2f32.v8i8(<2 x float> [[VD]], <8 x i8> [[VN]], <8 x i8> [[VM]])172// CHECK-CXX-NEXT: ret <2 x float> [[FDOT4_I]]173//174float32x2_t test_vdot_f32(float32x2_t vd, mfloat8x8_t vn, mfloat8x8_t vm, fpm_t fpmr) {175 return vdot_f32_mf8_fpm(vd, vn, vm, fpmr);176}177 178// CHECK-LABEL: define dso_local <4 x float> @test_vdotq_f32(179// CHECK-SAME: <4 x float> noundef [[VD:%.*]], <16 x i8> [[VN:%.*]], <16 x i8> [[VM:%.*]], i64 noundef [[FPMR:%.*]]) #[[ATTR0]] {180// CHECK-NEXT: [[ENTRY:.*:]]181// CHECK-NEXT: call void @llvm.aarch64.set.fpmr(i64 [[FPMR]])182// CHECK-NEXT: [[FDOT4_I:%.*]] = call <4 x float> @llvm.aarch64.neon.fp8.fdot4.v4f32.v16i8(<4 x float> [[VD]], <16 x i8> [[VN]], <16 x i8> [[VM]])183// CHECK-NEXT: ret <4 x float> [[FDOT4_I]]184//185// CHECK-CXX-LABEL: define dso_local noundef <4 x float> @_Z14test_vdotq_f3213__Float32x4_t14__Mfloat8x16_tS0_m(186// CHECK-CXX-SAME: <4 x float> noundef [[VD:%.*]], <16 x i8> [[VN:%.*]], <16 x i8> [[VM:%.*]], i64 noundef [[FPMR:%.*]]) #[[ATTR0]] {187// CHECK-CXX-NEXT: [[ENTRY:.*:]]188// CHECK-CXX-NEXT: call void @llvm.aarch64.set.fpmr(i64 [[FPMR]])189// CHECK-CXX-NEXT: [[FDOT4_I:%.*]] = call <4 x float> @llvm.aarch64.neon.fp8.fdot4.v4f32.v16i8(<4 x float> [[VD]], <16 x i8> [[VN]], <16 x i8> [[VM]])190// CHECK-CXX-NEXT: ret <4 x float> [[FDOT4_I]]191//192float32x4_t test_vdotq_f32(float32x4_t vd, mfloat8x16_t vn, mfloat8x16_t vm, fpm_t fpmr) {193 return vdotq_f32_mf8_fpm(vd, vn, vm, fpmr);194}195 196// CHECK-LABEL: define dso_local <2 x float> @test_vdot_lane_f32(197// CHECK-SAME: <2 x float> noundef [[VD:%.*]], <8 x i8> [[VN:%.*]], <8 x i8> [[VM:%.*]], i64 noundef [[FPMR:%.*]]) #[[ATTR0]] {198// CHECK-NEXT: [[ENTRY:.*:]]199// CHECK-NEXT: [[TMP0:%.*]] = call <16 x i8> @llvm.vector.insert.v16i8.v8i8(<16 x i8> poison, <8 x i8> [[VM]], i64 0)200// CHECK-NEXT: call void @llvm.aarch64.set.fpmr(i64 [[FPMR]])201// CHECK-NEXT: [[FDOT4_LANE:%.*]] = call <2 x float> @llvm.aarch64.neon.fp8.fdot4.lane.v2f32.v8i8(<2 x float> [[VD]], <8 x i8> [[VN]], <16 x i8> [[TMP0]], i32 1)202// CHECK-NEXT: ret <2 x float> [[FDOT4_LANE]]203//204// CHECK-CXX-LABEL: define dso_local noundef <2 x float> @_Z18test_vdot_lane_f3213__Float32x2_t13__Mfloat8x8_tS0_m(205// CHECK-CXX-SAME: <2 x float> noundef [[VD:%.*]], <8 x i8> [[VN:%.*]], <8 x i8> [[VM:%.*]], i64 noundef [[FPMR:%.*]]) #[[ATTR0]] {206// CHECK-CXX-NEXT: [[ENTRY:.*:]]207// CHECK-CXX-NEXT: [[TMP0:%.*]] = call <16 x i8> @llvm.vector.insert.v16i8.v8i8(<16 x i8> poison, <8 x i8> [[VM]], i64 0)208// CHECK-CXX-NEXT: call void @llvm.aarch64.set.fpmr(i64 [[FPMR]])209// CHECK-CXX-NEXT: [[FDOT4_LANE:%.*]] = call <2 x float> @llvm.aarch64.neon.fp8.fdot4.lane.v2f32.v8i8(<2 x float> [[VD]], <8 x i8> [[VN]], <16 x i8> [[TMP0]], i32 1)210// CHECK-CXX-NEXT: ret <2 x float> [[FDOT4_LANE]]211//212float32x2_t test_vdot_lane_f32(float32x2_t vd, mfloat8x8_t vn, mfloat8x8_t vm, fpm_t fpmr) {213 return vdot_lane_f32_mf8_fpm(vd, vn, vm, 1, fpmr);214}215 216// CHECK-LABEL: define dso_local <2 x float> @test_vdot_laneq_f32(217// CHECK-SAME: <2 x float> noundef [[VD:%.*]], <8 x i8> [[VN:%.*]], <16 x i8> [[VM:%.*]], i64 noundef [[FPMR:%.*]]) #[[ATTR0]] {218// CHECK-NEXT: [[ENTRY:.*:]]219// CHECK-NEXT: call void @llvm.aarch64.set.fpmr(i64 [[FPMR]])220// CHECK-NEXT: [[FDOT4_LANE:%.*]] = call <2 x float> @llvm.aarch64.neon.fp8.fdot4.lane.v2f32.v8i8(<2 x float> [[VD]], <8 x i8> [[VN]], <16 x i8> [[VM]], i32 3)221// CHECK-NEXT: ret <2 x float> [[FDOT4_LANE]]222//223// CHECK-CXX-LABEL: define dso_local noundef <2 x float> @_Z19test_vdot_laneq_f3213__Float32x2_t13__Mfloat8x8_t14__Mfloat8x16_tm(224// CHECK-CXX-SAME: <2 x float> noundef [[VD:%.*]], <8 x i8> [[VN:%.*]], <16 x i8> [[VM:%.*]], i64 noundef [[FPMR:%.*]]) #[[ATTR0]] {225// CHECK-CXX-NEXT: [[ENTRY:.*:]]226// CHECK-CXX-NEXT: call void @llvm.aarch64.set.fpmr(i64 [[FPMR]])227// CHECK-CXX-NEXT: [[FDOT4_LANE:%.*]] = call <2 x float> @llvm.aarch64.neon.fp8.fdot4.lane.v2f32.v8i8(<2 x float> [[VD]], <8 x i8> [[VN]], <16 x i8> [[VM]], i32 3)228// CHECK-CXX-NEXT: ret <2 x float> [[FDOT4_LANE]]229//230float32x2_t test_vdot_laneq_f32(float32x2_t vd, mfloat8x8_t vn, mfloat8x16_t vm, fpm_t fpmr) {231 return vdot_laneq_f32_mf8_fpm(vd, vn, vm, 3, fpmr);232}233 234// CHECK-LABEL: define dso_local <4 x float> @test_vdotq_lane_f32(235// CHECK-SAME: <4 x float> noundef [[VD:%.*]], <16 x i8> [[VN:%.*]], <8 x i8> [[VM:%.*]], i64 noundef [[FPMR:%.*]]) #[[ATTR0]] {236// CHECK-NEXT: [[ENTRY:.*:]]237// CHECK-NEXT: [[TMP0:%.*]] = call <16 x i8> @llvm.vector.insert.v16i8.v8i8(<16 x i8> poison, <8 x i8> [[VM]], i64 0)238// CHECK-NEXT: call void @llvm.aarch64.set.fpmr(i64 [[FPMR]])239// CHECK-NEXT: [[FDOT4_LANE:%.*]] = call <4 x float> @llvm.aarch64.neon.fp8.fdot4.lane.v4f32.v16i8(<4 x float> [[VD]], <16 x i8> [[VN]], <16 x i8> [[TMP0]], i32 1)240// CHECK-NEXT: ret <4 x float> [[FDOT4_LANE]]241//242// CHECK-CXX-LABEL: define dso_local noundef <4 x float> @_Z19test_vdotq_lane_f3213__Float32x4_t14__Mfloat8x16_t13__Mfloat8x8_tm(243// CHECK-CXX-SAME: <4 x float> noundef [[VD:%.*]], <16 x i8> [[VN:%.*]], <8 x i8> [[VM:%.*]], i64 noundef [[FPMR:%.*]]) #[[ATTR0]] {244// CHECK-CXX-NEXT: [[ENTRY:.*:]]245// CHECK-CXX-NEXT: [[TMP0:%.*]] = call <16 x i8> @llvm.vector.insert.v16i8.v8i8(<16 x i8> poison, <8 x i8> [[VM]], i64 0)246// CHECK-CXX-NEXT: call void @llvm.aarch64.set.fpmr(i64 [[FPMR]])247// CHECK-CXX-NEXT: [[FDOT4_LANE:%.*]] = call <4 x float> @llvm.aarch64.neon.fp8.fdot4.lane.v4f32.v16i8(<4 x float> [[VD]], <16 x i8> [[VN]], <16 x i8> [[TMP0]], i32 1)248// CHECK-CXX-NEXT: ret <4 x float> [[FDOT4_LANE]]249//250float32x4_t test_vdotq_lane_f32(float32x4_t vd, mfloat8x16_t vn, mfloat8x8_t vm, fpm_t fpmr) {251 return vdotq_lane_f32_mf8_fpm(vd, vn, vm, 1, fpmr);252}253 254// CHECK-LABEL: define dso_local <4 x float> @test_vdotq_laneq_f32(255// CHECK-SAME: <4 x float> noundef [[VD:%.*]], <16 x i8> [[VN:%.*]], <16 x i8> [[VM:%.*]], i64 noundef [[FPMR:%.*]]) #[[ATTR0]] {256// CHECK-NEXT: [[ENTRY:.*:]]257// CHECK-NEXT: call void @llvm.aarch64.set.fpmr(i64 [[FPMR]])258// CHECK-NEXT: [[FDOT4_LANE:%.*]] = call <4 x float> @llvm.aarch64.neon.fp8.fdot4.lane.v4f32.v16i8(<4 x float> [[VD]], <16 x i8> [[VN]], <16 x i8> [[VM]], i32 3)259// CHECK-NEXT: ret <4 x float> [[FDOT4_LANE]]260//261// CHECK-CXX-LABEL: define dso_local noundef <4 x float> @_Z20test_vdotq_laneq_f3213__Float32x4_t14__Mfloat8x16_tS0_m(262// CHECK-CXX-SAME: <4 x float> noundef [[VD:%.*]], <16 x i8> [[VN:%.*]], <16 x i8> [[VM:%.*]], i64 noundef [[FPMR:%.*]]) #[[ATTR0]] {263// CHECK-CXX-NEXT: [[ENTRY:.*:]]264// CHECK-CXX-NEXT: call void @llvm.aarch64.set.fpmr(i64 [[FPMR]])265// CHECK-CXX-NEXT: [[FDOT4_LANE:%.*]] = call <4 x float> @llvm.aarch64.neon.fp8.fdot4.lane.v4f32.v16i8(<4 x float> [[VD]], <16 x i8> [[VN]], <16 x i8> [[VM]], i32 3)266// CHECK-CXX-NEXT: ret <4 x float> [[FDOT4_LANE]]267//268float32x4_t test_vdotq_laneq_f32(float32x4_t vd, mfloat8x16_t vn, mfloat8x16_t vm, fpm_t fpmr) {269 return vdotq_laneq_f32_mf8_fpm(vd, vn, vm, 3, fpmr);270}271