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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 52// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +bf16 -target-feature +fp8 -target-feature +fp8fma -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,sroa | FileCheck %s3// RUN: %clang_cc1 -x c++ -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +bf16 -target-feature +fp8 -target-feature +fp8fma -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,sroa | FileCheck %s -check-prefix CHECK-CXX4 5// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +bf16 -target-feature +fp8 -target-feature +fp8fma -disable-O0-optnone -Werror -Wall -S -o /dev/null %s6 7// REQUIRES: aarch64-registered-target8 9#include <arm_neon.h>10 11// CHECK-LABEL: define dso_local <8 x half> @test_vmlalb(12// CHECK-SAME: <8 x half> noundef [[VD:%.*]], <16 x i8> [[VN:%.*]], <16 x i8> [[VM:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0:[0-9]+]] {13// CHECK-NEXT: [[ENTRY:.*:]]14// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x half> [[VD]] to <8 x i16>15// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[TMP0]] to <16 x i8>16// CHECK-NEXT: call void @llvm.aarch64.set.fpmr(i64 [[FPM]])17// CHECK-NEXT: [[VMLAL_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x half>18// CHECK-NEXT: [[VMLAL1_I:%.*]] = call <8 x half> @llvm.aarch64.neon.fp8.fmlalb.v8f16(<8 x half> [[VMLAL_I]], <16 x i8> [[VN]], <16 x i8> [[VM]])19// CHECK-NEXT: ret <8 x half> [[VMLAL1_I]]20//21// CHECK-CXX-LABEL: define dso_local noundef <8 x half> @_Z11test_vmlalb13__Float16x8_t14__Mfloat8x16_tS0_m(22// CHECK-CXX-SAME: <8 x half> noundef [[VD:%.*]], <16 x i8> [[VN:%.*]], <16 x i8> [[VM:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0:[0-9]+]] {23// CHECK-CXX-NEXT: [[ENTRY:.*:]]24// CHECK-CXX-NEXT: [[TMP0:%.*]] = bitcast <8 x half> [[VD]] to <8 x i16>25// CHECK-CXX-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[TMP0]] to <16 x i8>26// CHECK-CXX-NEXT: call void @llvm.aarch64.set.fpmr(i64 [[FPM]])27// CHECK-CXX-NEXT: [[VMLAL_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x half>28// CHECK-CXX-NEXT: [[VMLAL1_I:%.*]] = call <8 x half> @llvm.aarch64.neon.fp8.fmlalb.v8f16(<8 x half> [[VMLAL_I]], <16 x i8> [[VN]], <16 x i8> [[VM]])29// CHECK-CXX-NEXT: ret <8 x half> [[VMLAL1_I]]30//31float16x8_t test_vmlalb(float16x8_t vd, mfloat8x16_t vn, mfloat8x16_t vm, fpm_t fpm) {32 return vmlalbq_f16_mf8_fpm(vd, vn, vm, fpm);33}34 35// CHECK-LABEL: define dso_local <8 x half> @test_vmlalt(36// CHECK-SAME: <8 x half> noundef [[VD:%.*]], <16 x i8> [[VN:%.*]], <16 x i8> [[VM:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] {37// CHECK-NEXT: [[ENTRY:.*:]]38// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x half> [[VD]] to <8 x i16>39// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[TMP0]] to <16 x i8>40// CHECK-NEXT: call void @llvm.aarch64.set.fpmr(i64 [[FPM]])41// CHECK-NEXT: [[VMLAL_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x half>42// CHECK-NEXT: [[VMLAL1_I:%.*]] = call <8 x half> @llvm.aarch64.neon.fp8.fmlalt.v8f16(<8 x half> [[VMLAL_I]], <16 x i8> [[VN]], <16 x i8> [[VM]])43// CHECK-NEXT: ret <8 x half> [[VMLAL1_I]]44//45// CHECK-CXX-LABEL: define dso_local noundef <8 x half> @_Z11test_vmlalt13__Float16x8_t14__Mfloat8x16_tS0_m(46// CHECK-CXX-SAME: <8 x half> noundef [[VD:%.*]], <16 x i8> [[VN:%.*]], <16 x i8> [[VM:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] {47// CHECK-CXX-NEXT: [[ENTRY:.*:]]48// CHECK-CXX-NEXT: [[TMP0:%.*]] = bitcast <8 x half> [[VD]] to <8 x i16>49// CHECK-CXX-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[TMP0]] to <16 x i8>50// CHECK-CXX-NEXT: call void @llvm.aarch64.set.fpmr(i64 [[FPM]])51// CHECK-CXX-NEXT: [[VMLAL_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x half>52// CHECK-CXX-NEXT: [[VMLAL1_I:%.*]] = call <8 x half> @llvm.aarch64.neon.fp8.fmlalt.v8f16(<8 x half> [[VMLAL_I]], <16 x i8> [[VN]], <16 x i8> [[VM]])53// CHECK-CXX-NEXT: ret <8 x half> [[VMLAL1_I]]54//55float16x8_t test_vmlalt(float16x8_t vd, mfloat8x16_t vn, mfloat8x16_t vm, fpm_t fpm) {56 return vmlaltq_f16_mf8_fpm(vd, vn, vm, fpm);57}58 59// CHECK-LABEL: define dso_local <4 x float> @test_vmlallbb(60// CHECK-SAME: <4 x float> noundef [[VD:%.*]], <16 x i8> [[VN:%.*]], <16 x i8> [[VM:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] {61// CHECK-NEXT: [[ENTRY:.*:]]62// CHECK-NEXT: call void @llvm.aarch64.set.fpmr(i64 [[FPM]])63// CHECK-NEXT: [[VMLALL_I:%.*]] = call <4 x float> @llvm.aarch64.neon.fp8.fmlallbb.v4f32(<4 x float> [[VD]], <16 x i8> [[VN]], <16 x i8> [[VM]])64// CHECK-NEXT: ret <4 x float> [[VMLALL_I]]65//66// CHECK-CXX-LABEL: define dso_local noundef <4 x float> @_Z13test_vmlallbb13__Float32x4_t14__Mfloat8x16_tS0_m(67// CHECK-CXX-SAME: <4 x float> noundef [[VD:%.*]], <16 x i8> [[VN:%.*]], <16 x i8> [[VM:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] {68// CHECK-CXX-NEXT: [[ENTRY:.*:]]69// CHECK-CXX-NEXT: call void @llvm.aarch64.set.fpmr(i64 [[FPM]])70// CHECK-CXX-NEXT: [[VMLALL_I:%.*]] = call <4 x float> @llvm.aarch64.neon.fp8.fmlallbb.v4f32(<4 x float> [[VD]], <16 x i8> [[VN]], <16 x i8> [[VM]])71// CHECK-CXX-NEXT: ret <4 x float> [[VMLALL_I]]72//73float32x4_t test_vmlallbb(float32x4_t vd, mfloat8x16_t vn, mfloat8x16_t vm, fpm_t fpm) {74 return vmlallbbq_f32_mf8_fpm(vd, vn, vm, fpm);75}76 77// CHECK-LABEL: define dso_local <4 x float> @test_vmlallbt(78// CHECK-SAME: <4 x float> noundef [[VD:%.*]], <16 x i8> [[VN:%.*]], <16 x i8> [[VM:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] {79// CHECK-NEXT: [[ENTRY:.*:]]80// CHECK-NEXT: call void @llvm.aarch64.set.fpmr(i64 [[FPM]])81// CHECK-NEXT: [[VMLALL_I:%.*]] = call <4 x float> @llvm.aarch64.neon.fp8.fmlallbt.v4f32(<4 x float> [[VD]], <16 x i8> [[VN]], <16 x i8> [[VM]])82// CHECK-NEXT: ret <4 x float> [[VMLALL_I]]83//84// CHECK-CXX-LABEL: define dso_local noundef <4 x float> @_Z13test_vmlallbt13__Float32x4_t14__Mfloat8x16_tS0_m(85// CHECK-CXX-SAME: <4 x float> noundef [[VD:%.*]], <16 x i8> [[VN:%.*]], <16 x i8> [[VM:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] {86// CHECK-CXX-NEXT: [[ENTRY:.*:]]87// CHECK-CXX-NEXT: call void @llvm.aarch64.set.fpmr(i64 [[FPM]])88// CHECK-CXX-NEXT: [[VMLALL_I:%.*]] = call <4 x float> @llvm.aarch64.neon.fp8.fmlallbt.v4f32(<4 x float> [[VD]], <16 x i8> [[VN]], <16 x i8> [[VM]])89// CHECK-CXX-NEXT: ret <4 x float> [[VMLALL_I]]90//91float32x4_t test_vmlallbt(float32x4_t vd, mfloat8x16_t vn, mfloat8x16_t vm, fpm_t fpm) {92 return vmlallbtq_f32_mf8_fpm(vd, vn, vm, fpm);93}94 95// CHECK-LABEL: define dso_local <4 x float> @test_vmlalltb(96// CHECK-SAME: <4 x float> noundef [[VD:%.*]], <16 x i8> [[VN:%.*]], <16 x i8> [[VM:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] {97// CHECK-NEXT: [[ENTRY:.*:]]98// CHECK-NEXT: call void @llvm.aarch64.set.fpmr(i64 [[FPM]])99// CHECK-NEXT: [[VMLALL_I:%.*]] = call <4 x float> @llvm.aarch64.neon.fp8.fmlalltb.v4f32(<4 x float> [[VD]], <16 x i8> [[VN]], <16 x i8> [[VM]])100// CHECK-NEXT: ret <4 x float> [[VMLALL_I]]101//102// CHECK-CXX-LABEL: define dso_local noundef <4 x float> @_Z13test_vmlalltb13__Float32x4_t14__Mfloat8x16_tS0_m(103// CHECK-CXX-SAME: <4 x float> noundef [[VD:%.*]], <16 x i8> [[VN:%.*]], <16 x i8> [[VM:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] {104// CHECK-CXX-NEXT: [[ENTRY:.*:]]105// CHECK-CXX-NEXT: call void @llvm.aarch64.set.fpmr(i64 [[FPM]])106// CHECK-CXX-NEXT: [[VMLALL_I:%.*]] = call <4 x float> @llvm.aarch64.neon.fp8.fmlalltb.v4f32(<4 x float> [[VD]], <16 x i8> [[VN]], <16 x i8> [[VM]])107// CHECK-CXX-NEXT: ret <4 x float> [[VMLALL_I]]108//109float32x4_t test_vmlalltb(float32x4_t vd, mfloat8x16_t vn, mfloat8x16_t vm, fpm_t fpm) {110 return vmlalltbq_f32_mf8_fpm(vd, vn, vm, fpm);111}112 113// CHECK-LABEL: define dso_local <4 x float> @test_vmlalltt(114// CHECK-SAME: <4 x float> noundef [[VD:%.*]], <16 x i8> [[VN:%.*]], <16 x i8> [[VM:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] {115// CHECK-NEXT: [[ENTRY:.*:]]116// CHECK-NEXT: call void @llvm.aarch64.set.fpmr(i64 [[FPM]])117// CHECK-NEXT: [[VMLALL_I:%.*]] = call <4 x float> @llvm.aarch64.neon.fp8.fmlalltt.v4f32(<4 x float> [[VD]], <16 x i8> [[VN]], <16 x i8> [[VM]])118// CHECK-NEXT: ret <4 x float> [[VMLALL_I]]119//120// CHECK-CXX-LABEL: define dso_local noundef <4 x float> @_Z13test_vmlalltt13__Float32x4_t14__Mfloat8x16_tS0_m(121// CHECK-CXX-SAME: <4 x float> noundef [[VD:%.*]], <16 x i8> [[VN:%.*]], <16 x i8> [[VM:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] {122// CHECK-CXX-NEXT: [[ENTRY:.*:]]123// CHECK-CXX-NEXT: call void @llvm.aarch64.set.fpmr(i64 [[FPM]])124// CHECK-CXX-NEXT: [[VMLALL_I:%.*]] = call <4 x float> @llvm.aarch64.neon.fp8.fmlalltt.v4f32(<4 x float> [[VD]], <16 x i8> [[VN]], <16 x i8> [[VM]])125// CHECK-CXX-NEXT: ret <4 x float> [[VMLALL_I]]126//127float32x4_t test_vmlalltt(float32x4_t vd, mfloat8x16_t vn, mfloat8x16_t vm, fpm_t fpm) {128 return vmlallttq_f32_mf8_fpm(vd, vn, vm, fpm);129}130 131// CHECK-LABEL: define dso_local <8 x half> @test_vmlalb_lane(132// CHECK-SAME: <8 x half> noundef [[VD:%.*]], <16 x i8> [[VN:%.*]], <8 x i8> [[VM:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] {133// CHECK-NEXT: [[ENTRY:.*:]]134// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x half> [[VD]] to <8 x i16>135// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[TMP0]] to <16 x i8>136// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.vector.insert.v16i8.v8i8(<16 x i8> poison, <8 x i8> [[VM]], i64 0)137// CHECK-NEXT: call void @llvm.aarch64.set.fpmr(i64 [[FPM]])138// CHECK-NEXT: [[VMLAL_LANE:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x half>139// CHECK-NEXT: [[VMLAL_LANE1:%.*]] = call <8 x half> @llvm.aarch64.neon.fp8.fmlalb.lane.v8f16(<8 x half> [[VMLAL_LANE]], <16 x i8> [[VN]], <16 x i8> [[TMP2]], i32 0)140// CHECK-NEXT: ret <8 x half> [[VMLAL_LANE1]]141//142// CHECK-CXX-LABEL: define dso_local noundef <8 x half> @_Z16test_vmlalb_lane13__Float16x8_t14__Mfloat8x16_t13__Mfloat8x8_tm(143// CHECK-CXX-SAME: <8 x half> noundef [[VD:%.*]], <16 x i8> [[VN:%.*]], <8 x i8> [[VM:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] {144// CHECK-CXX-NEXT: [[ENTRY:.*:]]145// CHECK-CXX-NEXT: [[TMP0:%.*]] = bitcast <8 x half> [[VD]] to <8 x i16>146// CHECK-CXX-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[TMP0]] to <16 x i8>147// CHECK-CXX-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.vector.insert.v16i8.v8i8(<16 x i8> poison, <8 x i8> [[VM]], i64 0)148// CHECK-CXX-NEXT: call void @llvm.aarch64.set.fpmr(i64 [[FPM]])149// CHECK-CXX-NEXT: [[VMLAL_LANE:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x half>150// CHECK-CXX-NEXT: [[VMLAL_LANE1:%.*]] = call <8 x half> @llvm.aarch64.neon.fp8.fmlalb.lane.v8f16(<8 x half> [[VMLAL_LANE]], <16 x i8> [[VN]], <16 x i8> [[TMP2]], i32 0)151// CHECK-CXX-NEXT: ret <8 x half> [[VMLAL_LANE1]]152//153float16x8_t test_vmlalb_lane(float16x8_t vd, mfloat8x16_t vn, mfloat8x8_t vm, fpm_t fpm) {154 return vmlalbq_lane_f16_mf8_fpm(vd, vn, vm, 0, fpm);155}156 157// CHECK-LABEL: define dso_local <8 x half> @test_vmlalb_laneq(158// CHECK-SAME: <8 x half> noundef [[VD:%.*]], <16 x i8> [[VN:%.*]], <16 x i8> [[VM:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] {159// CHECK-NEXT: [[ENTRY:.*:]]160// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x half> [[VD]] to <8 x i16>161// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[TMP0]] to <16 x i8>162// CHECK-NEXT: call void @llvm.aarch64.set.fpmr(i64 [[FPM]])163// CHECK-NEXT: [[VMLAL_LANE:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x half>164// CHECK-NEXT: [[VMLAL_LANE1:%.*]] = call <8 x half> @llvm.aarch64.neon.fp8.fmlalb.lane.v8f16(<8 x half> [[VMLAL_LANE]], <16 x i8> [[VN]], <16 x i8> [[VM]], i32 0)165// CHECK-NEXT: ret <8 x half> [[VMLAL_LANE1]]166//167// CHECK-CXX-LABEL: define dso_local noundef <8 x half> @_Z17test_vmlalb_laneq13__Float16x8_t14__Mfloat8x16_tS0_m(168// CHECK-CXX-SAME: <8 x half> noundef [[VD:%.*]], <16 x i8> [[VN:%.*]], <16 x i8> [[VM:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] {169// CHECK-CXX-NEXT: [[ENTRY:.*:]]170// CHECK-CXX-NEXT: [[TMP0:%.*]] = bitcast <8 x half> [[VD]] to <8 x i16>171// CHECK-CXX-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[TMP0]] to <16 x i8>172// CHECK-CXX-NEXT: call void @llvm.aarch64.set.fpmr(i64 [[FPM]])173// CHECK-CXX-NEXT: [[VMLAL_LANE:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x half>174// CHECK-CXX-NEXT: [[VMLAL_LANE1:%.*]] = call <8 x half> @llvm.aarch64.neon.fp8.fmlalb.lane.v8f16(<8 x half> [[VMLAL_LANE]], <16 x i8> [[VN]], <16 x i8> [[VM]], i32 0)175// CHECK-CXX-NEXT: ret <8 x half> [[VMLAL_LANE1]]176//177float16x8_t test_vmlalb_laneq(float16x8_t vd, mfloat8x16_t vn, mfloat8x16_t vm, fpm_t fpm) {178 return vmlalbq_laneq_f16_mf8_fpm(vd, vn, vm, 0, fpm);179}180 181// CHECK-LABEL: define dso_local <8 x half> @test_vmlalt_lane(182// CHECK-SAME: <8 x half> noundef [[VD:%.*]], <16 x i8> [[VN:%.*]], <8 x i8> [[VM:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] {183// CHECK-NEXT: [[ENTRY:.*:]]184// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x half> [[VD]] to <8 x i16>185// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[TMP0]] to <16 x i8>186// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.vector.insert.v16i8.v8i8(<16 x i8> poison, <8 x i8> [[VM]], i64 0)187// CHECK-NEXT: call void @llvm.aarch64.set.fpmr(i64 [[FPM]])188// CHECK-NEXT: [[VMLAL_LANE:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x half>189// CHECK-NEXT: [[VMLAL_LANE1:%.*]] = call <8 x half> @llvm.aarch64.neon.fp8.fmlalt.lane.v8f16(<8 x half> [[VMLAL_LANE]], <16 x i8> [[VN]], <16 x i8> [[TMP2]], i32 7)190// CHECK-NEXT: ret <8 x half> [[VMLAL_LANE1]]191//192// CHECK-CXX-LABEL: define dso_local noundef <8 x half> @_Z16test_vmlalt_lane13__Float16x8_t14__Mfloat8x16_t13__Mfloat8x8_tm(193// CHECK-CXX-SAME: <8 x half> noundef [[VD:%.*]], <16 x i8> [[VN:%.*]], <8 x i8> [[VM:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] {194// CHECK-CXX-NEXT: [[ENTRY:.*:]]195// CHECK-CXX-NEXT: [[TMP0:%.*]] = bitcast <8 x half> [[VD]] to <8 x i16>196// CHECK-CXX-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[TMP0]] to <16 x i8>197// CHECK-CXX-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.vector.insert.v16i8.v8i8(<16 x i8> poison, <8 x i8> [[VM]], i64 0)198// CHECK-CXX-NEXT: call void @llvm.aarch64.set.fpmr(i64 [[FPM]])199// CHECK-CXX-NEXT: [[VMLAL_LANE:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x half>200// CHECK-CXX-NEXT: [[VMLAL_LANE1:%.*]] = call <8 x half> @llvm.aarch64.neon.fp8.fmlalt.lane.v8f16(<8 x half> [[VMLAL_LANE]], <16 x i8> [[VN]], <16 x i8> [[TMP2]], i32 7)201// CHECK-CXX-NEXT: ret <8 x half> [[VMLAL_LANE1]]202//203float16x8_t test_vmlalt_lane(float16x8_t vd, mfloat8x16_t vn, mfloat8x8_t vm, fpm_t fpm) {204 return vmlaltq_lane_f16_mf8_fpm(vd, vn, vm, 7, fpm);205}206 207// CHECK-LABEL: define dso_local <8 x half> @test_vmlalt_laneq(208// CHECK-SAME: <8 x half> noundef [[VD:%.*]], <16 x i8> [[VN:%.*]], <16 x i8> [[VM:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] {209// CHECK-NEXT: [[ENTRY:.*:]]210// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x half> [[VD]] to <8 x i16>211// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[TMP0]] to <16 x i8>212// CHECK-NEXT: call void @llvm.aarch64.set.fpmr(i64 [[FPM]])213// CHECK-NEXT: [[VMLAL_LANE:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x half>214// CHECK-NEXT: [[VMLAL_LANE1:%.*]] = call <8 x half> @llvm.aarch64.neon.fp8.fmlalt.lane.v8f16(<8 x half> [[VMLAL_LANE]], <16 x i8> [[VN]], <16 x i8> [[VM]], i32 15)215// CHECK-NEXT: ret <8 x half> [[VMLAL_LANE1]]216//217// CHECK-CXX-LABEL: define dso_local noundef <8 x half> @_Z17test_vmlalt_laneq13__Float16x8_t14__Mfloat8x16_tS0_m(218// CHECK-CXX-SAME: <8 x half> noundef [[VD:%.*]], <16 x i8> [[VN:%.*]], <16 x i8> [[VM:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] {219// CHECK-CXX-NEXT: [[ENTRY:.*:]]220// CHECK-CXX-NEXT: [[TMP0:%.*]] = bitcast <8 x half> [[VD]] to <8 x i16>221// CHECK-CXX-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[TMP0]] to <16 x i8>222// CHECK-CXX-NEXT: call void @llvm.aarch64.set.fpmr(i64 [[FPM]])223// CHECK-CXX-NEXT: [[VMLAL_LANE:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x half>224// CHECK-CXX-NEXT: [[VMLAL_LANE1:%.*]] = call <8 x half> @llvm.aarch64.neon.fp8.fmlalt.lane.v8f16(<8 x half> [[VMLAL_LANE]], <16 x i8> [[VN]], <16 x i8> [[VM]], i32 15)225// CHECK-CXX-NEXT: ret <8 x half> [[VMLAL_LANE1]]226//227float16x8_t test_vmlalt_laneq(float16x8_t vd, mfloat8x16_t vn, mfloat8x16_t vm, fpm_t fpm) {228 return vmlaltq_laneq_f16_mf8_fpm(vd, vn, vm, 15, fpm);229}230 231// CHECK-LABEL: define dso_local <4 x float> @test_vmlallbb_lane(232// CHECK-SAME: <4 x float> noundef [[VD:%.*]], <16 x i8> [[VN:%.*]], <8 x i8> [[VM:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] {233// CHECK-NEXT: [[ENTRY:.*:]]234// CHECK-NEXT: [[TMP0:%.*]] = call <16 x i8> @llvm.vector.insert.v16i8.v8i8(<16 x i8> poison, <8 x i8> [[VM]], i64 0)235// CHECK-NEXT: call void @llvm.aarch64.set.fpmr(i64 [[FPM]])236// CHECK-NEXT: [[VMLALL_LANE:%.*]] = call <4 x float> @llvm.aarch64.neon.fp8.fmlallbb.lane.v4f32(<4 x float> [[VD]], <16 x i8> [[VN]], <16 x i8> [[TMP0]], i32 0)237// CHECK-NEXT: ret <4 x float> [[VMLALL_LANE]]238//239// CHECK-CXX-LABEL: define dso_local noundef <4 x float> @_Z18test_vmlallbb_lane13__Float32x4_t14__Mfloat8x16_t13__Mfloat8x8_tm(240// CHECK-CXX-SAME: <4 x float> noundef [[VD:%.*]], <16 x i8> [[VN:%.*]], <8 x i8> [[VM:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] {241// CHECK-CXX-NEXT: [[ENTRY:.*:]]242// CHECK-CXX-NEXT: [[TMP0:%.*]] = call <16 x i8> @llvm.vector.insert.v16i8.v8i8(<16 x i8> poison, <8 x i8> [[VM]], i64 0)243// CHECK-CXX-NEXT: call void @llvm.aarch64.set.fpmr(i64 [[FPM]])244// CHECK-CXX-NEXT: [[VMLALL_LANE:%.*]] = call <4 x float> @llvm.aarch64.neon.fp8.fmlallbb.lane.v4f32(<4 x float> [[VD]], <16 x i8> [[VN]], <16 x i8> [[TMP0]], i32 0)245// CHECK-CXX-NEXT: ret <4 x float> [[VMLALL_LANE]]246//247float32x4_t test_vmlallbb_lane(float32x4_t vd, mfloat8x16_t vn, mfloat8x8_t vm, fpm_t fpm) {248 return vmlallbbq_lane_f32_mf8_fpm(vd, vn, vm, 0, fpm);249}250 251// CHECK-LABEL: define dso_local <4 x float> @test_vmlallbb_laneq(252// CHECK-SAME: <4 x float> noundef [[VD:%.*]], <16 x i8> [[VN:%.*]], <16 x i8> [[VM:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] {253// CHECK-NEXT: [[ENTRY:.*:]]254// CHECK-NEXT: call void @llvm.aarch64.set.fpmr(i64 [[FPM]])255// CHECK-NEXT: [[VMLALL_LANE:%.*]] = call <4 x float> @llvm.aarch64.neon.fp8.fmlallbb.lane.v4f32(<4 x float> [[VD]], <16 x i8> [[VN]], <16 x i8> [[VM]], i32 0)256// CHECK-NEXT: ret <4 x float> [[VMLALL_LANE]]257//258// CHECK-CXX-LABEL: define dso_local noundef <4 x float> @_Z19test_vmlallbb_laneq13__Float32x4_t14__Mfloat8x16_tS0_m(259// CHECK-CXX-SAME: <4 x float> noundef [[VD:%.*]], <16 x i8> [[VN:%.*]], <16 x i8> [[VM:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] {260// CHECK-CXX-NEXT: [[ENTRY:.*:]]261// CHECK-CXX-NEXT: call void @llvm.aarch64.set.fpmr(i64 [[FPM]])262// CHECK-CXX-NEXT: [[VMLALL_LANE:%.*]] = call <4 x float> @llvm.aarch64.neon.fp8.fmlallbb.lane.v4f32(<4 x float> [[VD]], <16 x i8> [[VN]], <16 x i8> [[VM]], i32 0)263// CHECK-CXX-NEXT: ret <4 x float> [[VMLALL_LANE]]264//265float32x4_t test_vmlallbb_laneq(float32x4_t vd, mfloat8x16_t vn, mfloat8x16_t vm, fpm_t fpm) {266 return vmlallbbq_laneq_f32_mf8_fpm(vd, vn, vm, 0, fpm);267}268 269// CHECK-LABEL: define dso_local <4 x float> @test_vmlallbt_lane(270// CHECK-SAME: <4 x float> noundef [[VD:%.*]], <16 x i8> [[VN:%.*]], <8 x i8> [[VM:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] {271// CHECK-NEXT: [[ENTRY:.*:]]272// CHECK-NEXT: [[TMP0:%.*]] = call <16 x i8> @llvm.vector.insert.v16i8.v8i8(<16 x i8> poison, <8 x i8> [[VM]], i64 0)273// CHECK-NEXT: call void @llvm.aarch64.set.fpmr(i64 [[FPM]])274// CHECK-NEXT: [[VMLALL_LANE:%.*]] = call <4 x float> @llvm.aarch64.neon.fp8.fmlallbt.lane.v4f32(<4 x float> [[VD]], <16 x i8> [[VN]], <16 x i8> [[TMP0]], i32 3)275// CHECK-NEXT: ret <4 x float> [[VMLALL_LANE]]276//277// CHECK-CXX-LABEL: define dso_local noundef <4 x float> @_Z18test_vmlallbt_lane13__Float32x4_t14__Mfloat8x16_t13__Mfloat8x8_tm(278// CHECK-CXX-SAME: <4 x float> noundef [[VD:%.*]], <16 x i8> [[VN:%.*]], <8 x i8> [[VM:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] {279// CHECK-CXX-NEXT: [[ENTRY:.*:]]280// CHECK-CXX-NEXT: [[TMP0:%.*]] = call <16 x i8> @llvm.vector.insert.v16i8.v8i8(<16 x i8> poison, <8 x i8> [[VM]], i64 0)281// CHECK-CXX-NEXT: call void @llvm.aarch64.set.fpmr(i64 [[FPM]])282// CHECK-CXX-NEXT: [[VMLALL_LANE:%.*]] = call <4 x float> @llvm.aarch64.neon.fp8.fmlallbt.lane.v4f32(<4 x float> [[VD]], <16 x i8> [[VN]], <16 x i8> [[TMP0]], i32 3)283// CHECK-CXX-NEXT: ret <4 x float> [[VMLALL_LANE]]284//285float32x4_t test_vmlallbt_lane(float32x4_t vd, mfloat8x16_t vn, mfloat8x8_t vm, fpm_t fpm) {286 return vmlallbtq_lane_f32_mf8_fpm(vd, vn, vm, 3, fpm);287}288 289// CHECK-LABEL: define dso_local <4 x float> @test_vmlallbt_laneq(290// CHECK-SAME: <4 x float> noundef [[VD:%.*]], <16 x i8> [[VN:%.*]], <16 x i8> [[VM:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] {291// CHECK-NEXT: [[ENTRY:.*:]]292// CHECK-NEXT: call void @llvm.aarch64.set.fpmr(i64 [[FPM]])293// CHECK-NEXT: [[VMLALL_LANE:%.*]] = call <4 x float> @llvm.aarch64.neon.fp8.fmlallbt.lane.v4f32(<4 x float> [[VD]], <16 x i8> [[VN]], <16 x i8> [[VM]], i32 3)294// CHECK-NEXT: ret <4 x float> [[VMLALL_LANE]]295//296// CHECK-CXX-LABEL: define dso_local noundef <4 x float> @_Z19test_vmlallbt_laneq13__Float32x4_t14__Mfloat8x16_tS0_m(297// CHECK-CXX-SAME: <4 x float> noundef [[VD:%.*]], <16 x i8> [[VN:%.*]], <16 x i8> [[VM:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] {298// CHECK-CXX-NEXT: [[ENTRY:.*:]]299// CHECK-CXX-NEXT: call void @llvm.aarch64.set.fpmr(i64 [[FPM]])300// CHECK-CXX-NEXT: [[VMLALL_LANE:%.*]] = call <4 x float> @llvm.aarch64.neon.fp8.fmlallbt.lane.v4f32(<4 x float> [[VD]], <16 x i8> [[VN]], <16 x i8> [[VM]], i32 3)301// CHECK-CXX-NEXT: ret <4 x float> [[VMLALL_LANE]]302//303float32x4_t test_vmlallbt_laneq(float32x4_t vd, mfloat8x16_t vn, mfloat8x16_t vm, fpm_t fpm) {304 return vmlallbtq_laneq_f32_mf8_fpm(vd, vn, vm, 3, fpm);305}306 307// CHECK-LABEL: define dso_local <4 x float> @test_vmlalltb_lane(308// CHECK-SAME: <4 x float> noundef [[VD:%.*]], <16 x i8> [[VN:%.*]], <8 x i8> [[VM:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] {309// CHECK-NEXT: [[ENTRY:.*:]]310// CHECK-NEXT: [[TMP0:%.*]] = call <16 x i8> @llvm.vector.insert.v16i8.v8i8(<16 x i8> poison, <8 x i8> [[VM]], i64 0)311// CHECK-NEXT: call void @llvm.aarch64.set.fpmr(i64 [[FPM]])312// CHECK-NEXT: [[VMLALL_LANE:%.*]] = call <4 x float> @llvm.aarch64.neon.fp8.fmlalltb.lane.v4f32(<4 x float> [[VD]], <16 x i8> [[VN]], <16 x i8> [[TMP0]], i32 7)313// CHECK-NEXT: ret <4 x float> [[VMLALL_LANE]]314//315// CHECK-CXX-LABEL: define dso_local noundef <4 x float> @_Z18test_vmlalltb_lane13__Float32x4_t14__Mfloat8x16_t13__Mfloat8x8_tm(316// CHECK-CXX-SAME: <4 x float> noundef [[VD:%.*]], <16 x i8> [[VN:%.*]], <8 x i8> [[VM:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] {317// CHECK-CXX-NEXT: [[ENTRY:.*:]]318// CHECK-CXX-NEXT: [[TMP0:%.*]] = call <16 x i8> @llvm.vector.insert.v16i8.v8i8(<16 x i8> poison, <8 x i8> [[VM]], i64 0)319// CHECK-CXX-NEXT: call void @llvm.aarch64.set.fpmr(i64 [[FPM]])320// CHECK-CXX-NEXT: [[VMLALL_LANE:%.*]] = call <4 x float> @llvm.aarch64.neon.fp8.fmlalltb.lane.v4f32(<4 x float> [[VD]], <16 x i8> [[VN]], <16 x i8> [[TMP0]], i32 7)321// CHECK-CXX-NEXT: ret <4 x float> [[VMLALL_LANE]]322//323float32x4_t test_vmlalltb_lane(float32x4_t vd, mfloat8x16_t vn, mfloat8x8_t vm, fpm_t fpm) {324 return vmlalltbq_lane_f32_mf8_fpm(vd, vn, vm, 7, fpm);325}326 327// CHECK-LABEL: define dso_local <4 x float> @test_vmlalltb_laneq(328// CHECK-SAME: <4 x float> noundef [[VD:%.*]], <16 x i8> [[VN:%.*]], <16 x i8> [[VM:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] {329// CHECK-NEXT: [[ENTRY:.*:]]330// CHECK-NEXT: call void @llvm.aarch64.set.fpmr(i64 [[FPM]])331// CHECK-NEXT: [[VMLALL_LANE:%.*]] = call <4 x float> @llvm.aarch64.neon.fp8.fmlalltb.lane.v4f32(<4 x float> [[VD]], <16 x i8> [[VN]], <16 x i8> [[VM]], i32 7)332// CHECK-NEXT: ret <4 x float> [[VMLALL_LANE]]333//334// CHECK-CXX-LABEL: define dso_local noundef <4 x float> @_Z19test_vmlalltb_laneq13__Float32x4_t14__Mfloat8x16_tS0_m(335// CHECK-CXX-SAME: <4 x float> noundef [[VD:%.*]], <16 x i8> [[VN:%.*]], <16 x i8> [[VM:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] {336// CHECK-CXX-NEXT: [[ENTRY:.*:]]337// CHECK-CXX-NEXT: call void @llvm.aarch64.set.fpmr(i64 [[FPM]])338// CHECK-CXX-NEXT: [[VMLALL_LANE:%.*]] = call <4 x float> @llvm.aarch64.neon.fp8.fmlalltb.lane.v4f32(<4 x float> [[VD]], <16 x i8> [[VN]], <16 x i8> [[VM]], i32 7)339// CHECK-CXX-NEXT: ret <4 x float> [[VMLALL_LANE]]340//341float32x4_t test_vmlalltb_laneq(float32x4_t vd, mfloat8x16_t vn, mfloat8x16_t vm, fpm_t fpm) {342 return vmlalltbq_laneq_f32_mf8_fpm(vd, vn, vm, 7, fpm);343}344 345// CHECK-LABEL: define dso_local <4 x float> @test_vmlalltt_lane(346// CHECK-SAME: <4 x float> noundef [[VD:%.*]], <16 x i8> [[VN:%.*]], <8 x i8> [[VM:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] {347// CHECK-NEXT: [[ENTRY:.*:]]348// CHECK-NEXT: [[TMP0:%.*]] = call <16 x i8> @llvm.vector.insert.v16i8.v8i8(<16 x i8> poison, <8 x i8> [[VM]], i64 0)349// CHECK-NEXT: call void @llvm.aarch64.set.fpmr(i64 [[FPM]])350// CHECK-NEXT: [[VMLALL_LANE:%.*]] = call <4 x float> @llvm.aarch64.neon.fp8.fmlalltt.lane.v4f32(<4 x float> [[VD]], <16 x i8> [[VN]], <16 x i8> [[TMP0]], i32 7)351// CHECK-NEXT: ret <4 x float> [[VMLALL_LANE]]352//353// CHECK-CXX-LABEL: define dso_local noundef <4 x float> @_Z18test_vmlalltt_lane13__Float32x4_t14__Mfloat8x16_t13__Mfloat8x8_tm(354// CHECK-CXX-SAME: <4 x float> noundef [[VD:%.*]], <16 x i8> [[VN:%.*]], <8 x i8> [[VM:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] {355// CHECK-CXX-NEXT: [[ENTRY:.*:]]356// CHECK-CXX-NEXT: [[TMP0:%.*]] = call <16 x i8> @llvm.vector.insert.v16i8.v8i8(<16 x i8> poison, <8 x i8> [[VM]], i64 0)357// CHECK-CXX-NEXT: call void @llvm.aarch64.set.fpmr(i64 [[FPM]])358// CHECK-CXX-NEXT: [[VMLALL_LANE:%.*]] = call <4 x float> @llvm.aarch64.neon.fp8.fmlalltt.lane.v4f32(<4 x float> [[VD]], <16 x i8> [[VN]], <16 x i8> [[TMP0]], i32 7)359// CHECK-CXX-NEXT: ret <4 x float> [[VMLALL_LANE]]360//361float32x4_t test_vmlalltt_lane(float32x4_t vd, mfloat8x16_t vn, mfloat8x8_t vm, fpm_t fpm) {362 return vmlallttq_lane_f32_mf8_fpm(vd, vn, vm, 7, fpm);363}364 365// CHECK-LABEL: define dso_local <4 x float> @test_vmlalltt_laneq(366// CHECK-SAME: <4 x float> noundef [[VD:%.*]], <16 x i8> [[VN:%.*]], <16 x i8> [[VM:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] {367// CHECK-NEXT: [[ENTRY:.*:]]368// CHECK-NEXT: call void @llvm.aarch64.set.fpmr(i64 [[FPM]])369// CHECK-NEXT: [[VMLALL_LANE:%.*]] = call <4 x float> @llvm.aarch64.neon.fp8.fmlalltt.lane.v4f32(<4 x float> [[VD]], <16 x i8> [[VN]], <16 x i8> [[VM]], i32 15)370// CHECK-NEXT: ret <4 x float> [[VMLALL_LANE]]371//372// CHECK-CXX-LABEL: define dso_local noundef <4 x float> @_Z19test_vmlalltt_laneq13__Float32x4_t14__Mfloat8x16_tS0_m(373// CHECK-CXX-SAME: <4 x float> noundef [[VD:%.*]], <16 x i8> [[VN:%.*]], <16 x i8> [[VM:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] {374// CHECK-CXX-NEXT: [[ENTRY:.*:]]375// CHECK-CXX-NEXT: call void @llvm.aarch64.set.fpmr(i64 [[FPM]])376// CHECK-CXX-NEXT: [[VMLALL_LANE:%.*]] = call <4 x float> @llvm.aarch64.neon.fp8.fmlalltt.lane.v4f32(<4 x float> [[VD]], <16 x i8> [[VN]], <16 x i8> [[VM]], i32 15)377// CHECK-CXX-NEXT: ret <4 x float> [[VMLALL_LANE]]378//379float32x4_t test_vmlalltt_laneq(float32x4_t vd, mfloat8x16_t vn, mfloat8x16_t vm, fpm_t fpm) {380 return vmlallttq_laneq_f32_mf8_fpm(vd, vn, vm, 15, fpm);381}382