453 lines · c
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature2// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \3// RUN: -disable-O0-optnone -emit-llvm -o - %s | opt -S -passes=mem2reg | FileCheck %s4 5// REQUIRES: aarch64-registered-target || arm-registered-target6 7#include <arm_neon.h>8 9// CHECK-LABEL: define {{[^@]+}}@test_vaddlv_s810// CHECK-SAME: (<8 x i8> noundef [[A:%.*]]) #[[ATTR0:[0-9]+]] {11// CHECK-NEXT: entry:12// CHECK-NEXT: [[VADDLV_I:%.*]] = call i32 @llvm.aarch64.neon.saddlv.i32.v8i8(<8 x i8> [[A]])13// CHECK-NEXT: [[TMP0:%.*]] = trunc i32 [[VADDLV_I]] to i1614// CHECK-NEXT: ret i16 [[TMP0]]15//16int16_t test_vaddlv_s8(int8x8_t a) {17 return vaddlv_s8(a);18}19 20// CHECK-LABEL: define {{[^@]+}}@test_vaddlv_s1621// CHECK-SAME: (<4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {22// CHECK-NEXT: entry:23// CHECK-NEXT: [[VADDLV_I:%.*]] = call i32 @llvm.aarch64.neon.saddlv.i32.v4i16(<4 x i16> [[A]])24// CHECK-NEXT: ret i32 [[VADDLV_I]]25//26int32_t test_vaddlv_s16(int16x4_t a) {27 return vaddlv_s16(a);28}29 30// CHECK-LABEL: define {{[^@]+}}@test_vaddlv_u831// CHECK-SAME: (<8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {32// CHECK-NEXT: entry:33// CHECK-NEXT: [[VADDLV_I:%.*]] = call i32 @llvm.aarch64.neon.uaddlv.i32.v8i8(<8 x i8> [[A]])34// CHECK-NEXT: [[TMP0:%.*]] = trunc i32 [[VADDLV_I]] to i1635// CHECK-NEXT: ret i16 [[TMP0]]36//37uint16_t test_vaddlv_u8(uint8x8_t a) {38 return vaddlv_u8(a);39}40 41// CHECK-LABEL: define {{[^@]+}}@test_vaddlv_u1642// CHECK-SAME: (<4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {43// CHECK-NEXT: entry:44// CHECK-NEXT: [[VADDLV_I:%.*]] = call i32 @llvm.aarch64.neon.uaddlv.i32.v4i16(<4 x i16> [[A]])45// CHECK-NEXT: ret i32 [[VADDLV_I]]46//47uint32_t test_vaddlv_u16(uint16x4_t a) {48 return vaddlv_u16(a);49}50 51// CHECK-LABEL: define {{[^@]+}}@test_vaddlvq_s852// CHECK-SAME: (<16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {53// CHECK-NEXT: entry:54// CHECK-NEXT: [[VADDLV_I:%.*]] = call i32 @llvm.aarch64.neon.saddlv.i32.v16i8(<16 x i8> [[A]])55// CHECK-NEXT: [[TMP0:%.*]] = trunc i32 [[VADDLV_I]] to i1656// CHECK-NEXT: ret i16 [[TMP0]]57//58int16_t test_vaddlvq_s8(int8x16_t a) {59 return vaddlvq_s8(a);60}61 62// CHECK-LABEL: define {{[^@]+}}@test_vaddlvq_s1663// CHECK-SAME: (<8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {64// CHECK-NEXT: entry:65// CHECK-NEXT: [[VADDLV_I:%.*]] = call i32 @llvm.aarch64.neon.saddlv.i32.v8i16(<8 x i16> [[A]])66// CHECK-NEXT: ret i32 [[VADDLV_I]]67//68int32_t test_vaddlvq_s16(int16x8_t a) {69 return vaddlvq_s16(a);70}71 72// CHECK-LABEL: define {{[^@]+}}@test_vaddlvq_s3273// CHECK-SAME: (<4 x i32> noundef [[A:%.*]]) #[[ATTR0]] {74// CHECK-NEXT: entry:75// CHECK-NEXT: [[VADDLVQ_S32_I:%.*]] = call i64 @llvm.aarch64.neon.saddlv.i64.v4i32(<4 x i32> [[A]])76// CHECK-NEXT: ret i64 [[VADDLVQ_S32_I]]77//78int64_t test_vaddlvq_s32(int32x4_t a) {79 return vaddlvq_s32(a);80}81 82// CHECK-LABEL: define {{[^@]+}}@test_vaddlvq_u883// CHECK-SAME: (<16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {84// CHECK-NEXT: entry:85// CHECK-NEXT: [[VADDLV_I:%.*]] = call i32 @llvm.aarch64.neon.uaddlv.i32.v16i8(<16 x i8> [[A]])86// CHECK-NEXT: [[TMP0:%.*]] = trunc i32 [[VADDLV_I]] to i1687// CHECK-NEXT: ret i16 [[TMP0]]88//89uint16_t test_vaddlvq_u8(uint8x16_t a) {90 return vaddlvq_u8(a);91}92 93// CHECK-LABEL: define {{[^@]+}}@test_vaddlvq_u1694// CHECK-SAME: (<8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {95// CHECK-NEXT: entry:96// CHECK-NEXT: [[VADDLV_I:%.*]] = call i32 @llvm.aarch64.neon.uaddlv.i32.v8i16(<8 x i16> [[A]])97// CHECK-NEXT: ret i32 [[VADDLV_I]]98//99uint32_t test_vaddlvq_u16(uint16x8_t a) {100 return vaddlvq_u16(a);101}102 103// CHECK-LABEL: define {{[^@]+}}@test_vaddlvq_u32104// CHECK-SAME: (<4 x i32> noundef [[A:%.*]]) #[[ATTR0]] {105// CHECK-NEXT: entry:106// CHECK-NEXT: [[VADDLVQ_U32_I:%.*]] = call i64 @llvm.aarch64.neon.uaddlv.i64.v4i32(<4 x i32> [[A]])107// CHECK-NEXT: ret i64 [[VADDLVQ_U32_I]]108//109uint64_t test_vaddlvq_u32(uint32x4_t a) {110 return vaddlvq_u32(a);111}112 113// CHECK-LABEL: define {{[^@]+}}@test_vmaxv_s8114// CHECK-SAME: (<8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {115// CHECK-NEXT: entry:116// CHECK-NEXT: [[VMAXV_S8_I:%.*]] = call i8 @llvm.vector.reduce.smax.v8i8(<8 x i8> [[A]])117// CHECK-NEXT: ret i8 [[VMAXV_S8_I]]118//119int8_t test_vmaxv_s8(int8x8_t a) {120 return vmaxv_s8(a);121}122 123// CHECK-LABEL: define {{[^@]+}}@test_vmaxv_s16124// CHECK-SAME: (<4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {125// CHECK-NEXT: entry:126// CHECK-NEXT: [[VMAXV_S16_I:%.*]] = call i16 @llvm.vector.reduce.smax.v4i16(<4 x i16> [[A]])127// CHECK-NEXT: ret i16 [[VMAXV_S16_I]]128//129int16_t test_vmaxv_s16(int16x4_t a) {130 return vmaxv_s16(a);131}132 133// CHECK-LABEL: define {{[^@]+}}@test_vmaxv_u8134// CHECK-SAME: (<8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {135// CHECK-NEXT: entry:136// CHECK-NEXT: [[VMAXV_U8_I:%.*]] = call i8 @llvm.vector.reduce.umax.v8i8(<8 x i8> [[A]])137// CHECK-NEXT: ret i8 [[VMAXV_U8_I]]138//139uint8_t test_vmaxv_u8(uint8x8_t a) {140 return vmaxv_u8(a);141}142 143// CHECK-LABEL: define {{[^@]+}}@test_vmaxv_u16144// CHECK-SAME: (<4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {145// CHECK-NEXT: entry:146// CHECK-NEXT: [[VMAXV_U16_I:%.*]] = call i16 @llvm.vector.reduce.umax.v4i16(<4 x i16> [[A]])147// CHECK-NEXT: ret i16 [[VMAXV_U16_I]]148//149uint16_t test_vmaxv_u16(uint16x4_t a) {150 return vmaxv_u16(a);151}152 153// CHECK-LABEL: define {{[^@]+}}@test_vmaxvq_s8154// CHECK-SAME: (<16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {155// CHECK-NEXT: entry:156// CHECK-NEXT: [[VMAXVQ_S8_I:%.*]] = call i8 @llvm.vector.reduce.smax.v16i8(<16 x i8> [[A]])157// CHECK-NEXT: ret i8 [[VMAXVQ_S8_I]]158//159int8_t test_vmaxvq_s8(int8x16_t a) {160 return vmaxvq_s8(a);161}162 163// CHECK-LABEL: define {{[^@]+}}@test_vmaxvq_s16164// CHECK-SAME: (<8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {165// CHECK-NEXT: entry:166// CHECK-NEXT: [[VMAXVQ_S16_I:%.*]] = call i16 @llvm.vector.reduce.smax.v8i16(<8 x i16> [[A]])167// CHECK-NEXT: ret i16 [[VMAXVQ_S16_I]]168//169int16_t test_vmaxvq_s16(int16x8_t a) {170 return vmaxvq_s16(a);171}172 173// CHECK-LABEL: define {{[^@]+}}@test_vmaxvq_s32174// CHECK-SAME: (<4 x i32> noundef [[A:%.*]]) #[[ATTR0]] {175// CHECK-NEXT: entry:176// CHECK-NEXT: [[VMAXVQ_S32_I:%.*]] = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> [[A]])177// CHECK-NEXT: ret i32 [[VMAXVQ_S32_I]]178//179int32_t test_vmaxvq_s32(int32x4_t a) {180 return vmaxvq_s32(a);181}182 183// CHECK-LABEL: define {{[^@]+}}@test_vmaxvq_u8184// CHECK-SAME: (<16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {185// CHECK-NEXT: entry:186// CHECK-NEXT: [[VMAXVQ_U8_I:%.*]] = call i8 @llvm.vector.reduce.umax.v16i8(<16 x i8> [[A]])187// CHECK-NEXT: ret i8 [[VMAXVQ_U8_I]]188//189uint8_t test_vmaxvq_u8(uint8x16_t a) {190 return vmaxvq_u8(a);191}192 193// CHECK-LABEL: define {{[^@]+}}@test_vmaxvq_u16194// CHECK-SAME: (<8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {195// CHECK-NEXT: entry:196// CHECK-NEXT: [[VMAXVQ_U16_I:%.*]] = call i16 @llvm.vector.reduce.umax.v8i16(<8 x i16> [[A]])197// CHECK-NEXT: ret i16 [[VMAXVQ_U16_I]]198//199uint16_t test_vmaxvq_u16(uint16x8_t a) {200 return vmaxvq_u16(a);201}202 203// CHECK-LABEL: define {{[^@]+}}@test_vmaxvq_u32204// CHECK-SAME: (<4 x i32> noundef [[A:%.*]]) #[[ATTR0]] {205// CHECK-NEXT: entry:206// CHECK-NEXT: [[VMAXVQ_U32_I:%.*]] = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> [[A]])207// CHECK-NEXT: ret i32 [[VMAXVQ_U32_I]]208//209uint32_t test_vmaxvq_u32(uint32x4_t a) {210 return vmaxvq_u32(a);211}212 213// CHECK-LABEL: define {{[^@]+}}@test_vminv_s8214// CHECK-SAME: (<8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {215// CHECK-NEXT: entry:216// CHECK-NEXT: [[VMINV_S8_I:%.*]] = call i8 @llvm.vector.reduce.smin.v8i8(<8 x i8> [[A]])217// CHECK-NEXT: ret i8 [[VMINV_S8_I]]218//219int8_t test_vminv_s8(int8x8_t a) {220 return vminv_s8(a);221}222 223// CHECK-LABEL: define {{[^@]+}}@test_vminv_s16224// CHECK-SAME: (<4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {225// CHECK-NEXT: entry:226// CHECK-NEXT: [[VMINV_S16_I:%.*]] = call i16 @llvm.vector.reduce.smin.v4i16(<4 x i16> [[A]])227// CHECK-NEXT: ret i16 [[VMINV_S16_I]]228//229int16_t test_vminv_s16(int16x4_t a) {230 return vminv_s16(a);231}232 233// CHECK-LABEL: define {{[^@]+}}@test_vminv_u8234// CHECK-SAME: (<8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {235// CHECK-NEXT: entry:236// CHECK-NEXT: [[VMINV_U8_I:%.*]] = call i8 @llvm.vector.reduce.umin.v8i8(<8 x i8> [[A]])237// CHECK-NEXT: ret i8 [[VMINV_U8_I]]238//239uint8_t test_vminv_u8(uint8x8_t a) {240 return vminv_u8(a);241}242 243// CHECK-LABEL: define {{[^@]+}}@test_vminv_u16244// CHECK-SAME: (<4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {245// CHECK-NEXT: entry:246// CHECK-NEXT: [[VMINV_U16_I:%.*]] = call i16 @llvm.vector.reduce.umin.v4i16(<4 x i16> [[A]])247// CHECK-NEXT: ret i16 [[VMINV_U16_I]]248//249uint16_t test_vminv_u16(uint16x4_t a) {250 return vminv_u16(a);251}252 253// CHECK-LABEL: define {{[^@]+}}@test_vminvq_s8254// CHECK-SAME: (<16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {255// CHECK-NEXT: entry:256// CHECK-NEXT: [[VMINVQ_S8_I:%.*]] = call i8 @llvm.vector.reduce.smin.v16i8(<16 x i8> [[A]])257// CHECK-NEXT: ret i8 [[VMINVQ_S8_I]]258//259int8_t test_vminvq_s8(int8x16_t a) {260 return vminvq_s8(a);261}262 263// CHECK-LABEL: define {{[^@]+}}@test_vminvq_s16264// CHECK-SAME: (<8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {265// CHECK-NEXT: entry:266// CHECK-NEXT: [[VMINVQ_S16_I:%.*]] = call i16 @llvm.vector.reduce.smin.v8i16(<8 x i16> [[A]])267// CHECK-NEXT: ret i16 [[VMINVQ_S16_I]]268//269int16_t test_vminvq_s16(int16x8_t a) {270 return vminvq_s16(a);271}272 273// CHECK-LABEL: define {{[^@]+}}@test_vminvq_s32274// CHECK-SAME: (<4 x i32> noundef [[A:%.*]]) #[[ATTR0]] {275// CHECK-NEXT: entry:276// CHECK-NEXT: [[VMINVQ_S32_I:%.*]] = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> [[A]])277// CHECK-NEXT: ret i32 [[VMINVQ_S32_I]]278//279int32_t test_vminvq_s32(int32x4_t a) {280 return vminvq_s32(a);281}282 283// CHECK-LABEL: define {{[^@]+}}@test_vminvq_u8284// CHECK-SAME: (<16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {285// CHECK-NEXT: entry:286// CHECK-NEXT: [[VMINVQ_U8_I:%.*]] = call i8 @llvm.vector.reduce.umin.v16i8(<16 x i8> [[A]])287// CHECK-NEXT: ret i8 [[VMINVQ_U8_I]]288//289uint8_t test_vminvq_u8(uint8x16_t a) {290 return vminvq_u8(a);291}292 293// CHECK-LABEL: define {{[^@]+}}@test_vminvq_u16294// CHECK-SAME: (<8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {295// CHECK-NEXT: entry:296// CHECK-NEXT: [[VMINVQ_U16_I:%.*]] = call i16 @llvm.vector.reduce.umin.v8i16(<8 x i16> [[A]])297// CHECK-NEXT: ret i16 [[VMINVQ_U16_I]]298//299uint16_t test_vminvq_u16(uint16x8_t a) {300 return vminvq_u16(a);301}302 303// CHECK-LABEL: define {{[^@]+}}@test_vminvq_u32304// CHECK-SAME: (<4 x i32> noundef [[A:%.*]]) #[[ATTR0]] {305// CHECK-NEXT: entry:306// CHECK-NEXT: [[VMINVQ_U32_I:%.*]] = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> [[A]])307// CHECK-NEXT: ret i32 [[VMINVQ_U32_I]]308//309uint32_t test_vminvq_u32(uint32x4_t a) {310 return vminvq_u32(a);311}312 313// CHECK-LABEL: define {{[^@]+}}@test_vaddv_s8314// CHECK-SAME: (<8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {315// CHECK-NEXT: entry:316// CHECK-NEXT: [[VADDV_S8_I:%.*]] = call i8 @llvm.vector.reduce.add.v8i8(<8 x i8> [[A]])317// CHECK-NEXT: ret i8 [[VADDV_S8_I]]318//319int8_t test_vaddv_s8(int8x8_t a) {320 return vaddv_s8(a);321}322 323// CHECK-LABEL: define {{[^@]+}}@test_vaddv_s16324// CHECK-SAME: (<4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {325// CHECK-NEXT: entry:326// CHECK-NEXT: [[VADDV_S16_I:%.*]] = call i16 @llvm.vector.reduce.add.v4i16(<4 x i16> [[A]])327// CHECK-NEXT: ret i16 [[VADDV_S16_I]]328//329int16_t test_vaddv_s16(int16x4_t a) {330 return vaddv_s16(a);331}332 333// CHECK-LABEL: define {{[^@]+}}@test_vaddv_u8334// CHECK-SAME: (<8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {335// CHECK-NEXT: entry:336// CHECK-NEXT: [[VADDV_U8_I:%.*]] = call i8 @llvm.vector.reduce.add.v8i8(<8 x i8> [[A]])337// CHECK-NEXT: ret i8 [[VADDV_U8_I]]338//339uint8_t test_vaddv_u8(uint8x8_t a) {340 return vaddv_u8(a);341}342 343// CHECK-LABEL: define {{[^@]+}}@test_vaddv_u16344// CHECK-SAME: (<4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {345// CHECK-NEXT: entry:346// CHECK-NEXT: [[VADDV_U16_I:%.*]] = call i16 @llvm.vector.reduce.add.v4i16(<4 x i16> [[A]])347// CHECK-NEXT: ret i16 [[VADDV_U16_I]]348//349uint16_t test_vaddv_u16(uint16x4_t a) {350 return vaddv_u16(a);351}352 353// CHECK-LABEL: define {{[^@]+}}@test_vaddvq_s8354// CHECK-SAME: (<16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {355// CHECK-NEXT: entry:356// CHECK-NEXT: [[VADDVQ_S8_I:%.*]] = call i8 @llvm.vector.reduce.add.v16i8(<16 x i8> [[A]])357// CHECK-NEXT: ret i8 [[VADDVQ_S8_I]]358//359int8_t test_vaddvq_s8(int8x16_t a) {360 return vaddvq_s8(a);361}362 363// CHECK-LABEL: define {{[^@]+}}@test_vaddvq_s16364// CHECK-SAME: (<8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {365// CHECK-NEXT: entry:366// CHECK-NEXT: [[VADDVQ_S16_I:%.*]] = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> [[A]])367// CHECK-NEXT: ret i16 [[VADDVQ_S16_I]]368//369int16_t test_vaddvq_s16(int16x8_t a) {370 return vaddvq_s16(a);371}372 373// CHECK-LABEL: define {{[^@]+}}@test_vaddvq_s32374// CHECK-SAME: (<4 x i32> noundef [[A:%.*]]) #[[ATTR0]] {375// CHECK-NEXT: entry:376// CHECK-NEXT: [[VADDVQ_S32_I:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[A]])377// CHECK-NEXT: ret i32 [[VADDVQ_S32_I]]378//379int32_t test_vaddvq_s32(int32x4_t a) {380 return vaddvq_s32(a);381}382 383// CHECK-LABEL: define {{[^@]+}}@test_vaddvq_u8384// CHECK-SAME: (<16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {385// CHECK-NEXT: entry:386// CHECK-NEXT: [[VADDVQ_U8_I:%.*]] = call i8 @llvm.vector.reduce.add.v16i8(<16 x i8> [[A]])387// CHECK-NEXT: ret i8 [[VADDVQ_U8_I]]388//389uint8_t test_vaddvq_u8(uint8x16_t a) {390 return vaddvq_u8(a);391}392 393// CHECK-LABEL: define {{[^@]+}}@test_vaddvq_u16394// CHECK-SAME: (<8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {395// CHECK-NEXT: entry:396// CHECK-NEXT: [[VADDVQ_U16_I:%.*]] = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> [[A]])397// CHECK-NEXT: ret i16 [[VADDVQ_U16_I]]398//399uint16_t test_vaddvq_u16(uint16x8_t a) {400 return vaddvq_u16(a);401}402 403// CHECK-LABEL: define {{[^@]+}}@test_vaddvq_u32404// CHECK-SAME: (<4 x i32> noundef [[A:%.*]]) #[[ATTR0]] {405// CHECK-NEXT: entry:406// CHECK-NEXT: [[VADDVQ_U32_I:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[A]])407// CHECK-NEXT: ret i32 [[VADDVQ_U32_I]]408//409uint32_t test_vaddvq_u32(uint32x4_t a) {410 return vaddvq_u32(a);411}412 413// CHECK-LABEL: define {{[^@]+}}@test_vmaxvq_f32414// CHECK-SAME: (<4 x float> noundef [[A:%.*]]) #[[ATTR0]] {415// CHECK-NEXT: entry:416// CHECK-NEXT: [[VMAXVQ_F32_I:%.*]] = call float @llvm.aarch64.neon.fmaxv.f32.v4f32(<4 x float> [[A]])417// CHECK-NEXT: ret float [[VMAXVQ_F32_I]]418//419float32_t test_vmaxvq_f32(float32x4_t a) {420 return vmaxvq_f32(a);421}422 423// CHECK-LABEL: define {{[^@]+}}@test_vminvq_f32424// CHECK-SAME: (<4 x float> noundef [[A:%.*]]) #[[ATTR0]] {425// CHECK-NEXT: entry:426// CHECK-NEXT: [[VMINVQ_F32_I:%.*]] = call float @llvm.aarch64.neon.fminv.f32.v4f32(<4 x float> [[A]])427// CHECK-NEXT: ret float [[VMINVQ_F32_I]]428//429float32_t test_vminvq_f32(float32x4_t a) {430 return vminvq_f32(a);431}432 433// CHECK-LABEL: define {{[^@]+}}@test_vmaxnmvq_f32434// CHECK-SAME: (<4 x float> noundef [[A:%.*]]) #[[ATTR0]] {435// CHECK-NEXT: entry:436// CHECK-NEXT: [[VMAXNMVQ_F32_I:%.*]] = call float @llvm.aarch64.neon.fmaxnmv.f32.v4f32(<4 x float> [[A]])437// CHECK-NEXT: ret float [[VMAXNMVQ_F32_I]]438//439float32_t test_vmaxnmvq_f32(float32x4_t a) {440 return vmaxnmvq_f32(a);441}442 443// CHECK-LABEL: define {{[^@]+}}@test_vminnmvq_f32444// CHECK-SAME: (<4 x float> noundef [[A:%.*]]) #[[ATTR0]] {445// CHECK-NEXT: entry:446// CHECK-NEXT: [[VMINNMVQ_F32_I:%.*]] = call float @llvm.aarch64.neon.fminnmv.f32.v4f32(<4 x float> [[A]])447// CHECK-NEXT: ret float [[VMINNMVQ_F32_I]]448//449float32_t test_vminnmvq_f32(float32x4_t a) {450 return vminnmvq_f32(a);451}452 453