346 lines · c
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature2// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - %s | opt -S -passes=mem2reg,sroa | FileCheck %s3 4// REQUIRES: aarch64-registered-target || arm-registered-target5 6#include <arm_neon.h>7 8// CHECK-LABEL: define {{[^@]+}}@test_vmla_n_f329// CHECK-SAME: (<2 x float> noundef [[A:%.*]], <2 x float> noundef [[B:%.*]], float noundef [[C:%.*]]) #[[ATTR0:[0-9]+]] {10// CHECK-NEXT: entry:11// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x float> poison, float [[C]], i32 012// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <2 x float> [[VECINIT_I]], float [[C]], i32 113// CHECK-NEXT: [[MUL_I:%.*]] = fmul <2 x float> [[B]], [[VECINIT1_I]]14// CHECK-NEXT: [[ADD_I:%.*]] = fadd <2 x float> [[A]], [[MUL_I]]15// CHECK-NEXT: ret <2 x float> [[ADD_I]]16//17float32x2_t test_vmla_n_f32(float32x2_t a, float32x2_t b, float32_t c) {18 return vmla_n_f32(a, b, c);19}20 21// CHECK-LABEL: define {{[^@]+}}@test_vmlaq_n_f3222// CHECK-SAME: (<4 x float> noundef [[A:%.*]], <4 x float> noundef [[B:%.*]], float noundef [[C:%.*]]) #[[ATTR0]] {23// CHECK-NEXT: entry:24// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x float> poison, float [[C]], i32 025// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x float> [[VECINIT_I]], float [[C]], i32 126// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x float> [[VECINIT1_I]], float [[C]], i32 227// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x float> [[VECINIT2_I]], float [[C]], i32 328// CHECK-NEXT: [[MUL_I:%.*]] = fmul <4 x float> [[B]], [[VECINIT3_I]]29// CHECK-NEXT: [[ADD_I:%.*]] = fadd <4 x float> [[A]], [[MUL_I]]30// CHECK-NEXT: ret <4 x float> [[ADD_I]]31//32float32x4_t test_vmlaq_n_f32(float32x4_t a, float32x4_t b, float32_t c) {33 return vmlaq_n_f32(a, b, c);34}35 36// CHECK-LABEL: define {{[^@]+}}@test_vmlsq_n_f3237// CHECK-SAME: (<4 x float> noundef [[A:%.*]], <4 x float> noundef [[B:%.*]], float noundef [[C:%.*]]) #[[ATTR0]] {38// CHECK-NEXT: entry:39// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x float> poison, float [[C]], i32 040// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x float> [[VECINIT_I]], float [[C]], i32 141// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x float> [[VECINIT1_I]], float [[C]], i32 242// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x float> [[VECINIT2_I]], float [[C]], i32 343// CHECK-NEXT: [[MUL_I:%.*]] = fmul <4 x float> [[B]], [[VECINIT3_I]]44// CHECK-NEXT: [[SUB_I:%.*]] = fsub <4 x float> [[A]], [[MUL_I]]45// CHECK-NEXT: ret <4 x float> [[SUB_I]]46//47float32x4_t test_vmlsq_n_f32(float32x4_t a, float32x4_t b, float32_t c) {48 return vmlsq_n_f32(a, b, c);49}50 51// CHECK-LABEL: define {{[^@]+}}@test_vmls_n_f3252// CHECK-SAME: (<2 x float> noundef [[A:%.*]], <2 x float> noundef [[B:%.*]], float noundef [[C:%.*]]) #[[ATTR0]] {53// CHECK-NEXT: entry:54// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x float> poison, float [[C]], i32 055// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <2 x float> [[VECINIT_I]], float [[C]], i32 156// CHECK-NEXT: [[MUL_I:%.*]] = fmul <2 x float> [[B]], [[VECINIT1_I]]57// CHECK-NEXT: [[SUB_I:%.*]] = fsub <2 x float> [[A]], [[MUL_I]]58// CHECK-NEXT: ret <2 x float> [[SUB_I]]59//60float32x2_t test_vmls_n_f32(float32x2_t a, float32x2_t b, float32_t c) {61 return vmls_n_f32(a, b, c);62}63 64// CHECK-LABEL: define {{[^@]+}}@test_vmla_lane_f32_065// CHECK-SAME: (<2 x float> noundef [[A:%.*]], <2 x float> noundef [[B:%.*]], <2 x float> noundef [[V:%.*]]) #[[ATTR0]] {66// CHECK-NEXT: entry:67// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[V]] to <2 x i32>68// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>69// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float>70// CHECK-NEXT: [[LANE:%.*]] = shufflevector <2 x float> [[TMP2]], <2 x float> [[TMP2]], <2 x i32> zeroinitializer71// CHECK-NEXT: [[MUL:%.*]] = fmul <2 x float> [[B]], [[LANE]]72// CHECK-NEXT: [[ADD:%.*]] = fadd <2 x float> [[A]], [[MUL]]73// CHECK-NEXT: ret <2 x float> [[ADD]]74//75float32x2_t test_vmla_lane_f32_0(float32x2_t a, float32x2_t b, float32x2_t v) {76 return vmla_lane_f32(a, b, v, 0);77}78 79// CHECK-LABEL: define {{[^@]+}}@test_vmlaq_lane_f32_080// CHECK-SAME: (<4 x float> noundef [[A:%.*]], <4 x float> noundef [[B:%.*]], <2 x float> noundef [[V:%.*]]) #[[ATTR0]] {81// CHECK-NEXT: entry:82// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[V]] to <2 x i32>83// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>84// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float>85// CHECK-NEXT: [[LANE:%.*]] = shufflevector <2 x float> [[TMP2]], <2 x float> [[TMP2]], <4 x i32> zeroinitializer86// CHECK-NEXT: [[MUL:%.*]] = fmul <4 x float> [[B]], [[LANE]]87// CHECK-NEXT: [[ADD:%.*]] = fadd <4 x float> [[A]], [[MUL]]88// CHECK-NEXT: ret <4 x float> [[ADD]]89//90float32x4_t test_vmlaq_lane_f32_0(float32x4_t a, float32x4_t b, float32x2_t v) {91 return vmlaq_lane_f32(a, b, v, 0);92}93 94// CHECK-LABEL: define {{[^@]+}}@test_vmla_laneq_f32_095// CHECK-SAME: (<2 x float> noundef [[A:%.*]], <2 x float> noundef [[B:%.*]], <4 x float> noundef [[V:%.*]]) #[[ATTR0]] {96// CHECK-NEXT: entry:97// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[V]] to <4 x i32>98// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>99// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float>100// CHECK-NEXT: [[LANE:%.*]] = shufflevector <4 x float> [[TMP2]], <4 x float> [[TMP2]], <2 x i32> zeroinitializer101// CHECK-NEXT: [[MUL:%.*]] = fmul <2 x float> [[B]], [[LANE]]102// CHECK-NEXT: [[ADD:%.*]] = fadd <2 x float> [[A]], [[MUL]]103// CHECK-NEXT: ret <2 x float> [[ADD]]104//105float32x2_t test_vmla_laneq_f32_0(float32x2_t a, float32x2_t b, float32x4_t v) {106 return vmla_laneq_f32(a, b, v, 0);107}108 109// CHECK-LABEL: define {{[^@]+}}@test_vmlaq_laneq_f32_0110// CHECK-SAME: (<4 x float> noundef [[A:%.*]], <4 x float> noundef [[B:%.*]], <4 x float> noundef [[V:%.*]]) #[[ATTR0]] {111// CHECK-NEXT: entry:112// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[V]] to <4 x i32>113// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>114// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float>115// CHECK-NEXT: [[LANE:%.*]] = shufflevector <4 x float> [[TMP2]], <4 x float> [[TMP2]], <4 x i32> zeroinitializer116// CHECK-NEXT: [[MUL:%.*]] = fmul <4 x float> [[B]], [[LANE]]117// CHECK-NEXT: [[ADD:%.*]] = fadd <4 x float> [[A]], [[MUL]]118// CHECK-NEXT: ret <4 x float> [[ADD]]119//120float32x4_t test_vmlaq_laneq_f32_0(float32x4_t a, float32x4_t b, float32x4_t v) {121 return vmlaq_laneq_f32(a, b, v, 0);122}123 124// CHECK-LABEL: define {{[^@]+}}@test_vmls_lane_f32_0125// CHECK-SAME: (<2 x float> noundef [[A:%.*]], <2 x float> noundef [[B:%.*]], <2 x float> noundef [[V:%.*]]) #[[ATTR0]] {126// CHECK-NEXT: entry:127// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[V]] to <2 x i32>128// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>129// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float>130// CHECK-NEXT: [[LANE:%.*]] = shufflevector <2 x float> [[TMP2]], <2 x float> [[TMP2]], <2 x i32> zeroinitializer131// CHECK-NEXT: [[MUL:%.*]] = fmul <2 x float> [[B]], [[LANE]]132// CHECK-NEXT: [[SUB:%.*]] = fsub <2 x float> [[A]], [[MUL]]133// CHECK-NEXT: ret <2 x float> [[SUB]]134//135float32x2_t test_vmls_lane_f32_0(float32x2_t a, float32x2_t b, float32x2_t v) {136 return vmls_lane_f32(a, b, v, 0);137}138 139// CHECK-LABEL: define {{[^@]+}}@test_vmlsq_lane_f32_0140// CHECK-SAME: (<4 x float> noundef [[A:%.*]], <4 x float> noundef [[B:%.*]], <2 x float> noundef [[V:%.*]]) #[[ATTR0]] {141// CHECK-NEXT: entry:142// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[V]] to <2 x i32>143// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>144// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float>145// CHECK-NEXT: [[LANE:%.*]] = shufflevector <2 x float> [[TMP2]], <2 x float> [[TMP2]], <4 x i32> zeroinitializer146// CHECK-NEXT: [[MUL:%.*]] = fmul <4 x float> [[B]], [[LANE]]147// CHECK-NEXT: [[SUB:%.*]] = fsub <4 x float> [[A]], [[MUL]]148// CHECK-NEXT: ret <4 x float> [[SUB]]149//150float32x4_t test_vmlsq_lane_f32_0(float32x4_t a, float32x4_t b, float32x2_t v) {151 return vmlsq_lane_f32(a, b, v, 0);152}153 154// CHECK-LABEL: define {{[^@]+}}@test_vmls_laneq_f32_0155// CHECK-SAME: (<2 x float> noundef [[A:%.*]], <2 x float> noundef [[B:%.*]], <4 x float> noundef [[V:%.*]]) #[[ATTR0]] {156// CHECK-NEXT: entry:157// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[V]] to <4 x i32>158// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>159// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float>160// CHECK-NEXT: [[LANE:%.*]] = shufflevector <4 x float> [[TMP2]], <4 x float> [[TMP2]], <2 x i32> zeroinitializer161// CHECK-NEXT: [[MUL:%.*]] = fmul <2 x float> [[B]], [[LANE]]162// CHECK-NEXT: [[SUB:%.*]] = fsub <2 x float> [[A]], [[MUL]]163// CHECK-NEXT: ret <2 x float> [[SUB]]164//165float32x2_t test_vmls_laneq_f32_0(float32x2_t a, float32x2_t b, float32x4_t v) {166 return vmls_laneq_f32(a, b, v, 0);167}168 169// CHECK-LABEL: define {{[^@]+}}@test_vmlsq_laneq_f32_0170// CHECK-SAME: (<4 x float> noundef [[A:%.*]], <4 x float> noundef [[B:%.*]], <4 x float> noundef [[V:%.*]]) #[[ATTR0]] {171// CHECK-NEXT: entry:172// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[V]] to <4 x i32>173// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>174// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float>175// CHECK-NEXT: [[LANE:%.*]] = shufflevector <4 x float> [[TMP2]], <4 x float> [[TMP2]], <4 x i32> zeroinitializer176// CHECK-NEXT: [[MUL:%.*]] = fmul <4 x float> [[B]], [[LANE]]177// CHECK-NEXT: [[SUB:%.*]] = fsub <4 x float> [[A]], [[MUL]]178// CHECK-NEXT: ret <4 x float> [[SUB]]179//180float32x4_t test_vmlsq_laneq_f32_0(float32x4_t a, float32x4_t b, float32x4_t v) {181 return vmlsq_laneq_f32(a, b, v, 0);182}183 184// CHECK-LABEL: define {{[^@]+}}@test_vmla_lane_f32185// CHECK-SAME: (<2 x float> noundef [[A:%.*]], <2 x float> noundef [[B:%.*]], <2 x float> noundef [[V:%.*]]) #[[ATTR0]] {186// CHECK-NEXT: entry:187// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[V]] to <2 x i32>188// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>189// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float>190// CHECK-NEXT: [[LANE:%.*]] = shufflevector <2 x float> [[TMP2]], <2 x float> [[TMP2]], <2 x i32> <i32 1, i32 1>191// CHECK-NEXT: [[MUL:%.*]] = fmul <2 x float> [[B]], [[LANE]]192// CHECK-NEXT: [[ADD:%.*]] = fadd <2 x float> [[A]], [[MUL]]193// CHECK-NEXT: ret <2 x float> [[ADD]]194//195float32x2_t test_vmla_lane_f32(float32x2_t a, float32x2_t b, float32x2_t v) {196 return vmla_lane_f32(a, b, v, 1);197}198 199// CHECK-LABEL: define {{[^@]+}}@test_vmlaq_lane_f32200// CHECK-SAME: (<4 x float> noundef [[A:%.*]], <4 x float> noundef [[B:%.*]], <2 x float> noundef [[V:%.*]]) #[[ATTR0]] {201// CHECK-NEXT: entry:202// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[V]] to <2 x i32>203// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>204// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float>205// CHECK-NEXT: [[LANE:%.*]] = shufflevector <2 x float> [[TMP2]], <2 x float> [[TMP2]], <4 x i32> <i32 1, i32 1, i32 1, i32 1>206// CHECK-NEXT: [[MUL:%.*]] = fmul <4 x float> [[B]], [[LANE]]207// CHECK-NEXT: [[ADD:%.*]] = fadd <4 x float> [[A]], [[MUL]]208// CHECK-NEXT: ret <4 x float> [[ADD]]209//210float32x4_t test_vmlaq_lane_f32(float32x4_t a, float32x4_t b, float32x2_t v) {211 return vmlaq_lane_f32(a, b, v, 1);212}213 214// CHECK-LABEL: define {{[^@]+}}@test_vmla_laneq_f32215// CHECK-SAME: (<2 x float> noundef [[A:%.*]], <2 x float> noundef [[B:%.*]], <4 x float> noundef [[V:%.*]]) #[[ATTR0]] {216// CHECK-NEXT: entry:217// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[V]] to <4 x i32>218// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>219// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float>220// CHECK-NEXT: [[LANE:%.*]] = shufflevector <4 x float> [[TMP2]], <4 x float> [[TMP2]], <2 x i32> <i32 3, i32 3>221// CHECK-NEXT: [[MUL:%.*]] = fmul <2 x float> [[B]], [[LANE]]222// CHECK-NEXT: [[ADD:%.*]] = fadd <2 x float> [[A]], [[MUL]]223// CHECK-NEXT: ret <2 x float> [[ADD]]224//225float32x2_t test_vmla_laneq_f32(float32x2_t a, float32x2_t b, float32x4_t v) {226 return vmla_laneq_f32(a, b, v, 3);227}228 229// CHECK-LABEL: define {{[^@]+}}@test_vmlaq_laneq_f32230// CHECK-SAME: (<4 x float> noundef [[A:%.*]], <4 x float> noundef [[B:%.*]], <4 x float> noundef [[V:%.*]]) #[[ATTR0]] {231// CHECK-NEXT: entry:232// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[V]] to <4 x i32>233// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>234// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float>235// CHECK-NEXT: [[LANE:%.*]] = shufflevector <4 x float> [[TMP2]], <4 x float> [[TMP2]], <4 x i32> <i32 3, i32 3, i32 3, i32 3>236// CHECK-NEXT: [[MUL:%.*]] = fmul <4 x float> [[B]], [[LANE]]237// CHECK-NEXT: [[ADD:%.*]] = fadd <4 x float> [[A]], [[MUL]]238// CHECK-NEXT: ret <4 x float> [[ADD]]239//240float32x4_t test_vmlaq_laneq_f32(float32x4_t a, float32x4_t b, float32x4_t v) {241 return vmlaq_laneq_f32(a, b, v, 3);242}243 244// CHECK-LABEL: define {{[^@]+}}@test_vmls_lane_f32245// CHECK-SAME: (<2 x float> noundef [[A:%.*]], <2 x float> noundef [[B:%.*]], <2 x float> noundef [[V:%.*]]) #[[ATTR0]] {246// CHECK-NEXT: entry:247// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[V]] to <2 x i32>248// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>249// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float>250// CHECK-NEXT: [[LANE:%.*]] = shufflevector <2 x float> [[TMP2]], <2 x float> [[TMP2]], <2 x i32> <i32 1, i32 1>251// CHECK-NEXT: [[MUL:%.*]] = fmul <2 x float> [[B]], [[LANE]]252// CHECK-NEXT: [[SUB:%.*]] = fsub <2 x float> [[A]], [[MUL]]253// CHECK-NEXT: ret <2 x float> [[SUB]]254//255float32x2_t test_vmls_lane_f32(float32x2_t a, float32x2_t b, float32x2_t v) {256 return vmls_lane_f32(a, b, v, 1);257}258 259// CHECK-LABEL: define {{[^@]+}}@test_vmlsq_lane_f32260// CHECK-SAME: (<4 x float> noundef [[A:%.*]], <4 x float> noundef [[B:%.*]], <2 x float> noundef [[V:%.*]]) #[[ATTR0]] {261// CHECK-NEXT: entry:262// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[V]] to <2 x i32>263// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>264// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float>265// CHECK-NEXT: [[LANE:%.*]] = shufflevector <2 x float> [[TMP2]], <2 x float> [[TMP2]], <4 x i32> <i32 1, i32 1, i32 1, i32 1>266// CHECK-NEXT: [[MUL:%.*]] = fmul <4 x float> [[B]], [[LANE]]267// CHECK-NEXT: [[SUB:%.*]] = fsub <4 x float> [[A]], [[MUL]]268// CHECK-NEXT: ret <4 x float> [[SUB]]269//270float32x4_t test_vmlsq_lane_f32(float32x4_t a, float32x4_t b, float32x2_t v) {271 return vmlsq_lane_f32(a, b, v, 1);272}273// CHECK-LABEL: define {{[^@]+}}@test_vmls_laneq_f32274// CHECK-SAME: (<2 x float> noundef [[A:%.*]], <2 x float> noundef [[B:%.*]], <4 x float> noundef [[V:%.*]]) #[[ATTR0]] {275// CHECK-NEXT: entry:276// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[V]] to <4 x i32>277// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>278// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float>279// CHECK-NEXT: [[LANE:%.*]] = shufflevector <4 x float> [[TMP2]], <4 x float> [[TMP2]], <2 x i32> <i32 3, i32 3>280// CHECK-NEXT: [[MUL:%.*]] = fmul <2 x float> [[B]], [[LANE]]281// CHECK-NEXT: [[SUB:%.*]] = fsub <2 x float> [[A]], [[MUL]]282// CHECK-NEXT: ret <2 x float> [[SUB]]283//284float32x2_t test_vmls_laneq_f32(float32x2_t a, float32x2_t b, float32x4_t v) {285 return vmls_laneq_f32(a, b, v, 3);286}287 288// CHECK-LABEL: define {{[^@]+}}@test_vmlsq_laneq_f32289// CHECK-SAME: (<4 x float> noundef [[A:%.*]], <4 x float> noundef [[B:%.*]], <4 x float> noundef [[V:%.*]]) #[[ATTR0]] {290// CHECK-NEXT: entry:291// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[V]] to <4 x i32>292// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>293// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float>294// CHECK-NEXT: [[LANE:%.*]] = shufflevector <4 x float> [[TMP2]], <4 x float> [[TMP2]], <4 x i32> <i32 3, i32 3, i32 3, i32 3>295// CHECK-NEXT: [[MUL:%.*]] = fmul <4 x float> [[B]], [[LANE]]296// CHECK-NEXT: [[SUB:%.*]] = fsub <4 x float> [[A]], [[MUL]]297// CHECK-NEXT: ret <4 x float> [[SUB]]298//299float32x4_t test_vmlsq_laneq_f32(float32x4_t a, float32x4_t b, float32x4_t v) {300 return vmlsq_laneq_f32(a, b, v, 3);301}302 303// CHECK-LABEL: define {{[^@]+}}@test_vfmaq_n_f64304// CHECK-SAME: (<2 x double> noundef [[A:%.*]], <2 x double> noundef [[B:%.*]], double noundef [[C:%.*]]) #[[ATTR0]] {305// CHECK-NEXT: entry:306// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x double> poison, double [[C]], i32 0307// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <2 x double> [[VECINIT_I]], double [[C]], i32 1308// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x double> [[A]] to <2 x i64>309// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x double> [[B]] to <2 x i64>310// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x double> [[VECINIT1_I]] to <2 x i64>311// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8>312// CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i64> [[TMP1]] to <16 x i8>313// CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP2]] to <16 x i8>314// CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP3]] to <2 x double>315// CHECK-NEXT: [[TMP7:%.*]] = bitcast <16 x i8> [[TMP4]] to <2 x double>316// CHECK-NEXT: [[TMP8:%.*]] = bitcast <16 x i8> [[TMP5]] to <2 x double>317// CHECK-NEXT: [[TMP9:%.*]] = call <2 x double> @llvm.fma.v2f64(<2 x double> [[TMP7]], <2 x double> [[TMP8]], <2 x double> [[TMP6]])318// CHECK-NEXT: ret <2 x double> [[TMP9]]319//320float64x2_t test_vfmaq_n_f64(float64x2_t a, float64x2_t b, float64_t c) {321 return vfmaq_n_f64(a, b, c);322}323 324// CHECK-LABEL: define {{[^@]+}}@test_vfmsq_n_f64325// CHECK-SAME: (<2 x double> noundef [[A:%.*]], <2 x double> noundef [[B:%.*]], double noundef [[C:%.*]]) #[[ATTR0]] {326// CHECK-NEXT: entry:327// CHECK-NEXT: [[FNEG_I:%.*]] = fneg <2 x double> [[B]]328// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x double> poison, double [[C]], i32 0329// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <2 x double> [[VECINIT_I]], double [[C]], i32 1330// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x double> [[A]] to <2 x i64>331// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x double> [[FNEG_I]] to <2 x i64>332// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x double> [[VECINIT1_I]] to <2 x i64>333// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8>334// CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i64> [[TMP1]] to <16 x i8>335// CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP2]] to <16 x i8>336// CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP3]] to <2 x double>337// CHECK-NEXT: [[TMP7:%.*]] = bitcast <16 x i8> [[TMP4]] to <2 x double>338// CHECK-NEXT: [[TMP8:%.*]] = bitcast <16 x i8> [[TMP5]] to <2 x double>339// CHECK-NEXT: [[TMP9:%.*]] = call <2 x double> @llvm.fma.v2f64(<2 x double> [[TMP7]], <2 x double> [[TMP8]], <2 x double> [[TMP6]])340// CHECK-NEXT: ret <2 x double> [[TMP9]]341//342float64x2_t test_vfmsq_n_f64(float64x2_t a, float64x2_t b, float64_t c) {343 return vfmsq_n_f64(a, b, c);344}345 346