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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py2 3// REQUIRES: aarch64-registered-target4 5// RUN: %clang_cc1 -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s6// RUN: %clang_cc1 -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK7// RUN: %clang_cc1 -D__SVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s8// RUN: %clang_cc1 -D__SVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK9// RUN: %clang_cc1 -triple aarch64 -target-feature +sme -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s10 11#include <arm_sme.h>12 13#ifdef SVE_OVERLOADED_FORMS14// A simple used,unused... macro, long enough to represent any SVE builtin.15#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A316#else17#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A418#endif19 20// CHECK-LABEL: @test_cvt_f16_x2(21// CHECK-NEXT: entry:22// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.fcvt.x2.nxv4f32(<vscale x 4 x float> [[ZN_COERCE0:%.*]], <vscale x 4 x float> [[ZN_COERCE1:%.*]])23// CHECK-NEXT: ret <vscale x 8 x half> [[TMP0]]24//25// CPP-CHECK-LABEL: @_Z15test_cvt_f16_x213svfloat32x2_t(26// CPP-CHECK-NEXT: entry:27// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.fcvt.x2.nxv4f32(<vscale x 4 x float> [[ZN_COERCE0:%.*]], <vscale x 4 x float> [[ZN_COERCE1:%.*]])28// CPP-CHECK-NEXT: ret <vscale x 8 x half> [[TMP0]]29//30svfloat16_t test_cvt_f16_x2(svfloat32x2_t zn) __arm_streaming {31 return SVE_ACLE_FUNC(svcvt_f16,_f32_x2,,)(zn);32}33 34// CHECK-LABEL: @test_cvt_bf16_x2(35// CHECK-NEXT: entry:36// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x bfloat> @llvm.aarch64.sve.bfcvt.x2(<vscale x 4 x float> [[ZN_COERCE0:%.*]], <vscale x 4 x float> [[ZN_COERCE1:%.*]])37// CHECK-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]38//39// CPP-CHECK-LABEL: @_Z16test_cvt_bf16_x213svfloat32x2_t(40// CPP-CHECK-NEXT: entry:41// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x bfloat> @llvm.aarch64.sve.bfcvt.x2(<vscale x 4 x float> [[ZN_COERCE0:%.*]], <vscale x 4 x float> [[ZN_COERCE1:%.*]])42// CPP-CHECK-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]43//44svbfloat16_t test_cvt_bf16_x2(svfloat32x2_t zn) __arm_streaming {45 return SVE_ACLE_FUNC(svcvt_bf16,_f32_x2,,)(zn);46}47 48 49// x250// CHECK-LABEL: @test_svcvt_f32_u32_x2(51// CHECK-NEXT: entry:52// CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.ucvtf.x2.nxv4f32.nxv4i32(<vscale x 4 x i32> [[ZN_COERCE0:%.*]], <vscale x 4 x i32> [[ZN_COERCE1:%.*]])53// CHECK-NEXT: ret { <vscale x 4 x float>, <vscale x 4 x float> } [[TMP0]]54//55// CPP-CHECK-LABEL: @_Z21test_svcvt_f32_u32_x212svuint32x2_t(56// CPP-CHECK-NEXT: entry:57// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.ucvtf.x2.nxv4f32.nxv4i32(<vscale x 4 x i32> [[ZN_COERCE0:%.*]], <vscale x 4 x i32> [[ZN_COERCE1:%.*]])58// CPP-CHECK-NEXT: ret { <vscale x 4 x float>, <vscale x 4 x float> } [[TMP0]]59//60svfloat32x2_t test_svcvt_f32_u32_x2(svuint32x2_t zn) __arm_streaming {61 return SVE_ACLE_FUNC(svcvt_f32,_u32_x2,,)(zn);62}63 64// CHECK-LABEL: @test_svcvt_f32_s32_x2(65// CHECK-NEXT: entry:66// CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.scvtf.x2.nxv4f32.nxv4i32(<vscale x 4 x i32> [[ZN_COERCE0:%.*]], <vscale x 4 x i32> [[ZN_COERCE1:%.*]])67// CHECK-NEXT: ret { <vscale x 4 x float>, <vscale x 4 x float> } [[TMP0]]68//69// CPP-CHECK-LABEL: @_Z21test_svcvt_f32_s32_x211svint32x2_t(70// CPP-CHECK-NEXT: entry:71// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.scvtf.x2.nxv4f32.nxv4i32(<vscale x 4 x i32> [[ZN_COERCE0:%.*]], <vscale x 4 x i32> [[ZN_COERCE1:%.*]])72// CPP-CHECK-NEXT: ret { <vscale x 4 x float>, <vscale x 4 x float> } [[TMP0]]73//74svfloat32x2_t test_svcvt_f32_s32_x2(svint32x2_t zn) __arm_streaming {75 return SVE_ACLE_FUNC(svcvt_f32,_s32_x2,,)(zn);76}77 78// CHECK-LABEL: @test_svcvt_u32_f32_x2(79// CHECK-NEXT: entry:80// CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.fcvtzu.x2.nxv4i32.nxv4f32(<vscale x 4 x float> [[ZN_COERCE0:%.*]], <vscale x 4 x float> [[ZN_COERCE1:%.*]])81// CHECK-NEXT: ret { <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP0]]82//83// CPP-CHECK-LABEL: @_Z21test_svcvt_u32_f32_x213svfloat32x2_t(84// CPP-CHECK-NEXT: entry:85// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.fcvtzu.x2.nxv4i32.nxv4f32(<vscale x 4 x float> [[ZN_COERCE0:%.*]], <vscale x 4 x float> [[ZN_COERCE1:%.*]])86// CPP-CHECK-NEXT: ret { <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP0]]87//88svuint32x2_t test_svcvt_u32_f32_x2(svfloat32x2_t zn) __arm_streaming {89 return SVE_ACLE_FUNC(svcvt_u32,_f32_x2,,)(zn);90}91 92// CHECK-LABEL: @test_svcvt_s32_f32_x2(93// CHECK-NEXT: entry:94// CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.fcvtzs.x2.nxv4i32.nxv4f32(<vscale x 4 x float> [[ZN_COERCE0:%.*]], <vscale x 4 x float> [[ZN_COERCE1:%.*]])95// CHECK-NEXT: ret { <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP0]]96//97// CPP-CHECK-LABEL: @_Z21test_svcvt_s32_f32_x213svfloat32x2_t(98// CPP-CHECK-NEXT: entry:99// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.fcvtzs.x2.nxv4i32.nxv4f32(<vscale x 4 x float> [[ZN_COERCE0:%.*]], <vscale x 4 x float> [[ZN_COERCE1:%.*]])100// CPP-CHECK-NEXT: ret { <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP0]]101//102svint32x2_t test_svcvt_s32_f32_x2(svfloat32x2_t zn) __arm_streaming {103 return SVE_ACLE_FUNC(svcvt_s32,_f32_x2,,)(zn);104}105 106// x4107// CHECK-LABEL: @test_svcvt_f32_u32_x4(108// CHECK-NEXT: entry:109// CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.ucvtf.x4.nxv4f32.nxv4i32(<vscale x 4 x i32> [[ZN_COERCE0:%.*]], <vscale x 4 x i32> [[ZN_COERCE1:%.*]], <vscale x 4 x i32> [[ZN_COERCE2:%.*]], <vscale x 4 x i32> [[ZN_COERCE3:%.*]])110// CHECK-NEXT: ret { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } [[TMP0]]111//112// CPP-CHECK-LABEL: @_Z21test_svcvt_f32_u32_x412svuint32x4_t(113// CPP-CHECK-NEXT: entry:114// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.ucvtf.x4.nxv4f32.nxv4i32(<vscale x 4 x i32> [[ZN_COERCE0:%.*]], <vscale x 4 x i32> [[ZN_COERCE1:%.*]], <vscale x 4 x i32> [[ZN_COERCE2:%.*]], <vscale x 4 x i32> [[ZN_COERCE3:%.*]])115// CPP-CHECK-NEXT: ret { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } [[TMP0]]116//117svfloat32x4_t test_svcvt_f32_u32_x4(svuint32x4_t zn) __arm_streaming {118 return SVE_ACLE_FUNC(svcvt_f32,_u32_x4,,)(zn);119}120 121// CHECK-LABEL: @test_svcvt_f32_s32_x4(122// CHECK-NEXT: entry:123// CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.scvtf.x4.nxv4f32.nxv4i32(<vscale x 4 x i32> [[ZN_COERCE0:%.*]], <vscale x 4 x i32> [[ZN_COERCE1:%.*]], <vscale x 4 x i32> [[ZN_COERCE2:%.*]], <vscale x 4 x i32> [[ZN_COERCE3:%.*]])124// CHECK-NEXT: ret { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } [[TMP0]]125//126// CPP-CHECK-LABEL: @_Z21test_svcvt_f32_s32_x411svint32x4_t(127// CPP-CHECK-NEXT: entry:128// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.scvtf.x4.nxv4f32.nxv4i32(<vscale x 4 x i32> [[ZN_COERCE0:%.*]], <vscale x 4 x i32> [[ZN_COERCE1:%.*]], <vscale x 4 x i32> [[ZN_COERCE2:%.*]], <vscale x 4 x i32> [[ZN_COERCE3:%.*]])129// CPP-CHECK-NEXT: ret { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } [[TMP0]]130//131svfloat32x4_t test_svcvt_f32_s32_x4(svint32x4_t zn) __arm_streaming {132 return SVE_ACLE_FUNC(svcvt_f32,_s32_x4,,)(zn);133}134 135// CHECK-LABEL: @test_svcvt_u32_f32_x4(136// CHECK-NEXT: entry:137// CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.fcvtzu.x4.nxv4i32.nxv4f32(<vscale x 4 x float> [[ZN_COERCE0:%.*]], <vscale x 4 x float> [[ZN_COERCE1:%.*]], <vscale x 4 x float> [[ZN_COERCE2:%.*]], <vscale x 4 x float> [[ZN_COERCE3:%.*]])138// CHECK-NEXT: ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP0]]139//140// CPP-CHECK-LABEL: @_Z21test_svcvt_u32_f32_x413svfloat32x4_t(141// CPP-CHECK-NEXT: entry:142// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.fcvtzu.x4.nxv4i32.nxv4f32(<vscale x 4 x float> [[ZN_COERCE0:%.*]], <vscale x 4 x float> [[ZN_COERCE1:%.*]], <vscale x 4 x float> [[ZN_COERCE2:%.*]], <vscale x 4 x float> [[ZN_COERCE3:%.*]])143// CPP-CHECK-NEXT: ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP0]]144//145svuint32x4_t test_svcvt_u32_f32_x4(svfloat32x4_t zn) __arm_streaming {146 return SVE_ACLE_FUNC(svcvt_u32,_f32_x4,,)(zn);147}148 149// CHECK-LABEL: @test_svcvt_s32_f32_x4(150// CHECK-NEXT: entry:151// CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.fcvtzs.x4.nxv4i32.nxv4f32(<vscale x 4 x float> [[ZN_COERCE0:%.*]], <vscale x 4 x float> [[ZN_COERCE1:%.*]], <vscale x 4 x float> [[ZN_COERCE2:%.*]], <vscale x 4 x float> [[ZN_COERCE3:%.*]])152// CHECK-NEXT: ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP0]]153//154// CPP-CHECK-LABEL: @_Z21test_svcvt_s32_f32_x413svfloat32x4_t(155// CPP-CHECK-NEXT: entry:156// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.fcvtzs.x4.nxv4i32.nxv4f32(<vscale x 4 x float> [[ZN_COERCE0:%.*]], <vscale x 4 x float> [[ZN_COERCE1:%.*]], <vscale x 4 x float> [[ZN_COERCE2:%.*]], <vscale x 4 x float> [[ZN_COERCE3:%.*]])157// CPP-CHECK-NEXT: ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP0]]158//159svint32x4_t test_svcvt_s32_f32_x4(svfloat32x4_t zn) __arm_streaming {160 return SVE_ACLE_FUNC(svcvt_s32,_f32_x4,,)(zn);161}162 163// CHECK-LABEL: @test_qcvt_s16_s32_x2(164// CHECK-NEXT: entry:165// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.sqcvt.x2.nxv4i32(<vscale x 4 x i32> [[ZN_COERCE0:%.*]], <vscale x 4 x i32> [[ZN_COERCE1:%.*]])166// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]167//168// CPP-CHECK-LABEL: @_Z20test_qcvt_s16_s32_x211svint32x2_t(169// CPP-CHECK-NEXT: entry:170// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.sqcvt.x2.nxv4i32(<vscale x 4 x i32> [[ZN_COERCE0:%.*]], <vscale x 4 x i32> [[ZN_COERCE1:%.*]])171// CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]172//173svint16_t test_qcvt_s16_s32_x2(svint32x2_t zn) __arm_streaming {174 return SVE_ACLE_FUNC(svqcvt_s16,_s32_x2,,)(zn);175}176 177// CHECK-LABEL: @test_qcvt_u16_u32_x2(178// CHECK-NEXT: entry:179// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.uqcvt.x2.nxv4i32(<vscale x 4 x i32> [[ZN_COERCE0:%.*]], <vscale x 4 x i32> [[ZN_COERCE1:%.*]])180// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]181//182// CPP-CHECK-LABEL: @_Z20test_qcvt_u16_u32_x212svuint32x2_t(183// CPP-CHECK-NEXT: entry:184// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.uqcvt.x2.nxv4i32(<vscale x 4 x i32> [[ZN_COERCE0:%.*]], <vscale x 4 x i32> [[ZN_COERCE1:%.*]])185// CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]186//187svuint16_t test_qcvt_u16_u32_x2(svuint32x2_t zn) __arm_streaming {188 return SVE_ACLE_FUNC(svqcvt_u16,_u32_x2,,)(zn);189}190 191// CHECK-LABEL: @test_qcvt_u16_s32_x2(192// CHECK-NEXT: entry:193// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.sqcvtu.x2.nxv4i32(<vscale x 4 x i32> [[ZN_COERCE0:%.*]], <vscale x 4 x i32> [[ZN_COERCE1:%.*]])194// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]195//196// CPP-CHECK-LABEL: @_Z20test_qcvt_u16_s32_x211svint32x2_t(197// CPP-CHECK-NEXT: entry:198// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.sqcvtu.x2.nxv4i32(<vscale x 4 x i32> [[ZN_COERCE0:%.*]], <vscale x 4 x i32> [[ZN_COERCE1:%.*]])199// CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]200//201svuint16_t test_qcvt_u16_s32_x2(svint32x2_t zn) __arm_streaming {202 return SVE_ACLE_FUNC(svqcvt_u16,_s32_x2,,)(zn);203}204 205// CHECK-LABEL: @test_qcvt_u8_u32_x4(206// CHECK-NEXT: entry:207// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.uqcvt.x4.nxv4i32(<vscale x 4 x i32> [[ZN_COERCE0:%.*]], <vscale x 4 x i32> [[ZN_COERCE1:%.*]], <vscale x 4 x i32> [[ZN_COERCE2:%.*]], <vscale x 4 x i32> [[ZN_COERCE3:%.*]])208// CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]209//210// CPP-CHECK-LABEL: @_Z19test_qcvt_u8_u32_x412svuint32x4_t(211// CPP-CHECK-NEXT: entry:212// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.uqcvt.x4.nxv4i32(<vscale x 4 x i32> [[ZN_COERCE0:%.*]], <vscale x 4 x i32> [[ZN_COERCE1:%.*]], <vscale x 4 x i32> [[ZN_COERCE2:%.*]], <vscale x 4 x i32> [[ZN_COERCE3:%.*]])213// CPP-CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]214//215svuint8_t test_qcvt_u8_u32_x4(svuint32x4_t zn) __arm_streaming {216 return SVE_ACLE_FUNC(svqcvt_u8,_u32_x4,,)(zn);217}218 219// CHECK-LABEL: @test_qcvt_u16_u64_x4(220// CHECK-NEXT: entry:221// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.uqcvt.x4.nxv2i64(<vscale x 2 x i64> [[ZN_COERCE0:%.*]], <vscale x 2 x i64> [[ZN_COERCE1:%.*]], <vscale x 2 x i64> [[ZN_COERCE2:%.*]], <vscale x 2 x i64> [[ZN_COERCE3:%.*]])222// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]223//224// CPP-CHECK-LABEL: @_Z20test_qcvt_u16_u64_x412svuint64x4_t(225// CPP-CHECK-NEXT: entry:226// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.uqcvt.x4.nxv2i64(<vscale x 2 x i64> [[ZN_COERCE0:%.*]], <vscale x 2 x i64> [[ZN_COERCE1:%.*]], <vscale x 2 x i64> [[ZN_COERCE2:%.*]], <vscale x 2 x i64> [[ZN_COERCE3:%.*]])227// CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]228//229svuint16_t test_qcvt_u16_u64_x4(svuint64x4_t zn) __arm_streaming {230 return SVE_ACLE_FUNC(svqcvt_u16,_u64_x4,,)(zn);231}232 233// CHECK-LABEL: @test_qcvt_s8_s32_x4(234// CHECK-NEXT: entry:235// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.sqcvt.x4.nxv4i32(<vscale x 4 x i32> [[ZN_COERCE0:%.*]], <vscale x 4 x i32> [[ZN_COERCE1:%.*]], <vscale x 4 x i32> [[ZN_COERCE2:%.*]], <vscale x 4 x i32> [[ZN_COERCE3:%.*]])236// CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]237//238// CPP-CHECK-LABEL: @_Z19test_qcvt_s8_s32_x411svint32x4_t(239// CPP-CHECK-NEXT: entry:240// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.sqcvt.x4.nxv4i32(<vscale x 4 x i32> [[ZN_COERCE0:%.*]], <vscale x 4 x i32> [[ZN_COERCE1:%.*]], <vscale x 4 x i32> [[ZN_COERCE2:%.*]], <vscale x 4 x i32> [[ZN_COERCE3:%.*]])241// CPP-CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]242//243svint8_t test_qcvt_s8_s32_x4(svint32x4_t zn) __arm_streaming {244 return SVE_ACLE_FUNC(svqcvt_s8,_s32_x4,,)(zn);245}246 247// CHECK-LABEL: @test_qcvt_s16_s64_x4(248// CHECK-NEXT: entry:249// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.sqcvt.x4.nxv2i64(<vscale x 2 x i64> [[ZN_COERCE0:%.*]], <vscale x 2 x i64> [[ZN_COERCE1:%.*]], <vscale x 2 x i64> [[ZN_COERCE2:%.*]], <vscale x 2 x i64> [[ZN_COERCE3:%.*]])250// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]251//252// CPP-CHECK-LABEL: @_Z20test_qcvt_s16_s64_x411svint64x4_t(253// CPP-CHECK-NEXT: entry:254// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.sqcvt.x4.nxv2i64(<vscale x 2 x i64> [[ZN_COERCE0:%.*]], <vscale x 2 x i64> [[ZN_COERCE1:%.*]], <vscale x 2 x i64> [[ZN_COERCE2:%.*]], <vscale x 2 x i64> [[ZN_COERCE3:%.*]])255// CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]256//257svint16_t test_qcvt_s16_s64_x4(svint64x4_t zn) __arm_streaming {258 return SVE_ACLE_FUNC(svqcvt_s16,_s64_x4,,)(zn);259}260 261// CHECK-LABEL: @test_qcvt_u8_s32_x4(262// CHECK-NEXT: entry:263// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.sqcvtu.x4.nxv4i32(<vscale x 4 x i32> [[ZN_COERCE0:%.*]], <vscale x 4 x i32> [[ZN_COERCE1:%.*]], <vscale x 4 x i32> [[ZN_COERCE2:%.*]], <vscale x 4 x i32> [[ZN_COERCE3:%.*]])264// CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]265//266// CPP-CHECK-LABEL: @_Z19test_qcvt_u8_s32_x411svint32x4_t(267// CPP-CHECK-NEXT: entry:268// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.sqcvtu.x4.nxv4i32(<vscale x 4 x i32> [[ZN_COERCE0:%.*]], <vscale x 4 x i32> [[ZN_COERCE1:%.*]], <vscale x 4 x i32> [[ZN_COERCE2:%.*]], <vscale x 4 x i32> [[ZN_COERCE3:%.*]])269// CPP-CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]270//271svuint8_t test_qcvt_u8_s32_x4(svint32x4_t zn) __arm_streaming {272 return SVE_ACLE_FUNC(svqcvt_u8,_s32_x4,,)(zn);273}274 275// CHECK-LABEL: @test_qcvt_u16_s64_x4(276// CHECK-NEXT: entry:277// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.sqcvtu.x4.nxv2i64(<vscale x 2 x i64> [[ZN_COERCE0:%.*]], <vscale x 2 x i64> [[ZN_COERCE1:%.*]], <vscale x 2 x i64> [[ZN_COERCE2:%.*]], <vscale x 2 x i64> [[ZN_COERCE3:%.*]])278// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]279//280// CPP-CHECK-LABEL: @_Z20test_qcvt_u16_s64_x411svint64x4_t(281// CPP-CHECK-NEXT: entry:282// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.sqcvtu.x4.nxv2i64(<vscale x 2 x i64> [[ZN_COERCE0:%.*]], <vscale x 2 x i64> [[ZN_COERCE1:%.*]], <vscale x 2 x i64> [[ZN_COERCE2:%.*]], <vscale x 2 x i64> [[ZN_COERCE3:%.*]])283// CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]284//285svuint16_t test_qcvt_u16_s64_x4(svint64x4_t zn) __arm_streaming {286 return SVE_ACLE_FUNC(svqcvt_u16,_s64_x4,,)(zn);287}288 289// CHECK-LABEL: @test_cvt_f32_x2(290// CHECK-NEXT: entry:291// CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.fcvt.widen.x2.nxv4f32(<vscale x 8 x half> [[ZN:%.*]])292// CHECK-NEXT: ret { <vscale x 4 x float>, <vscale x 4 x float> } [[TMP0]]293//294// CPP-CHECK-LABEL: @_Z15test_cvt_f32_x2u13__SVFloat16_t(295// CPP-CHECK-NEXT: entry:296// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.fcvt.widen.x2.nxv4f32(<vscale x 8 x half> [[ZN:%.*]])297// CPP-CHECK-NEXT: ret { <vscale x 4 x float>, <vscale x 4 x float> } [[TMP0]]298//299__attribute__((target("sme-f16f16"))) svfloat32x2_t test_cvt_f32_x2(svfloat16_t zn) __arm_streaming {300 return SVE_ACLE_FUNC(svcvt_f32,_f16_x2,,)(zn);301}302