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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py2 3// REQUIRES: aarch64-registered-target4 5// RUN: %clang_cc1 -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s6// RUN: %clang_cc1 -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK7// RUN: %clang_cc1 -D__SVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s8// RUN: %clang_cc1 -D__SVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK9// RUN: %clang_cc1 -triple aarch64 -target-feature +sme -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s10 11#include <arm_sme.h>12 13#ifdef SVE_OVERLOADED_FORMS14// A simple used,unused... macro, long enough to represent any SVE builtin.15#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A316#else17#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A418#endif19 20// CHECK-LABEL: @test_cvtn_f16_x2(21// CHECK-NEXT: entry:22// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.fcvtn.x2.nxv4f32(<vscale x 4 x float> [[ZN_COERCE0:%.*]], <vscale x 4 x float> [[ZN_COERCE1:%.*]])23// CHECK-NEXT: ret <vscale x 8 x half> [[TMP0]]24//25// CPP-CHECK-LABEL: @_Z16test_cvtn_f16_x213svfloat32x2_t(26// CPP-CHECK-NEXT: entry:27// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.fcvtn.x2.nxv4f32(<vscale x 4 x float> [[ZN_COERCE0:%.*]], <vscale x 4 x float> [[ZN_COERCE1:%.*]])28// CPP-CHECK-NEXT: ret <vscale x 8 x half> [[TMP0]]29//30svfloat16_t test_cvtn_f16_x2(svfloat32x2_t zn) __arm_streaming {31 return SVE_ACLE_FUNC(svcvtn_f16,_f32_x2,,)(zn);32}33 34// CHECK-LABEL: @test_cvtn_bf16_x2(35// CHECK-NEXT: entry:36// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x bfloat> @llvm.aarch64.sve.bfcvtn.x2(<vscale x 4 x float> [[ZN_COERCE0:%.*]], <vscale x 4 x float> [[ZN_COERCE1:%.*]])37// CHECK-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]38//39// CPP-CHECK-LABEL: @_Z17test_cvtn_bf16_x213svfloat32x2_t(40// CPP-CHECK-NEXT: entry:41// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x bfloat> @llvm.aarch64.sve.bfcvtn.x2(<vscale x 4 x float> [[ZN_COERCE0:%.*]], <vscale x 4 x float> [[ZN_COERCE1:%.*]])42// CPP-CHECK-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]43//44svbfloat16_t test_cvtn_bf16_x2(svfloat32x2_t zn) __arm_streaming {45 return SVE_ACLE_FUNC(svcvtn_bf16,_f32_x2,,)(zn);46}47 48// CHECK-LABEL: @test_qcvtn_u8_u32_x4(49// CHECK-NEXT: entry:50// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.uqcvtn.x4.nxv4i32(<vscale x 4 x i32> [[ZN_COERCE0:%.*]], <vscale x 4 x i32> [[ZN_COERCE1:%.*]], <vscale x 4 x i32> [[ZN_COERCE2:%.*]], <vscale x 4 x i32> [[ZN_COERCE3:%.*]])51// CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]52//53// CPP-CHECK-LABEL: @_Z20test_qcvtn_u8_u32_x412svuint32x4_t(54// CPP-CHECK-NEXT: entry:55// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.uqcvtn.x4.nxv4i32(<vscale x 4 x i32> [[ZN_COERCE0:%.*]], <vscale x 4 x i32> [[ZN_COERCE1:%.*]], <vscale x 4 x i32> [[ZN_COERCE2:%.*]], <vscale x 4 x i32> [[ZN_COERCE3:%.*]])56// CPP-CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]57//58svuint8_t test_qcvtn_u8_u32_x4(svuint32x4_t zn) __arm_streaming {59 return SVE_ACLE_FUNC(svqcvtn_u8,_u32_x4,,)(zn);60}61 62// CHECK-LABEL: @test_qcvtn_u16_u64_x4(63// CHECK-NEXT: entry:64// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.uqcvtn.x4.nxv2i64(<vscale x 2 x i64> [[ZN_COERCE0:%.*]], <vscale x 2 x i64> [[ZN_COERCE1:%.*]], <vscale x 2 x i64> [[ZN_COERCE2:%.*]], <vscale x 2 x i64> [[ZN_COERCE3:%.*]])65// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]66//67// CPP-CHECK-LABEL: @_Z21test_qcvtn_u16_u64_x412svuint64x4_t(68// CPP-CHECK-NEXT: entry:69// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.uqcvtn.x4.nxv2i64(<vscale x 2 x i64> [[ZN_COERCE0:%.*]], <vscale x 2 x i64> [[ZN_COERCE1:%.*]], <vscale x 2 x i64> [[ZN_COERCE2:%.*]], <vscale x 2 x i64> [[ZN_COERCE3:%.*]])70// CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]71//72svuint16_t test_qcvtn_u16_u64_x4(svuint64x4_t zn) __arm_streaming {73 return SVE_ACLE_FUNC(svqcvtn_u16,_u64_x4,,)(zn);74}75 76// CHECK-LABEL: @test_qcvtn_s8_s32_x4(77// CHECK-NEXT: entry:78// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.sqcvtn.x4.nxv4i32(<vscale x 4 x i32> [[ZN_COERCE0:%.*]], <vscale x 4 x i32> [[ZN_COERCE1:%.*]], <vscale x 4 x i32> [[ZN_COERCE2:%.*]], <vscale x 4 x i32> [[ZN_COERCE3:%.*]])79// CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]80//81// CPP-CHECK-LABEL: @_Z20test_qcvtn_s8_s32_x411svint32x4_t(82// CPP-CHECK-NEXT: entry:83// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.sqcvtn.x4.nxv4i32(<vscale x 4 x i32> [[ZN_COERCE0:%.*]], <vscale x 4 x i32> [[ZN_COERCE1:%.*]], <vscale x 4 x i32> [[ZN_COERCE2:%.*]], <vscale x 4 x i32> [[ZN_COERCE3:%.*]])84// CPP-CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]85//86svint8_t test_qcvtn_s8_s32_x4(svint32x4_t zn) __arm_streaming {87 return SVE_ACLE_FUNC(svqcvtn_s8,_s32_x4,,)(zn);88}89 90// CHECK-LABEL: @test_qcvtn_s16_s64_x4(91// CHECK-NEXT: entry:92// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.sqcvtn.x4.nxv2i64(<vscale x 2 x i64> [[ZN_COERCE0:%.*]], <vscale x 2 x i64> [[ZN_COERCE1:%.*]], <vscale x 2 x i64> [[ZN_COERCE2:%.*]], <vscale x 2 x i64> [[ZN_COERCE3:%.*]])93// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]94//95// CPP-CHECK-LABEL: @_Z21test_qcvtn_s16_s64_x411svint64x4_t(96// CPP-CHECK-NEXT: entry:97// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.sqcvtn.x4.nxv2i64(<vscale x 2 x i64> [[ZN_COERCE0:%.*]], <vscale x 2 x i64> [[ZN_COERCE1:%.*]], <vscale x 2 x i64> [[ZN_COERCE2:%.*]], <vscale x 2 x i64> [[ZN_COERCE3:%.*]])98// CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]99//100svint16_t test_qcvtn_s16_s64_x4(svint64x4_t zn) __arm_streaming {101 return SVE_ACLE_FUNC(svqcvtn_s16,_s64_x4,,)(zn);102}103 104// CHECK-LABEL: @test_qcvtn_u8_32_x4(105// CHECK-NEXT: entry:106// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.sqcvtun.x4.nxv4i32(<vscale x 4 x i32> [[ZN_COERCE0:%.*]], <vscale x 4 x i32> [[ZN_COERCE1:%.*]], <vscale x 4 x i32> [[ZN_COERCE2:%.*]], <vscale x 4 x i32> [[ZN_COERCE3:%.*]])107// CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]108//109// CPP-CHECK-LABEL: @_Z19test_qcvtn_u8_32_x411svint32x4_t(110// CPP-CHECK-NEXT: entry:111// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.sqcvtun.x4.nxv4i32(<vscale x 4 x i32> [[ZN_COERCE0:%.*]], <vscale x 4 x i32> [[ZN_COERCE1:%.*]], <vscale x 4 x i32> [[ZN_COERCE2:%.*]], <vscale x 4 x i32> [[ZN_COERCE3:%.*]])112// CPP-CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]113//114svuint8_t test_qcvtn_u8_32_x4(svint32x4_t zn) __arm_streaming {115 return SVE_ACLE_FUNC(svqcvtn_u8,_s32_x4,,)(zn);116}117 118// CHECK-LABEL: @test_qcvtn_u16_s64_x4(119// CHECK-NEXT: entry:120// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.sqcvtun.x4.nxv2i64(<vscale x 2 x i64> [[ZN_COERCE0:%.*]], <vscale x 2 x i64> [[ZN_COERCE1:%.*]], <vscale x 2 x i64> [[ZN_COERCE2:%.*]], <vscale x 2 x i64> [[ZN_COERCE3:%.*]])121// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]122//123// CPP-CHECK-LABEL: @_Z21test_qcvtn_u16_s64_x411svint64x4_t(124// CPP-CHECK-NEXT: entry:125// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.sqcvtun.x4.nxv2i64(<vscale x 2 x i64> [[ZN_COERCE0:%.*]], <vscale x 2 x i64> [[ZN_COERCE1:%.*]], <vscale x 2 x i64> [[ZN_COERCE2:%.*]], <vscale x 2 x i64> [[ZN_COERCE3:%.*]])126// CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]127//128svuint16_t test_qcvtn_u16_s64_x4(svint64x4_t zn) __arm_streaming {129 return SVE_ACLE_FUNC(svqcvtn_u16,_s64_x4,,)(zn);130}131 132 133