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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py2// REQUIRES: aarch64-registered-target3 4// RUN: %clang_cc1 -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s5// RUN: %clang_cc1 -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK6// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s7// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK8// RUN: %clang_cc1 -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-f64f64 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s9 10#include <arm_sme.h>11 12#ifdef SVE_OVERLOADED_FORMS13// A simple used,unused... macro, long enough to represent any SVE builtin.14#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED,A5) A1##A3##A515#else16#define SVE_ACLE_FUNC(A1,A2,A3,A4,A5) A1##A2##A3##A4##A517#endif18 19// SVQRSHR20 21// CHECK-LABEL: @test_svsqrshr_u16_u32_x4(22// CHECK-NEXT: entry:23// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.uqrshr.x2.nxv4i32(<vscale x 4 x i32> [[ZN_COERCE0:%.*]], <vscale x 4 x i32> [[ZN_COERCE1:%.*]], i32 16)24// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]25//26// CPP-CHECK-LABEL: @_Z24test_svsqrshr_u16_u32_x412svuint32x2_t(27// CPP-CHECK-NEXT: entry:28// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.uqrshr.x2.nxv4i32(<vscale x 4 x i32> [[ZN_COERCE0:%.*]], <vscale x 4 x i32> [[ZN_COERCE1:%.*]], i32 16)29// CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]30//31svuint16_t test_svsqrshr_u16_u32_x4(svuint32x2_t zn) __arm_streaming {32 return SVE_ACLE_FUNC(svqrshr,_n,_u16,_u32_x2,)(zn, 16);33}34 35// CHECK-LABEL: @test_svsqrshr_s16_s32_x4(36// CHECK-NEXT: entry:37// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.sqrshr.x2.nxv4i32(<vscale x 4 x i32> [[ZN_COERCE0:%.*]], <vscale x 4 x i32> [[ZN_COERCE1:%.*]], i32 16)38// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]39//40// CPP-CHECK-LABEL: @_Z24test_svsqrshr_s16_s32_x411svint32x2_t(41// CPP-CHECK-NEXT: entry:42// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.sqrshr.x2.nxv4i32(<vscale x 4 x i32> [[ZN_COERCE0:%.*]], <vscale x 4 x i32> [[ZN_COERCE1:%.*]], i32 16)43// CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]44//45svint16_t test_svsqrshr_s16_s32_x4(svint32x2_t zn) __arm_streaming {46 return SVE_ACLE_FUNC(svqrshr,_n,_s16,_s32_x2,)(zn, 16);47}48 49// CHECK-LABEL: @test_svsqrshr_u8_u32_x4(50// CHECK-NEXT: entry:51// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.uqrshr.x4.nxv4i32(<vscale x 4 x i32> [[ZN_COERCE0:%.*]], <vscale x 4 x i32> [[ZN_COERCE1:%.*]], <vscale x 4 x i32> [[ZN_COERCE2:%.*]], <vscale x 4 x i32> [[ZN_COERCE3:%.*]], i32 8)52// CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]53//54// CPP-CHECK-LABEL: @_Z23test_svsqrshr_u8_u32_x412svuint32x4_t(55// CPP-CHECK-NEXT: entry:56// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.uqrshr.x4.nxv4i32(<vscale x 4 x i32> [[ZN_COERCE0:%.*]], <vscale x 4 x i32> [[ZN_COERCE1:%.*]], <vscale x 4 x i32> [[ZN_COERCE2:%.*]], <vscale x 4 x i32> [[ZN_COERCE3:%.*]], i32 8)57// CPP-CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]58//59svuint8_t test_svsqrshr_u8_u32_x4(svuint32x4_t zn) __arm_streaming {60 return SVE_ACLE_FUNC(svqrshr,_n,_u8,_u32_x4,)(zn, 8);61}62 63// CHECK-LABEL: @test_svsqrshr_s8_s32_x4(64// CHECK-NEXT: entry:65// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.sqrshr.x4.nxv4i32(<vscale x 4 x i32> [[ZN_COERCE0:%.*]], <vscale x 4 x i32> [[ZN_COERCE1:%.*]], <vscale x 4 x i32> [[ZN_COERCE2:%.*]], <vscale x 4 x i32> [[ZN_COERCE3:%.*]], i32 8)66// CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]67//68// CPP-CHECK-LABEL: @_Z23test_svsqrshr_s8_s32_x411svint32x4_t(69// CPP-CHECK-NEXT: entry:70// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.sqrshr.x4.nxv4i32(<vscale x 4 x i32> [[ZN_COERCE0:%.*]], <vscale x 4 x i32> [[ZN_COERCE1:%.*]], <vscale x 4 x i32> [[ZN_COERCE2:%.*]], <vscale x 4 x i32> [[ZN_COERCE3:%.*]], i32 8)71// CPP-CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]72//73svint8_t test_svsqrshr_s8_s32_x4(svint32x4_t zn) __arm_streaming {74 return SVE_ACLE_FUNC(svqrshr,_n,_s8,_s32_x4,)(zn, 8);75}76 77// CHECK-LABEL: @test_svsqrshr_u16_u64_x4(78// CHECK-NEXT: entry:79// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.uqrshr.x4.nxv2i64(<vscale x 2 x i64> [[ZN_COERCE0:%.*]], <vscale x 2 x i64> [[ZN_COERCE1:%.*]], <vscale x 2 x i64> [[ZN_COERCE2:%.*]], <vscale x 2 x i64> [[ZN_COERCE3:%.*]], i32 16)80// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]81//82// CPP-CHECK-LABEL: @_Z24test_svsqrshr_u16_u64_x412svuint64x4_t(83// CPP-CHECK-NEXT: entry:84// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.uqrshr.x4.nxv2i64(<vscale x 2 x i64> [[ZN_COERCE0:%.*]], <vscale x 2 x i64> [[ZN_COERCE1:%.*]], <vscale x 2 x i64> [[ZN_COERCE2:%.*]], <vscale x 2 x i64> [[ZN_COERCE3:%.*]], i32 16)85// CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]86//87svuint16_t test_svsqrshr_u16_u64_x4(svuint64x4_t zn) __arm_streaming {88 return SVE_ACLE_FUNC(svqrshr,_n,_u16,_u64_x4,)(zn, 16);89}90 91// CHECK-LABEL: @test_svsqrshr_s16_s64_x4(92// CHECK-NEXT: entry:93// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.sqrshr.x4.nxv2i64(<vscale x 2 x i64> [[ZN_COERCE0:%.*]], <vscale x 2 x i64> [[ZN_COERCE1:%.*]], <vscale x 2 x i64> [[ZN_COERCE2:%.*]], <vscale x 2 x i64> [[ZN_COERCE3:%.*]], i32 16)94// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]95//96// CPP-CHECK-LABEL: @_Z24test_svsqrshr_s16_s64_x411svint64x4_t(97// CPP-CHECK-NEXT: entry:98// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.sqrshr.x4.nxv2i64(<vscale x 2 x i64> [[ZN_COERCE0:%.*]], <vscale x 2 x i64> [[ZN_COERCE1:%.*]], <vscale x 2 x i64> [[ZN_COERCE2:%.*]], <vscale x 2 x i64> [[ZN_COERCE3:%.*]], i32 16)99// CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]100//101svint16_t test_svsqrshr_s16_s64_x4(svint64x4_t zn) __arm_streaming {102 return SVE_ACLE_FUNC(svqrshr,_n,_s16,_s64_x4,)(zn, 16);103}104 105// SVQRSHRN106 107// CHECK-LABEL: @test_svsqrshrn_u8_u32_x4(108// CHECK-NEXT: entry:109// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.uqrshrn.x4.nxv4i32(<vscale x 4 x i32> [[ZN_COERCE0:%.*]], <vscale x 4 x i32> [[ZN_COERCE1:%.*]], <vscale x 4 x i32> [[ZN_COERCE2:%.*]], <vscale x 4 x i32> [[ZN_COERCE3:%.*]], i32 8)110// CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]111//112// CPP-CHECK-LABEL: @_Z24test_svsqrshrn_u8_u32_x412svuint32x4_t(113// CPP-CHECK-NEXT: entry:114// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.uqrshrn.x4.nxv4i32(<vscale x 4 x i32> [[ZN_COERCE0:%.*]], <vscale x 4 x i32> [[ZN_COERCE1:%.*]], <vscale x 4 x i32> [[ZN_COERCE2:%.*]], <vscale x 4 x i32> [[ZN_COERCE3:%.*]], i32 8)115// CPP-CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]116//117svuint8_t test_svsqrshrn_u8_u32_x4(svuint32x4_t zn) __arm_streaming {118 return SVE_ACLE_FUNC(svqrshrn,_n,_u8,_u32_x4,)(zn, 8);119}120 121// CHECK-LABEL: @test_svsqrshrn_s8_s32_x4(122// CHECK-NEXT: entry:123// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.sqrshrn.x4.nxv4i32(<vscale x 4 x i32> [[ZN_COERCE0:%.*]], <vscale x 4 x i32> [[ZN_COERCE1:%.*]], <vscale x 4 x i32> [[ZN_COERCE2:%.*]], <vscale x 4 x i32> [[ZN_COERCE3:%.*]], i32 8)124// CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]125//126// CPP-CHECK-LABEL: @_Z24test_svsqrshrn_s8_s32_x411svint32x4_t(127// CPP-CHECK-NEXT: entry:128// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.sqrshrn.x4.nxv4i32(<vscale x 4 x i32> [[ZN_COERCE0:%.*]], <vscale x 4 x i32> [[ZN_COERCE1:%.*]], <vscale x 4 x i32> [[ZN_COERCE2:%.*]], <vscale x 4 x i32> [[ZN_COERCE3:%.*]], i32 8)129// CPP-CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]130//131svint8_t test_svsqrshrn_s8_s32_x4(svint32x4_t zn) __arm_streaming {132 return SVE_ACLE_FUNC(svqrshrn,_n,_s8,_s32_x4,)(zn, 8);133}134 135// CHECK-LABEL: @test_svsqrshrn_u16_u64_x4(136// CHECK-NEXT: entry:137// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.uqrshrn.x4.nxv2i64(<vscale x 2 x i64> [[ZN_COERCE0:%.*]], <vscale x 2 x i64> [[ZN_COERCE1:%.*]], <vscale x 2 x i64> [[ZN_COERCE2:%.*]], <vscale x 2 x i64> [[ZN_COERCE3:%.*]], i32 16)138// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]139//140// CPP-CHECK-LABEL: @_Z25test_svsqrshrn_u16_u64_x412svuint64x4_t(141// CPP-CHECK-NEXT: entry:142// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.uqrshrn.x4.nxv2i64(<vscale x 2 x i64> [[ZN_COERCE0:%.*]], <vscale x 2 x i64> [[ZN_COERCE1:%.*]], <vscale x 2 x i64> [[ZN_COERCE2:%.*]], <vscale x 2 x i64> [[ZN_COERCE3:%.*]], i32 16)143// CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]144//145svuint16_t test_svsqrshrn_u16_u64_x4(svuint64x4_t zn) __arm_streaming {146 return SVE_ACLE_FUNC(svqrshrn,_n,_u16,_u64_x4,)(zn, 16);147}148 149// CHECK-LABEL: @test_svsqrshrn_s16_s64_x4(150// CHECK-NEXT: entry:151// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.sqrshrn.x4.nxv2i64(<vscale x 2 x i64> [[ZN_COERCE0:%.*]], <vscale x 2 x i64> [[ZN_COERCE1:%.*]], <vscale x 2 x i64> [[ZN_COERCE2:%.*]], <vscale x 2 x i64> [[ZN_COERCE3:%.*]], i32 16)152// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]153//154// CPP-CHECK-LABEL: @_Z25test_svsqrshrn_s16_s64_x411svint64x4_t(155// CPP-CHECK-NEXT: entry:156// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.sqrshrn.x4.nxv2i64(<vscale x 2 x i64> [[ZN_COERCE0:%.*]], <vscale x 2 x i64> [[ZN_COERCE1:%.*]], <vscale x 2 x i64> [[ZN_COERCE2:%.*]], <vscale x 2 x i64> [[ZN_COERCE3:%.*]], i32 16)157// CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]158//159svint16_t test_svsqrshrn_s16_s64_x4(svint64x4_t zn) __arm_streaming {160 return SVE_ACLE_FUNC(svqrshrn,_n,_s16,_s64_x4,)(zn, 16);161}162 163// SVSQRSHRU164 165// CHECK-LABEL: @test_svsvqrshru_u16_s32_x2(166// CHECK-NEXT: entry:167// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.sqrshru.x2.nxv4i32(<vscale x 4 x i32> [[ZN_COERCE0:%.*]], <vscale x 4 x i32> [[ZN_COERCE1:%.*]], i32 16)168// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]169//170// CPP-CHECK-LABEL: @_Z26test_svsvqrshru_u16_s32_x211svint32x2_t(171// CPP-CHECK-NEXT: entry:172// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.sqrshru.x2.nxv4i32(<vscale x 4 x i32> [[ZN_COERCE0:%.*]], <vscale x 4 x i32> [[ZN_COERCE1:%.*]], i32 16)173// CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]174//175svuint16_t test_svsvqrshru_u16_s32_x2(svint32x2_t zn) __arm_streaming {176 return SVE_ACLE_FUNC(svqrshru,_n,_u16,_s32_x2,)(zn, 16);177}178 179// CHECK-LABEL: @test_svsqrshru_u8_s32_x4(180// CHECK-NEXT: entry:181// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.sqrshru.x4.nxv4i32(<vscale x 4 x i32> [[ZN_COERCE0:%.*]], <vscale x 4 x i32> [[ZN_COERCE1:%.*]], <vscale x 4 x i32> [[ZN_COERCE2:%.*]], <vscale x 4 x i32> [[ZN_COERCE3:%.*]], i32 8)182// CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]183//184// CPP-CHECK-LABEL: @_Z24test_svsqrshru_u8_s32_x411svint32x4_t(185// CPP-CHECK-NEXT: entry:186// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.sqrshru.x4.nxv4i32(<vscale x 4 x i32> [[ZN_COERCE0:%.*]], <vscale x 4 x i32> [[ZN_COERCE1:%.*]], <vscale x 4 x i32> [[ZN_COERCE2:%.*]], <vscale x 4 x i32> [[ZN_COERCE3:%.*]], i32 8)187// CPP-CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]188//189svuint8_t test_svsqrshru_u8_s32_x4(svint32x4_t zn) __arm_streaming {190 return SVE_ACLE_FUNC(svqrshru,_n,_u8,_s32_x4,)(zn, 8);191}192 193// CHECK-LABEL: @test_svsqrshru_u16_s64_x4(194// CHECK-NEXT: entry:195// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.sqrshru.x4.nxv2i64(<vscale x 2 x i64> [[ZN_COERCE0:%.*]], <vscale x 2 x i64> [[ZN_COERCE1:%.*]], <vscale x 2 x i64> [[ZN_COERCE2:%.*]], <vscale x 2 x i64> [[ZN_COERCE3:%.*]], i32 16)196// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]197//198// CPP-CHECK-LABEL: @_Z25test_svsqrshru_u16_s64_x411svint64x4_t(199// CPP-CHECK-NEXT: entry:200// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.sqrshru.x4.nxv2i64(<vscale x 2 x i64> [[ZN_COERCE0:%.*]], <vscale x 2 x i64> [[ZN_COERCE1:%.*]], <vscale x 2 x i64> [[ZN_COERCE2:%.*]], <vscale x 2 x i64> [[ZN_COERCE3:%.*]], i32 16)201// CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]202//203svuint16_t test_svsqrshru_u16_s64_x4(svint64x4_t zn) __arm_streaming {204 return SVE_ACLE_FUNC(svqrshru,_n,_u16,_s64_x4,)(zn, 16);205}206 207// SQRSHRUN x 4208 209// CHECK-LABEL: @test_svsqrshrun_u8_s32_x4(210// CHECK-NEXT: entry:211// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.sqrshrun.x4.nxv4i32(<vscale x 4 x i32> [[ZN_COERCE0:%.*]], <vscale x 4 x i32> [[ZN_COERCE1:%.*]], <vscale x 4 x i32> [[ZN_COERCE2:%.*]], <vscale x 4 x i32> [[ZN_COERCE3:%.*]], i32 32)212// CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]213//214// CPP-CHECK-LABEL: @_Z25test_svsqrshrun_u8_s32_x411svint32x4_t(215// CPP-CHECK-NEXT: entry:216// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.sqrshrun.x4.nxv4i32(<vscale x 4 x i32> [[ZN_COERCE0:%.*]], <vscale x 4 x i32> [[ZN_COERCE1:%.*]], <vscale x 4 x i32> [[ZN_COERCE2:%.*]], <vscale x 4 x i32> [[ZN_COERCE3:%.*]], i32 32)217// CPP-CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]218//219svuint8_t test_svsqrshrun_u8_s32_x4(svint32x4_t zn) __arm_streaming {220 return SVE_ACLE_FUNC(svqrshrun,_n,_u8,_s32_x4,)(zn, 32);221}222 223// CHECK-LABEL: @test_svsqrshrun_u16_s64_x4(224// CHECK-NEXT: entry:225// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.sqrshrun.x4.nxv2i64(<vscale x 2 x i64> [[ZN_COERCE0:%.*]], <vscale x 2 x i64> [[ZN_COERCE1:%.*]], <vscale x 2 x i64> [[ZN_COERCE2:%.*]], <vscale x 2 x i64> [[ZN_COERCE3:%.*]], i32 64)226// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]227//228// CPP-CHECK-LABEL: @_Z26test_svsqrshrun_u16_s64_x411svint64x4_t(229// CPP-CHECK-NEXT: entry:230// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.sqrshrun.x4.nxv2i64(<vscale x 2 x i64> [[ZN_COERCE0:%.*]], <vscale x 2 x i64> [[ZN_COERCE1:%.*]], <vscale x 2 x i64> [[ZN_COERCE2:%.*]], <vscale x 2 x i64> [[ZN_COERCE3:%.*]], i32 64)231// CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]232//233svuint16_t test_svsqrshrun_u16_s64_x4(svint64x4_t zn) __arm_streaming {234 return SVE_ACLE_FUNC(svqrshrun,_n,_u16,_s64_x4,)(zn, 64);235}236