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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py2// REQUIRES: aarch64-registered-target3// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s4// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK5// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s6// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK7// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s8#include <arm_sve.h>9 10#ifdef SVE_OVERLOADED_FORMS11// A simple used,unused... macro, long enough to represent any SVE builtin.12#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A313#else14#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A415#endif16 17// CHECK-LABEL: @test_svadrd_u32base_s32index(18// CHECK-NEXT: entry:19// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.adrd.nxv4i32(<vscale x 4 x i32> [[BASES:%.*]], <vscale x 4 x i32> [[INDICES:%.*]])20// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]21//22// CPP-CHECK-LABEL: @_Z28test_svadrd_u32base_s32indexu12__SVUint32_tu11__SVInt32_t(23// CPP-CHECK-NEXT: entry:24// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.adrd.nxv4i32(<vscale x 4 x i32> [[BASES:%.*]], <vscale x 4 x i32> [[INDICES:%.*]])25// CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]26//27svuint32_t test_svadrd_u32base_s32index(svuint32_t bases, svint32_t indices)28{29 return SVE_ACLE_FUNC(svadrd_,u32base_s32,index,)(bases, indices);30}31 32// CHECK-LABEL: @test_svadrd_u64base_s64index(33// CHECK-NEXT: entry:34// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.adrd.nxv2i64(<vscale x 2 x i64> [[BASES:%.*]], <vscale x 2 x i64> [[INDICES:%.*]])35// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]36//37// CPP-CHECK-LABEL: @_Z28test_svadrd_u64base_s64indexu12__SVUint64_tu11__SVInt64_t(38// CPP-CHECK-NEXT: entry:39// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.adrd.nxv2i64(<vscale x 2 x i64> [[BASES:%.*]], <vscale x 2 x i64> [[INDICES:%.*]])40// CPP-CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]41//42svuint64_t test_svadrd_u64base_s64index(svuint64_t bases, svint64_t indices)43{44 return SVE_ACLE_FUNC(svadrd_,u64base_s64,index,)(bases, indices);45}46 47// CHECK-LABEL: @test_svadrd_u32base_u32index(48// CHECK-NEXT: entry:49// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.adrd.nxv4i32(<vscale x 4 x i32> [[BASES:%.*]], <vscale x 4 x i32> [[INDICES:%.*]])50// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]51//52// CPP-CHECK-LABEL: @_Z28test_svadrd_u32base_u32indexu12__SVUint32_tS_(53// CPP-CHECK-NEXT: entry:54// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.adrd.nxv4i32(<vscale x 4 x i32> [[BASES:%.*]], <vscale x 4 x i32> [[INDICES:%.*]])55// CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]56//57svuint32_t test_svadrd_u32base_u32index(svuint32_t bases, svuint32_t indices)58{59 return SVE_ACLE_FUNC(svadrd_,u32base_u32,index,)(bases, indices);60}61 62// CHECK-LABEL: @test_svadrd_u64base_u64index(63// CHECK-NEXT: entry:64// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.adrd.nxv2i64(<vscale x 2 x i64> [[BASES:%.*]], <vscale x 2 x i64> [[INDICES:%.*]])65// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]66//67// CPP-CHECK-LABEL: @_Z28test_svadrd_u64base_u64indexu12__SVUint64_tS_(68// CPP-CHECK-NEXT: entry:69// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.adrd.nxv2i64(<vscale x 2 x i64> [[BASES:%.*]], <vscale x 2 x i64> [[INDICES:%.*]])70// CPP-CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]71//72svuint64_t test_svadrd_u64base_u64index(svuint64_t bases, svuint64_t indices)73{74 return SVE_ACLE_FUNC(svadrd_,u64base_u64,index,)(bases, indices);75}76