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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py2// REQUIRES: aarch64-registered-target3// RUN: %clang_cc1 -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s4// RUN: %clang_cc1 -triple aarch64 -target-feature +ssve-fexpa -target-feature +sme2 -target-feature +sme -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s5// RUN: %clang_cc1 -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK6// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s7// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK8// RUN: %clang_cc1 -triple aarch64 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s9// RUN: %clang_cc1 -triple aarch64 -target-feature +ssve-fexpa -target-feature +sme2 -target-feature +sme -S -disable-O0-optnone -Werror -Wall -o /dev/null %s10#include <arm_sve.h>11 12#ifdef SVE_OVERLOADED_FORMS13// A simple used,unused... macro, long enough to represent any SVE builtin.14#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A315#else16#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A417#endif18 19#ifdef __ARM_FEATURE_SME20#define STREAMING __arm_streaming21#else22#define STREAMING23#endif24 25// CHECK-LABEL: @test_svexpa_f16(26// CHECK-NEXT: entry:27// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.fexpa.x.nxv8f16(<vscale x 8 x i16> [[OP:%.*]])28// CHECK-NEXT: ret <vscale x 8 x half> [[TMP0]]29//30// CPP-CHECK-LABEL: @_Z15test_svexpa_f16u12__SVUint16_t(31// CPP-CHECK-NEXT: entry:32// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.fexpa.x.nxv8f16(<vscale x 8 x i16> [[OP:%.*]])33// CPP-CHECK-NEXT: ret <vscale x 8 x half> [[TMP0]]34//35svfloat16_t test_svexpa_f16(svuint16_t op) STREAMING36{37 return SVE_ACLE_FUNC(svexpa,_f16,,)(op);38}39 40// CHECK-LABEL: @test_svexpa_f32(41// CHECK-NEXT: entry:42// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.fexpa.x.nxv4f32(<vscale x 4 x i32> [[OP:%.*]])43// CHECK-NEXT: ret <vscale x 4 x float> [[TMP0]]44//45// CPP-CHECK-LABEL: @_Z15test_svexpa_f32u12__SVUint32_t(46// CPP-CHECK-NEXT: entry:47// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.fexpa.x.nxv4f32(<vscale x 4 x i32> [[OP:%.*]])48// CPP-CHECK-NEXT: ret <vscale x 4 x float> [[TMP0]]49//50svfloat32_t test_svexpa_f32(svuint32_t op) STREAMING51{52 return SVE_ACLE_FUNC(svexpa,_f32,,)(op);53}54 55// CHECK-LABEL: @test_svexpa_f64(56// CHECK-NEXT: entry:57// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x double> @llvm.aarch64.sve.fexpa.x.nxv2f64(<vscale x 2 x i64> [[OP:%.*]])58// CHECK-NEXT: ret <vscale x 2 x double> [[TMP0]]59//60// CPP-CHECK-LABEL: @_Z15test_svexpa_f64u12__SVUint64_t(61// CPP-CHECK-NEXT: entry:62// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x double> @llvm.aarch64.sve.fexpa.x.nxv2f64(<vscale x 2 x i64> [[OP:%.*]])63// CPP-CHECK-NEXT: ret <vscale x 2 x double> [[TMP0]]64//65svfloat64_t test_svexpa_f64(svuint64_t op) STREAMING66{67 return SVE_ACLE_FUNC(svexpa,_f64,,)(op);68}69