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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py2// REQUIRES: aarch64-registered-target3// RUN: %clang_cc1 -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s4// RUN: %clang_cc1 -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK5// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s6// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK7// RUN: %clang_cc1 -triple aarch64 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s8// RUN: %clang_cc1 -triple aarch64 -target-feature +sme -S -disable-O0-optnone -Werror -Wall -o /dev/null %s9 10#include <arm_sve.h>11 12 13#if defined __ARM_FEATURE_SME14#define MODE_ATTR __arm_streaming15#else16#define MODE_ATTR17#endif18 19#ifdef SVE_OVERLOADED_FORMS20// A simple used,unused... macro, long enough to represent any SVE builtin.21#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A322#else23#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A424#endif25 26// CHECK-LABEL: @test_svminnmv_f16(27// CHECK-NEXT: entry:28// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])29// CHECK-NEXT: [[TMP1:%.*]] = tail call half @llvm.aarch64.sve.fminnmv.nxv8f16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x half> [[OP:%.*]])30// CHECK-NEXT: ret half [[TMP1]]31//32// CPP-CHECK-LABEL: @_Z17test_svminnmv_f16u10__SVBool_tu13__SVFloat16_t(33// CPP-CHECK-NEXT: entry:34// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])35// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call half @llvm.aarch64.sve.fminnmv.nxv8f16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x half> [[OP:%.*]])36// CPP-CHECK-NEXT: ret half [[TMP1]]37//38float16_t test_svminnmv_f16(svbool_t pg, svfloat16_t op) MODE_ATTR39{40 return SVE_ACLE_FUNC(svminnmv,_f16,,)(pg, op);41}42 43// CHECK-LABEL: @test_svminnmv_f32(44// CHECK-NEXT: entry:45// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]])46// CHECK-NEXT: [[TMP1:%.*]] = tail call float @llvm.aarch64.sve.fminnmv.nxv4f32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x float> [[OP:%.*]])47// CHECK-NEXT: ret float [[TMP1]]48//49// CPP-CHECK-LABEL: @_Z17test_svminnmv_f32u10__SVBool_tu13__SVFloat32_t(50// CPP-CHECK-NEXT: entry:51// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]])52// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call float @llvm.aarch64.sve.fminnmv.nxv4f32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x float> [[OP:%.*]])53// CPP-CHECK-NEXT: ret float [[TMP1]]54//55float32_t test_svminnmv_f32(svbool_t pg, svfloat32_t op) MODE_ATTR56{57 return SVE_ACLE_FUNC(svminnmv,_f32,,)(pg, op);58}59 60// CHECK-LABEL: @test_svminnmv_f64(61// CHECK-NEXT: entry:62// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]])63// CHECK-NEXT: [[TMP1:%.*]] = tail call double @llvm.aarch64.sve.fminnmv.nxv2f64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x double> [[OP:%.*]])64// CHECK-NEXT: ret double [[TMP1]]65//66// CPP-CHECK-LABEL: @_Z17test_svminnmv_f64u10__SVBool_tu13__SVFloat64_t(67// CPP-CHECK-NEXT: entry:68// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]])69// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call double @llvm.aarch64.sve.fminnmv.nxv2f64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x double> [[OP:%.*]])70// CPP-CHECK-NEXT: ret double [[TMP1]]71//72float64_t test_svminnmv_f64(svbool_t pg, svfloat64_t op) MODE_ATTR73{74 return SVE_ACLE_FUNC(svminnmv,_f64,,)(pg, op);75}76