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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py2// REQUIRES: aarch64-registered-target3// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s4// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK5// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s6// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK7// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s8// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -S -disable-O0-optnone -Werror -Wall -o /dev/null %s9 10#include <arm_sve.h>11 12#if defined __ARM_FEATURE_SME13#define MODE_ATTR __arm_streaming14#else15#define MODE_ATTR16#endif17 18#ifdef SVE_OVERLOADED_FORMS19// A simple used,unused... macro, long enough to represent any SVE builtin.20#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A321#else22#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A423#endif24 25// CHECK-LABEL: @test_svsel_s8(26// CHECK-NEXT: entry:27// CHECK-NEXT: [[TMP0:%.*]] = select <vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]]28// CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]29//30// CPP-CHECK-LABEL: @_Z13test_svsel_s8u10__SVBool_tu10__SVInt8_tS0_(31// CPP-CHECK-NEXT: entry:32// CPP-CHECK-NEXT: [[TMP0:%.*]] = select <vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]]33// CPP-CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]34//35svint8_t test_svsel_s8(svbool_t pg, svint8_t op1, svint8_t op2) MODE_ATTR36{37 return SVE_ACLE_FUNC(svsel,_s8,,)(pg, op1, op2);38}39 40// CHECK-LABEL: @test_svsel_s16(41// CHECK-NEXT: entry:42// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])43// CHECK-NEXT: [[TMP1:%.*]] = select <vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]]44// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP1]]45//46// CPP-CHECK-LABEL: @_Z14test_svsel_s16u10__SVBool_tu11__SVInt16_tS0_(47// CPP-CHECK-NEXT: entry:48// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])49// CPP-CHECK-NEXT: [[TMP1:%.*]] = select <vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]]50// CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP1]]51//52svint16_t test_svsel_s16(svbool_t pg, svint16_t op1, svint16_t op2) MODE_ATTR53{54 return SVE_ACLE_FUNC(svsel,_s16,,)(pg, op1, op2);55}56 57// CHECK-LABEL: @test_svsel_s32(58// CHECK-NEXT: entry:59// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]])60// CHECK-NEXT: [[TMP1:%.*]] = select <vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]]61// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP1]]62//63// CPP-CHECK-LABEL: @_Z14test_svsel_s32u10__SVBool_tu11__SVInt32_tS0_(64// CPP-CHECK-NEXT: entry:65// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]])66// CPP-CHECK-NEXT: [[TMP1:%.*]] = select <vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]]67// CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP1]]68//69svint32_t test_svsel_s32(svbool_t pg, svint32_t op1, svint32_t op2) MODE_ATTR70{71 return SVE_ACLE_FUNC(svsel,_s32,,)(pg, op1, op2);72}73 74// CHECK-LABEL: @test_svsel_s64(75// CHECK-NEXT: entry:76// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]])77// CHECK-NEXT: [[TMP1:%.*]] = select <vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]]78// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP1]]79//80// CPP-CHECK-LABEL: @_Z14test_svsel_s64u10__SVBool_tu11__SVInt64_tS0_(81// CPP-CHECK-NEXT: entry:82// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]])83// CPP-CHECK-NEXT: [[TMP1:%.*]] = select <vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]]84// CPP-CHECK-NEXT: ret <vscale x 2 x i64> [[TMP1]]85//86svint64_t test_svsel_s64(svbool_t pg, svint64_t op1, svint64_t op2) MODE_ATTR87{88 return SVE_ACLE_FUNC(svsel,_s64,,)(pg, op1, op2);89}90 91// CHECK-LABEL: @test_svsel_u8(92// CHECK-NEXT: entry:93// CHECK-NEXT: [[TMP0:%.*]] = select <vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]]94// CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]95//96// CPP-CHECK-LABEL: @_Z13test_svsel_u8u10__SVBool_tu11__SVUint8_tS0_(97// CPP-CHECK-NEXT: entry:98// CPP-CHECK-NEXT: [[TMP0:%.*]] = select <vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]]99// CPP-CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]100//101svuint8_t test_svsel_u8(svbool_t pg, svuint8_t op1, svuint8_t op2) MODE_ATTR102{103 return SVE_ACLE_FUNC(svsel,_u8,,)(pg, op1, op2);104}105 106// CHECK-LABEL: @test_svsel_u16(107// CHECK-NEXT: entry:108// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])109// CHECK-NEXT: [[TMP1:%.*]] = select <vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]]110// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP1]]111//112// CPP-CHECK-LABEL: @_Z14test_svsel_u16u10__SVBool_tu12__SVUint16_tS0_(113// CPP-CHECK-NEXT: entry:114// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])115// CPP-CHECK-NEXT: [[TMP1:%.*]] = select <vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]]116// CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP1]]117//118svuint16_t test_svsel_u16(svbool_t pg, svuint16_t op1, svuint16_t op2) MODE_ATTR119{120 return SVE_ACLE_FUNC(svsel,_u16,,)(pg, op1, op2);121}122 123// CHECK-LABEL: @test_svsel_u32(124// CHECK-NEXT: entry:125// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]])126// CHECK-NEXT: [[TMP1:%.*]] = select <vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]]127// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP1]]128//129// CPP-CHECK-LABEL: @_Z14test_svsel_u32u10__SVBool_tu12__SVUint32_tS0_(130// CPP-CHECK-NEXT: entry:131// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]])132// CPP-CHECK-NEXT: [[TMP1:%.*]] = select <vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]]133// CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP1]]134//135svuint32_t test_svsel_u32(svbool_t pg, svuint32_t op1, svuint32_t op2) MODE_ATTR136{137 return SVE_ACLE_FUNC(svsel,_u32,,)(pg, op1, op2);138}139 140// CHECK-LABEL: @test_svsel_u64(141// CHECK-NEXT: entry:142// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]])143// CHECK-NEXT: [[TMP1:%.*]] = select <vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]]144// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP1]]145//146// CPP-CHECK-LABEL: @_Z14test_svsel_u64u10__SVBool_tu12__SVUint64_tS0_(147// CPP-CHECK-NEXT: entry:148// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]])149// CPP-CHECK-NEXT: [[TMP1:%.*]] = select <vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]]150// CPP-CHECK-NEXT: ret <vscale x 2 x i64> [[TMP1]]151//152svuint64_t test_svsel_u64(svbool_t pg, svuint64_t op1, svuint64_t op2) MODE_ATTR153{154 return SVE_ACLE_FUNC(svsel,_u64,,)(pg, op1, op2);155}156 157// CHECK-LABEL: @test_svsel_f16(158// CHECK-NEXT: entry:159// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])160// CHECK-NEXT: [[TMP1:%.*]] = select <vscale x 8 x i1> [[TMP0]], <vscale x 8 x half> [[OP1:%.*]], <vscale x 8 x half> [[OP2:%.*]]161// CHECK-NEXT: ret <vscale x 8 x half> [[TMP1]]162//163// CPP-CHECK-LABEL: @_Z14test_svsel_f16u10__SVBool_tu13__SVFloat16_tS0_(164// CPP-CHECK-NEXT: entry:165// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])166// CPP-CHECK-NEXT: [[TMP1:%.*]] = select <vscale x 8 x i1> [[TMP0]], <vscale x 8 x half> [[OP1:%.*]], <vscale x 8 x half> [[OP2:%.*]]167// CPP-CHECK-NEXT: ret <vscale x 8 x half> [[TMP1]]168//169svfloat16_t test_svsel_f16(svbool_t pg, svfloat16_t op1, svfloat16_t op2) MODE_ATTR170{171 return SVE_ACLE_FUNC(svsel,_f16,,)(pg, op1, op2);172}173 174// CHECK-LABEL: @test_svsel_f32(175// CHECK-NEXT: entry:176// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]])177// CHECK-NEXT: [[TMP1:%.*]] = select <vscale x 4 x i1> [[TMP0]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]]178// CHECK-NEXT: ret <vscale x 4 x float> [[TMP1]]179//180// CPP-CHECK-LABEL: @_Z14test_svsel_f32u10__SVBool_tu13__SVFloat32_tS0_(181// CPP-CHECK-NEXT: entry:182// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]])183// CPP-CHECK-NEXT: [[TMP1:%.*]] = select <vscale x 4 x i1> [[TMP0]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]]184// CPP-CHECK-NEXT: ret <vscale x 4 x float> [[TMP1]]185//186svfloat32_t test_svsel_f32(svbool_t pg, svfloat32_t op1, svfloat32_t op2) MODE_ATTR187{188 return SVE_ACLE_FUNC(svsel,_f32,,)(pg, op1, op2);189}190 191// CHECK-LABEL: @test_svsel_f64(192// CHECK-NEXT: entry:193// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]])194// CHECK-NEXT: [[TMP1:%.*]] = select <vscale x 2 x i1> [[TMP0]], <vscale x 2 x double> [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]]195// CHECK-NEXT: ret <vscale x 2 x double> [[TMP1]]196//197// CPP-CHECK-LABEL: @_Z14test_svsel_f64u10__SVBool_tu13__SVFloat64_tS0_(198// CPP-CHECK-NEXT: entry:199// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]])200// CPP-CHECK-NEXT: [[TMP1:%.*]] = select <vscale x 2 x i1> [[TMP0]], <vscale x 2 x double> [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]]201// CPP-CHECK-NEXT: ret <vscale x 2 x double> [[TMP1]]202//203svfloat64_t test_svsel_f64(svbool_t pg, svfloat64_t op1, svfloat64_t op2) MODE_ATTR204{205 return SVE_ACLE_FUNC(svsel,_f64,,)(pg, op1, op2);206}207 208// CHECK-LABEL: @test_svsel_b(209// CHECK-NEXT: entry:210// CHECK-NEXT: [[TMP0:%.*]] = select <vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i1> [[OP1:%.*]], <vscale x 16 x i1> [[OP2:%.*]]211// CHECK-NEXT: ret <vscale x 16 x i1> [[TMP0]]212//213// CPP-CHECK-LABEL: @_Z12test_svsel_bu10__SVBool_tS_S_(214// CPP-CHECK-NEXT: entry:215// CPP-CHECK-NEXT: [[TMP0:%.*]] = select <vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i1> [[OP1:%.*]], <vscale x 16 x i1> [[OP2:%.*]]216// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP0]]217//218svbool_t test_svsel_b(svbool_t pg, svbool_t op1, svbool_t op2) MODE_ATTR219{220 return SVE_ACLE_FUNC(svsel,_b,,)(pg, op1, op2);221}222 223// CHECK-LABEL: @test_svsel_bf16(224// CHECK-NEXT: entry:225// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])226// CHECK-NEXT: [[TMP1:%.*]] = select <vscale x 8 x i1> [[TMP0]], <vscale x 8 x bfloat> [[OP1:%.*]], <vscale x 8 x bfloat> [[OP2:%.*]]227// CHECK-NEXT: ret <vscale x 8 x bfloat> [[TMP1]]228//229// CPP-CHECK-LABEL: @_Z15test_svsel_bf16u10__SVBool_tu14__SVBfloat16_tS0_(230// CPP-CHECK-NEXT: entry:231// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])232// CPP-CHECK-NEXT: [[TMP1:%.*]] = select <vscale x 8 x i1> [[TMP0]], <vscale x 8 x bfloat> [[OP1:%.*]], <vscale x 8 x bfloat> [[OP2:%.*]]233// CPP-CHECK-NEXT: ret <vscale x 8 x bfloat> [[TMP1]]234//235svbfloat16_t test_svsel_bf16(svbool_t pg, svbfloat16_t op1, svbfloat16_t op2) MODE_ATTR236{237 // expected-warning@+1 {{implicit declaration of function 'svsel_bf16'}}238 return SVE_ACLE_FUNC(svsel,_bf16,,)(pg, op1, op2);239}240