341 lines · c
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py2// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve \3// RUN: -disable-O0-optnone \4// RUN: -emit-llvm -o - %s | opt -S -passes=sroa | FileCheck %s5 6// REQUIRES: aarch64-registered-target7 8#include <arm_sve.h>9 10// AND11 12// CHECK-LABEL: @and_bool(13// CHECK-NEXT: entry:14// CHECK-NEXT: [[AND:%.*]] = and <vscale x 16 x i1> [[A:%.*]], [[B:%.*]]15// CHECK-NEXT: ret <vscale x 16 x i1> [[AND]]16//17svbool_t and_bool(svbool_t a, svbool_t b) {18 return a & b;19}20 21// CHECK-LABEL: @and_i8(22// CHECK-NEXT: entry:23// CHECK-NEXT: [[AND:%.*]] = and <vscale x 16 x i8> [[A:%.*]], [[B:%.*]]24// CHECK-NEXT: ret <vscale x 16 x i8> [[AND]]25//26svint8_t and_i8(svint8_t a, svint8_t b) {27 return a & b;28}29 30// CHECK-LABEL: @and_i16(31// CHECK-NEXT: entry:32// CHECK-NEXT: [[AND:%.*]] = and <vscale x 8 x i16> [[A:%.*]], [[B:%.*]]33// CHECK-NEXT: ret <vscale x 8 x i16> [[AND]]34//35svint16_t and_i16(svint16_t a, svint16_t b) {36 return a & b;37}38 39// CHECK-LABEL: @and_i32(40// CHECK-NEXT: entry:41// CHECK-NEXT: [[AND:%.*]] = and <vscale x 4 x i32> [[A:%.*]], [[B:%.*]]42// CHECK-NEXT: ret <vscale x 4 x i32> [[AND]]43//44svint32_t and_i32(svint32_t a, svint32_t b) {45 return a & b;46}47 48// CHECK-LABEL: @and_i64(49// CHECK-NEXT: entry:50// CHECK-NEXT: [[AND:%.*]] = and <vscale x 2 x i64> [[A:%.*]], [[B:%.*]]51// CHECK-NEXT: ret <vscale x 2 x i64> [[AND]]52//53svint64_t and_i64(svint64_t a, svint64_t b) {54 return a & b;55}56 57// CHECK-LABEL: @and_u8(58// CHECK-NEXT: entry:59// CHECK-NEXT: [[AND:%.*]] = and <vscale x 16 x i8> [[A:%.*]], [[B:%.*]]60// CHECK-NEXT: ret <vscale x 16 x i8> [[AND]]61//62svuint8_t and_u8(svuint8_t a, svuint8_t b) {63 return a & b;64}65 66// CHECK-LABEL: @and_u16(67// CHECK-NEXT: entry:68// CHECK-NEXT: [[AND:%.*]] = and <vscale x 8 x i16> [[A:%.*]], [[B:%.*]]69// CHECK-NEXT: ret <vscale x 8 x i16> [[AND]]70//71svuint16_t and_u16(svuint16_t a, svuint16_t b) {72 return a & b;73}74 75// CHECK-LABEL: @and_u32(76// CHECK-NEXT: entry:77// CHECK-NEXT: [[AND:%.*]] = and <vscale x 4 x i32> [[A:%.*]], [[B:%.*]]78// CHECK-NEXT: ret <vscale x 4 x i32> [[AND]]79//80svuint32_t and_u32(svuint32_t a, svuint32_t b) {81 return a & b;82}83 84// CHECK-LABEL: @and_u64(85// CHECK-NEXT: entry:86// CHECK-NEXT: [[AND:%.*]] = and <vscale x 2 x i64> [[A:%.*]], [[B:%.*]]87// CHECK-NEXT: ret <vscale x 2 x i64> [[AND]]88//89svuint64_t and_u64(svuint64_t a, svuint64_t b) {90 return a & b;91}92 93// OR94 95// CHECK-LABEL: @or_bool(96// CHECK-NEXT: entry:97// CHECK-NEXT: [[OR:%.*]] = or <vscale x 16 x i1> [[A:%.*]], [[B:%.*]]98// CHECK-NEXT: ret <vscale x 16 x i1> [[OR]]99//100svbool_t or_bool(svbool_t a, svbool_t b) {101 return a | b;102}103 104// CHECK-LABEL: @or_i8(105// CHECK-NEXT: entry:106// CHECK-NEXT: [[OR:%.*]] = or <vscale x 16 x i8> [[A:%.*]], [[B:%.*]]107// CHECK-NEXT: ret <vscale x 16 x i8> [[OR]]108//109svint8_t or_i8(svint8_t a, svint8_t b) {110 return a | b;111}112 113// CHECK-LABEL: @or_i16(114// CHECK-NEXT: entry:115// CHECK-NEXT: [[OR:%.*]] = or <vscale x 8 x i16> [[A:%.*]], [[B:%.*]]116// CHECK-NEXT: ret <vscale x 8 x i16> [[OR]]117//118svint16_t or_i16(svint16_t a, svint16_t b) {119 return a | b;120}121 122// CHECK-LABEL: @or_i32(123// CHECK-NEXT: entry:124// CHECK-NEXT: [[OR:%.*]] = or <vscale x 4 x i32> [[A:%.*]], [[B:%.*]]125// CHECK-NEXT: ret <vscale x 4 x i32> [[OR]]126//127svint32_t or_i32(svint32_t a, svint32_t b) {128 return a | b;129}130 131// CHECK-LABEL: @or_i64(132// CHECK-NEXT: entry:133// CHECK-NEXT: [[OR:%.*]] = or <vscale x 2 x i64> [[A:%.*]], [[B:%.*]]134// CHECK-NEXT: ret <vscale x 2 x i64> [[OR]]135//136svint64_t or_i64(svint64_t a, svint64_t b) {137 return a | b;138}139 140// CHECK-LABEL: @or_u8(141// CHECK-NEXT: entry:142// CHECK-NEXT: [[OR:%.*]] = or <vscale x 16 x i8> [[A:%.*]], [[B:%.*]]143// CHECK-NEXT: ret <vscale x 16 x i8> [[OR]]144//145svuint8_t or_u8(svuint8_t a, svuint8_t b) {146 return a | b;147}148 149// CHECK-LABEL: @or_u16(150// CHECK-NEXT: entry:151// CHECK-NEXT: [[OR:%.*]] = or <vscale x 8 x i16> [[A:%.*]], [[B:%.*]]152// CHECK-NEXT: ret <vscale x 8 x i16> [[OR]]153//154svuint16_t or_u16(svuint16_t a, svuint16_t b) {155 return a | b;156}157 158// CHECK-LABEL: @or_u32(159// CHECK-NEXT: entry:160// CHECK-NEXT: [[OR:%.*]] = or <vscale x 4 x i32> [[A:%.*]], [[B:%.*]]161// CHECK-NEXT: ret <vscale x 4 x i32> [[OR]]162//163svuint32_t or_u32(svuint32_t a, svuint32_t b) {164 return a | b;165}166 167// CHECK-LABEL: @or_u64(168// CHECK-NEXT: entry:169// CHECK-NEXT: [[OR:%.*]] = or <vscale x 2 x i64> [[A:%.*]], [[B:%.*]]170// CHECK-NEXT: ret <vscale x 2 x i64> [[OR]]171//172svuint64_t or_u64(svuint64_t a, svuint64_t b) {173 return a | b;174}175 176// XOR177 178// CHECK-LABEL: @xor_bool(179// CHECK-NEXT: entry:180// CHECK-NEXT: [[XOR:%.*]] = xor <vscale x 16 x i1> [[A:%.*]], [[B:%.*]]181// CHECK-NEXT: ret <vscale x 16 x i1> [[XOR]]182//183svbool_t xor_bool(svbool_t a, svbool_t b) {184 return a ^ b;185}186 187// CHECK-LABEL: @xor_i8(188// CHECK-NEXT: entry:189// CHECK-NEXT: [[XOR:%.*]] = xor <vscale x 16 x i8> [[A:%.*]], [[B:%.*]]190// CHECK-NEXT: ret <vscale x 16 x i8> [[XOR]]191//192svint8_t xor_i8(svint8_t a, svint8_t b) {193 return a ^ b;194}195 196// CHECK-LABEL: @xor_i16(197// CHECK-NEXT: entry:198// CHECK-NEXT: [[XOR:%.*]] = xor <vscale x 8 x i16> [[A:%.*]], [[B:%.*]]199// CHECK-NEXT: ret <vscale x 8 x i16> [[XOR]]200//201svint16_t xor_i16(svint16_t a, svint16_t b) {202 return a ^ b;203}204 205// CHECK-LABEL: @xor_i32(206// CHECK-NEXT: entry:207// CHECK-NEXT: [[XOR:%.*]] = xor <vscale x 4 x i32> [[A:%.*]], [[B:%.*]]208// CHECK-NEXT: ret <vscale x 4 x i32> [[XOR]]209//210svint32_t xor_i32(svint32_t a, svint32_t b) {211 return a ^ b;212}213 214// CHECK-LABEL: @xor_i64(215// CHECK-NEXT: entry:216// CHECK-NEXT: [[XOR:%.*]] = xor <vscale x 2 x i64> [[A:%.*]], [[B:%.*]]217// CHECK-NEXT: ret <vscale x 2 x i64> [[XOR]]218//219svint64_t xor_i64(svint64_t a, svint64_t b) {220 return a ^ b;221}222 223// CHECK-LABEL: @xor_u8(224// CHECK-NEXT: entry:225// CHECK-NEXT: [[XOR:%.*]] = xor <vscale x 16 x i8> [[A:%.*]], [[B:%.*]]226// CHECK-NEXT: ret <vscale x 16 x i8> [[XOR]]227//228svuint8_t xor_u8(svuint8_t a, svuint8_t b) {229 return a ^ b;230}231 232// CHECK-LABEL: @xor_u16(233// CHECK-NEXT: entry:234// CHECK-NEXT: [[XOR:%.*]] = xor <vscale x 8 x i16> [[A:%.*]], [[B:%.*]]235// CHECK-NEXT: ret <vscale x 8 x i16> [[XOR]]236//237svuint16_t xor_u16(svuint16_t a, svuint16_t b) {238 return a ^ b;239}240 241// CHECK-LABEL: @xor_u32(242// CHECK-NEXT: entry:243// CHECK-NEXT: [[XOR:%.*]] = xor <vscale x 4 x i32> [[A:%.*]], [[B:%.*]]244// CHECK-NEXT: ret <vscale x 4 x i32> [[XOR]]245//246svuint32_t xor_u32(svuint32_t a, svuint32_t b) {247 return a ^ b;248}249 250// CHECK-LABEL: @xor_u64(251// CHECK-NEXT: entry:252// CHECK-NEXT: [[XOR:%.*]] = xor <vscale x 2 x i64> [[A:%.*]], [[B:%.*]]253// CHECK-NEXT: ret <vscale x 2 x i64> [[XOR]]254//255svuint64_t xor_u64(svuint64_t a, svuint64_t b) {256 return a ^ b;257}258 259// NEG260 261// CHECK-LABEL: @neg_bool(262// CHECK-NEXT: entry:263// CHECK-NEXT: [[NOT:%.*]] = xor <vscale x 16 x i1> [[A:%.*]], splat (i1 true)264// CHECK-NEXT: ret <vscale x 16 x i1> [[NOT]]265//266svbool_t neg_bool(svbool_t a) {267 return ~a;268}269 270// CHECK-LABEL: @neg_i8(271// CHECK-NEXT: entry:272// CHECK-NEXT: [[NOT:%.*]] = xor <vscale x 16 x i8> [[A:%.*]], splat (i8 -1)273// CHECK-NEXT: ret <vscale x 16 x i8> [[NOT]]274//275svint8_t neg_i8(svint8_t a) {276 return ~a;277}278 279// CHECK-LABEL: @neg_i16(280// CHECK-NEXT: entry:281// CHECK-NEXT: [[NOT:%.*]] = xor <vscale x 8 x i16> [[A:%.*]], splat (i16 -1)282// CHECK-NEXT: ret <vscale x 8 x i16> [[NOT]]283//284svint16_t neg_i16(svint16_t a) {285 return ~a;286}287 288// CHECK-LABEL: @neg_i32(289// CHECK-NEXT: entry:290// CHECK-NEXT: [[NOT:%.*]] = xor <vscale x 4 x i32> [[A:%.*]], splat (i32 -1)291// CHECK-NEXT: ret <vscale x 4 x i32> [[NOT]]292//293svint32_t neg_i32(svint32_t a) {294 return ~a;295}296 297// CHECK-LABEL: @neg_i64(298// CHECK-NEXT: entry:299// CHECK-NEXT: [[NOT:%.*]] = xor <vscale x 2 x i64> [[A:%.*]], splat (i64 -1)300// CHECK-NEXT: ret <vscale x 2 x i64> [[NOT]]301//302svint64_t neg_i64(svint64_t a) {303 return ~a;304}305 306// CHECK-LABEL: @neg_u8(307// CHECK-NEXT: entry:308// CHECK-NEXT: [[NOT:%.*]] = xor <vscale x 16 x i8> [[A:%.*]], splat (i8 -1)309// CHECK-NEXT: ret <vscale x 16 x i8> [[NOT]]310//311svuint8_t neg_u8(svuint8_t a) {312 return ~a;313}314 315// CHECK-LABEL: @neg_u16(316// CHECK-NEXT: entry:317// CHECK-NEXT: [[NOT:%.*]] = xor <vscale x 8 x i16> [[A:%.*]], splat (i16 -1)318// CHECK-NEXT: ret <vscale x 8 x i16> [[NOT]]319//320svuint16_t neg_u16(svuint16_t a) {321 return ~a;322}323 324// CHECK-LABEL: @neg_u32(325// CHECK-NEXT: entry:326// CHECK-NEXT: [[NOT:%.*]] = xor <vscale x 4 x i32> [[A:%.*]], splat (i32 -1)327// CHECK-NEXT: ret <vscale x 4 x i32> [[NOT]]328//329svuint32_t neg_u32(svuint32_t a) {330 return ~a;331}332 333// CHECK-LABEL: @neg_u64(334// CHECK-NEXT: entry:335// CHECK-NEXT: [[NOT:%.*]] = xor <vscale x 2 x i64> [[A:%.*]], splat (i64 -1)336// CHECK-NEXT: ret <vscale x 2 x i64> [[NOT]]337//338svuint64_t neg_u64(svuint64_t a) {339 return ~a;340}341