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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py2// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s3// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -O1 -Werror -Wall -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefix=CPP-CHECK4// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -target-feature +sve2 -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s5// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -target-feature +sve2 -O1 -Werror -Wall -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefix=CPP-CHECK6 7// REQUIRES: aarch64-registered-target8 9#include <arm_sve.h>10 11#ifdef SVE_OVERLOADED_FORMS12// A simple used,unused... macro, long enough to represent any SVE builtin.13#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A314#else15#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A416#endif17 18// CHECK-LABEL: @test_svcmla_s8(19// CHECK-NEXT: entry:20// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.cmla.x.nxv16i8(<vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i8> [[OP3:%.*]], i32 0)21// CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]22//23// CPP-CHECK-LABEL: @_Z14test_svcmla_s8u10__SVInt8_tS_S_(24// CPP-CHECK-NEXT: entry:25// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.cmla.x.nxv16i8(<vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i8> [[OP3:%.*]], i32 0)26// CPP-CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]27//28svint8_t test_svcmla_s8(svint8_t op1, svint8_t op2, svint8_t op3)29{30 return SVE_ACLE_FUNC(svcmla,_s8,,)(op1, op2, op3, 0);31}32 33// CHECK-LABEL: @test_svcmla_s8_1(34// CHECK-NEXT: entry:35// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.cmla.x.nxv16i8(<vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i8> [[OP3:%.*]], i32 90)36// CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]37//38// CPP-CHECK-LABEL: @_Z16test_svcmla_s8_1u10__SVInt8_tS_S_(39// CPP-CHECK-NEXT: entry:40// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.cmla.x.nxv16i8(<vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i8> [[OP3:%.*]], i32 90)41// CPP-CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]42//43svint8_t test_svcmla_s8_1(svint8_t op1, svint8_t op2, svint8_t op3)44{45 return SVE_ACLE_FUNC(svcmla,_s8,,)(op1, op2, op3, 90);46}47 48// CHECK-LABEL: @test_svcmla_s8_2(49// CHECK-NEXT: entry:50// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.cmla.x.nxv16i8(<vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i8> [[OP3:%.*]], i32 180)51// CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]52//53// CPP-CHECK-LABEL: @_Z16test_svcmla_s8_2u10__SVInt8_tS_S_(54// CPP-CHECK-NEXT: entry:55// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.cmla.x.nxv16i8(<vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i8> [[OP3:%.*]], i32 180)56// CPP-CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]57//58svint8_t test_svcmla_s8_2(svint8_t op1, svint8_t op2, svint8_t op3)59{60 return SVE_ACLE_FUNC(svcmla,_s8,,)(op1, op2, op3, 180);61}62 63// CHECK-LABEL: @test_svcmla_s8_3(64// CHECK-NEXT: entry:65// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.cmla.x.nxv16i8(<vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i8> [[OP3:%.*]], i32 270)66// CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]67//68// CPP-CHECK-LABEL: @_Z16test_svcmla_s8_3u10__SVInt8_tS_S_(69// CPP-CHECK-NEXT: entry:70// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.cmla.x.nxv16i8(<vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i8> [[OP3:%.*]], i32 270)71// CPP-CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]72//73svint8_t test_svcmla_s8_3(svint8_t op1, svint8_t op2, svint8_t op3)74{75 return SVE_ACLE_FUNC(svcmla,_s8,,)(op1, op2, op3, 270);76}77 78// CHECK-LABEL: @test_svcmla_s16(79// CHECK-NEXT: entry:80// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.cmla.x.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[OP3:%.*]], i32 0)81// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]82//83// CPP-CHECK-LABEL: @_Z15test_svcmla_s16u11__SVInt16_tS_S_(84// CPP-CHECK-NEXT: entry:85// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.cmla.x.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[OP3:%.*]], i32 0)86// CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]87//88svint16_t test_svcmla_s16(svint16_t op1, svint16_t op2, svint16_t op3)89{90 return SVE_ACLE_FUNC(svcmla,_s16,,)(op1, op2, op3, 0);91}92 93// CHECK-LABEL: @test_svcmla_s16_1(94// CHECK-NEXT: entry:95// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.cmla.x.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[OP3:%.*]], i32 90)96// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]97//98// CPP-CHECK-LABEL: @_Z17test_svcmla_s16_1u11__SVInt16_tS_S_(99// CPP-CHECK-NEXT: entry:100// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.cmla.x.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[OP3:%.*]], i32 90)101// CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]102//103svint16_t test_svcmla_s16_1(svint16_t op1, svint16_t op2, svint16_t op3)104{105 return SVE_ACLE_FUNC(svcmla,_s16,,)(op1, op2, op3, 90);106}107 108// CHECK-LABEL: @test_svcmla_s16_2(109// CHECK-NEXT: entry:110// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.cmla.x.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[OP3:%.*]], i32 180)111// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]112//113// CPP-CHECK-LABEL: @_Z17test_svcmla_s16_2u11__SVInt16_tS_S_(114// CPP-CHECK-NEXT: entry:115// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.cmla.x.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[OP3:%.*]], i32 180)116// CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]117//118svint16_t test_svcmla_s16_2(svint16_t op1, svint16_t op2, svint16_t op3)119{120 return SVE_ACLE_FUNC(svcmla,_s16,,)(op1, op2, op3, 180);121}122 123// CHECK-LABEL: @test_svcmla_s16_3(124// CHECK-NEXT: entry:125// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.cmla.x.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[OP3:%.*]], i32 270)126// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]127//128// CPP-CHECK-LABEL: @_Z17test_svcmla_s16_3u11__SVInt16_tS_S_(129// CPP-CHECK-NEXT: entry:130// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.cmla.x.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[OP3:%.*]], i32 270)131// CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]132//133svint16_t test_svcmla_s16_3(svint16_t op1, svint16_t op2, svint16_t op3)134{135 return SVE_ACLE_FUNC(svcmla,_s16,,)(op1, op2, op3, 270);136}137 138// CHECK-LABEL: @test_svcmla_s32(139// CHECK-NEXT: entry:140// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.cmla.x.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i32> [[OP3:%.*]], i32 0)141// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]142//143// CPP-CHECK-LABEL: @_Z15test_svcmla_s32u11__SVInt32_tS_S_(144// CPP-CHECK-NEXT: entry:145// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.cmla.x.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i32> [[OP3:%.*]], i32 0)146// CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]147//148svint32_t test_svcmla_s32(svint32_t op1, svint32_t op2, svint32_t op3)149{150 return SVE_ACLE_FUNC(svcmla,_s32,,)(op1, op2, op3, 0);151}152 153// CHECK-LABEL: @test_svcmla_s32_1(154// CHECK-NEXT: entry:155// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.cmla.x.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i32> [[OP3:%.*]], i32 90)156// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]157//158// CPP-CHECK-LABEL: @_Z17test_svcmla_s32_1u11__SVInt32_tS_S_(159// CPP-CHECK-NEXT: entry:160// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.cmla.x.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i32> [[OP3:%.*]], i32 90)161// CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]162//163svint32_t test_svcmla_s32_1(svint32_t op1, svint32_t op2, svint32_t op3)164{165 return SVE_ACLE_FUNC(svcmla,_s32,,)(op1, op2, op3, 90);166}167 168// CHECK-LABEL: @test_svcmla_s32_2(169// CHECK-NEXT: entry:170// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.cmla.x.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i32> [[OP3:%.*]], i32 180)171// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]172//173// CPP-CHECK-LABEL: @_Z17test_svcmla_s32_2u11__SVInt32_tS_S_(174// CPP-CHECK-NEXT: entry:175// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.cmla.x.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i32> [[OP3:%.*]], i32 180)176// CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]177//178svint32_t test_svcmla_s32_2(svint32_t op1, svint32_t op2, svint32_t op3)179{180 return SVE_ACLE_FUNC(svcmla,_s32,,)(op1, op2, op3, 180);181}182 183// CHECK-LABEL: @test_svcmla_s32_3(184// CHECK-NEXT: entry:185// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.cmla.x.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i32> [[OP3:%.*]], i32 270)186// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]187//188// CPP-CHECK-LABEL: @_Z17test_svcmla_s32_3u11__SVInt32_tS_S_(189// CPP-CHECK-NEXT: entry:190// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.cmla.x.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i32> [[OP3:%.*]], i32 270)191// CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]192//193svint32_t test_svcmla_s32_3(svint32_t op1, svint32_t op2, svint32_t op3)194{195 return SVE_ACLE_FUNC(svcmla,_s32,,)(op1, op2, op3, 270);196}197 198// CHECK-LABEL: @test_svcmla_s64(199// CHECK-NEXT: entry:200// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.cmla.x.nxv2i64(<vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i64> [[OP3:%.*]], i32 0)201// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]202//203// CPP-CHECK-LABEL: @_Z15test_svcmla_s64u11__SVInt64_tS_S_(204// CPP-CHECK-NEXT: entry:205// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.cmla.x.nxv2i64(<vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i64> [[OP3:%.*]], i32 0)206// CPP-CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]207//208svint64_t test_svcmla_s64(svint64_t op1, svint64_t op2, svint64_t op3)209{210 return SVE_ACLE_FUNC(svcmla,_s64,,)(op1, op2, op3, 0);211}212 213// CHECK-LABEL: @test_svcmla_s64_1(214// CHECK-NEXT: entry:215// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.cmla.x.nxv2i64(<vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i64> [[OP3:%.*]], i32 90)216// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]217//218// CPP-CHECK-LABEL: @_Z17test_svcmla_s64_1u11__SVInt64_tS_S_(219// CPP-CHECK-NEXT: entry:220// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.cmla.x.nxv2i64(<vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i64> [[OP3:%.*]], i32 90)221// CPP-CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]222//223svint64_t test_svcmla_s64_1(svint64_t op1, svint64_t op2, svint64_t op3)224{225 return SVE_ACLE_FUNC(svcmla,_s64,,)(op1, op2, op3, 90);226}227 228// CHECK-LABEL: @test_svcmla_s64_2(229// CHECK-NEXT: entry:230// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.cmla.x.nxv2i64(<vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i64> [[OP3:%.*]], i32 180)231// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]232//233// CPP-CHECK-LABEL: @_Z17test_svcmla_s64_2u11__SVInt64_tS_S_(234// CPP-CHECK-NEXT: entry:235// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.cmla.x.nxv2i64(<vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i64> [[OP3:%.*]], i32 180)236// CPP-CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]237//238svint64_t test_svcmla_s64_2(svint64_t op1, svint64_t op2, svint64_t op3)239{240 return SVE_ACLE_FUNC(svcmla,_s64,,)(op1, op2, op3, 180);241}242 243// CHECK-LABEL: @test_svcmla_s64_3(244// CHECK-NEXT: entry:245// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.cmla.x.nxv2i64(<vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i64> [[OP3:%.*]], i32 270)246// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]247//248// CPP-CHECK-LABEL: @_Z17test_svcmla_s64_3u11__SVInt64_tS_S_(249// CPP-CHECK-NEXT: entry:250// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.cmla.x.nxv2i64(<vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i64> [[OP3:%.*]], i32 270)251// CPP-CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]252//253svint64_t test_svcmla_s64_3(svint64_t op1, svint64_t op2, svint64_t op3)254{255 return SVE_ACLE_FUNC(svcmla,_s64,,)(op1, op2, op3, 270);256}257 258// CHECK-LABEL: @test_svcmla_u8(259// CHECK-NEXT: entry:260// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.cmla.x.nxv16i8(<vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i8> [[OP3:%.*]], i32 0)261// CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]262//263// CPP-CHECK-LABEL: @_Z14test_svcmla_u8u11__SVUint8_tS_S_(264// CPP-CHECK-NEXT: entry:265// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.cmla.x.nxv16i8(<vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i8> [[OP3:%.*]], i32 0)266// CPP-CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]267//268svuint8_t test_svcmla_u8(svuint8_t op1, svuint8_t op2, svuint8_t op3)269{270 return SVE_ACLE_FUNC(svcmla,_u8,,)(op1, op2, op3, 0);271}272 273// CHECK-LABEL: @test_svcmla_u8_1(274// CHECK-NEXT: entry:275// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.cmla.x.nxv16i8(<vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i8> [[OP3:%.*]], i32 90)276// CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]277//278// CPP-CHECK-LABEL: @_Z16test_svcmla_u8_1u11__SVUint8_tS_S_(279// CPP-CHECK-NEXT: entry:280// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.cmla.x.nxv16i8(<vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i8> [[OP3:%.*]], i32 90)281// CPP-CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]282//283svuint8_t test_svcmla_u8_1(svuint8_t op1, svuint8_t op2, svuint8_t op3)284{285 return SVE_ACLE_FUNC(svcmla,_u8,,)(op1, op2, op3, 90);286}287 288// CHECK-LABEL: @test_svcmla_u8_2(289// CHECK-NEXT: entry:290// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.cmla.x.nxv16i8(<vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i8> [[OP3:%.*]], i32 180)291// CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]292//293// CPP-CHECK-LABEL: @_Z16test_svcmla_u8_2u11__SVUint8_tS_S_(294// CPP-CHECK-NEXT: entry:295// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.cmla.x.nxv16i8(<vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i8> [[OP3:%.*]], i32 180)296// CPP-CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]297//298svuint8_t test_svcmla_u8_2(svuint8_t op1, svuint8_t op2, svuint8_t op3)299{300 return SVE_ACLE_FUNC(svcmla,_u8,,)(op1, op2, op3, 180);301}302 303// CHECK-LABEL: @test_svcmla_u8_3(304// CHECK-NEXT: entry:305// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.cmla.x.nxv16i8(<vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i8> [[OP3:%.*]], i32 270)306// CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]307//308// CPP-CHECK-LABEL: @_Z16test_svcmla_u8_3u11__SVUint8_tS_S_(309// CPP-CHECK-NEXT: entry:310// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.cmla.x.nxv16i8(<vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i8> [[OP3:%.*]], i32 270)311// CPP-CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]312//313svuint8_t test_svcmla_u8_3(svuint8_t op1, svuint8_t op2, svuint8_t op3)314{315 return SVE_ACLE_FUNC(svcmla,_u8,,)(op1, op2, op3, 270);316}317 318// CHECK-LABEL: @test_svcmla_u16(319// CHECK-NEXT: entry:320// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.cmla.x.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[OP3:%.*]], i32 0)321// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]322//323// CPP-CHECK-LABEL: @_Z15test_svcmla_u16u12__SVUint16_tS_S_(324// CPP-CHECK-NEXT: entry:325// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.cmla.x.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[OP3:%.*]], i32 0)326// CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]327//328svuint16_t test_svcmla_u16(svuint16_t op1, svuint16_t op2, svuint16_t op3)329{330 return SVE_ACLE_FUNC(svcmla,_u16,,)(op1, op2, op3, 0);331}332 333// CHECK-LABEL: @test_svcmla_u16_1(334// CHECK-NEXT: entry:335// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.cmla.x.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[OP3:%.*]], i32 90)336// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]337//338// CPP-CHECK-LABEL: @_Z17test_svcmla_u16_1u12__SVUint16_tS_S_(339// CPP-CHECK-NEXT: entry:340// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.cmla.x.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[OP3:%.*]], i32 90)341// CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]342//343svuint16_t test_svcmla_u16_1(svuint16_t op1, svuint16_t op2, svuint16_t op3)344{345 return SVE_ACLE_FUNC(svcmla,_u16,,)(op1, op2, op3, 90);346}347 348// CHECK-LABEL: @test_svcmla_u16_2(349// CHECK-NEXT: entry:350// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.cmla.x.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[OP3:%.*]], i32 180)351// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]352//353// CPP-CHECK-LABEL: @_Z17test_svcmla_u16_2u12__SVUint16_tS_S_(354// CPP-CHECK-NEXT: entry:355// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.cmla.x.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[OP3:%.*]], i32 180)356// CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]357//358svuint16_t test_svcmla_u16_2(svuint16_t op1, svuint16_t op2, svuint16_t op3)359{360 return SVE_ACLE_FUNC(svcmla,_u16,,)(op1, op2, op3, 180);361}362 363// CHECK-LABEL: @test_svcmla_u16_3(364// CHECK-NEXT: entry:365// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.cmla.x.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[OP3:%.*]], i32 270)366// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]367//368// CPP-CHECK-LABEL: @_Z17test_svcmla_u16_3u12__SVUint16_tS_S_(369// CPP-CHECK-NEXT: entry:370// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.cmla.x.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[OP3:%.*]], i32 270)371// CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]372//373svuint16_t test_svcmla_u16_3(svuint16_t op1, svuint16_t op2, svuint16_t op3)374{375 return SVE_ACLE_FUNC(svcmla,_u16,,)(op1, op2, op3, 270);376}377 378// CHECK-LABEL: @test_svcmla_u32(379// CHECK-NEXT: entry:380// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.cmla.x.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i32> [[OP3:%.*]], i32 0)381// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]382//383// CPP-CHECK-LABEL: @_Z15test_svcmla_u32u12__SVUint32_tS_S_(384// CPP-CHECK-NEXT: entry:385// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.cmla.x.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i32> [[OP3:%.*]], i32 0)386// CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]387//388svuint32_t test_svcmla_u32(svuint32_t op1, svuint32_t op2, svuint32_t op3)389{390 return SVE_ACLE_FUNC(svcmla,_u32,,)(op1, op2, op3, 0);391}392 393// CHECK-LABEL: @test_svcmla_u32_1(394// CHECK-NEXT: entry:395// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.cmla.x.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i32> [[OP3:%.*]], i32 90)396// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]397//398// CPP-CHECK-LABEL: @_Z17test_svcmla_u32_1u12__SVUint32_tS_S_(399// CPP-CHECK-NEXT: entry:400// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.cmla.x.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i32> [[OP3:%.*]], i32 90)401// CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]402//403svuint32_t test_svcmla_u32_1(svuint32_t op1, svuint32_t op2, svuint32_t op3)404{405 return SVE_ACLE_FUNC(svcmla,_u32,,)(op1, op2, op3, 90);406}407 408// CHECK-LABEL: @test_svcmla_u32_2(409// CHECK-NEXT: entry:410// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.cmla.x.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i32> [[OP3:%.*]], i32 180)411// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]412//413// CPP-CHECK-LABEL: @_Z17test_svcmla_u32_2u12__SVUint32_tS_S_(414// CPP-CHECK-NEXT: entry:415// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.cmla.x.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i32> [[OP3:%.*]], i32 180)416// CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]417//418svuint32_t test_svcmla_u32_2(svuint32_t op1, svuint32_t op2, svuint32_t op3)419{420 return SVE_ACLE_FUNC(svcmla,_u32,,)(op1, op2, op3, 180);421}422 423// CHECK-LABEL: @test_svcmla_u32_3(424// CHECK-NEXT: entry:425// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.cmla.x.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i32> [[OP3:%.*]], i32 270)426// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]427//428// CPP-CHECK-LABEL: @_Z17test_svcmla_u32_3u12__SVUint32_tS_S_(429// CPP-CHECK-NEXT: entry:430// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.cmla.x.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i32> [[OP3:%.*]], i32 270)431// CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]432//433svuint32_t test_svcmla_u32_3(svuint32_t op1, svuint32_t op2, svuint32_t op3)434{435 return SVE_ACLE_FUNC(svcmla,_u32,,)(op1, op2, op3, 270);436}437 438// CHECK-LABEL: @test_svcmla_u64(439// CHECK-NEXT: entry:440// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.cmla.x.nxv2i64(<vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i64> [[OP3:%.*]], i32 0)441// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]442//443// CPP-CHECK-LABEL: @_Z15test_svcmla_u64u12__SVUint64_tS_S_(444// CPP-CHECK-NEXT: entry:445// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.cmla.x.nxv2i64(<vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i64> [[OP3:%.*]], i32 0)446// CPP-CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]447//448svuint64_t test_svcmla_u64(svuint64_t op1, svuint64_t op2, svuint64_t op3)449{450 return SVE_ACLE_FUNC(svcmla,_u64,,)(op1, op2, op3, 0);451}452 453// CHECK-LABEL: @test_svcmla_u64_1(454// CHECK-NEXT: entry:455// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.cmla.x.nxv2i64(<vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i64> [[OP3:%.*]], i32 90)456// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]457//458// CPP-CHECK-LABEL: @_Z17test_svcmla_u64_1u12__SVUint64_tS_S_(459// CPP-CHECK-NEXT: entry:460// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.cmla.x.nxv2i64(<vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i64> [[OP3:%.*]], i32 90)461// CPP-CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]462//463svuint64_t test_svcmla_u64_1(svuint64_t op1, svuint64_t op2, svuint64_t op3)464{465 return SVE_ACLE_FUNC(svcmla,_u64,,)(op1, op2, op3, 90);466}467 468// CHECK-LABEL: @test_svcmla_u64_2(469// CHECK-NEXT: entry:470// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.cmla.x.nxv2i64(<vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i64> [[OP3:%.*]], i32 180)471// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]472//473// CPP-CHECK-LABEL: @_Z17test_svcmla_u64_2u12__SVUint64_tS_S_(474// CPP-CHECK-NEXT: entry:475// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.cmla.x.nxv2i64(<vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i64> [[OP3:%.*]], i32 180)476// CPP-CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]477//478svuint64_t test_svcmla_u64_2(svuint64_t op1, svuint64_t op2, svuint64_t op3)479{480 return SVE_ACLE_FUNC(svcmla,_u64,,)(op1, op2, op3, 180);481}482 483// CHECK-LABEL: @test_svcmla_u64_3(484// CHECK-NEXT: entry:485// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.cmla.x.nxv2i64(<vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i64> [[OP3:%.*]], i32 270)486// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]487//488// CPP-CHECK-LABEL: @_Z17test_svcmla_u64_3u12__SVUint64_tS_S_(489// CPP-CHECK-NEXT: entry:490// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.cmla.x.nxv2i64(<vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i64> [[OP3:%.*]], i32 270)491// CPP-CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]492//493svuint64_t test_svcmla_u64_3(svuint64_t op1, svuint64_t op2, svuint64_t op3)494{495 return SVE_ACLE_FUNC(svcmla,_u64,,)(op1, op2, op3, 270);496}497 498// CHECK-LABEL: @test_svcmla_lane_s16(499// CHECK-NEXT: entry:500// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.cmla.lane.x.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[OP3:%.*]], i32 0, i32 90)501// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]502//503// CPP-CHECK-LABEL: @_Z20test_svcmla_lane_s16u11__SVInt16_tS_S_(504// CPP-CHECK-NEXT: entry:505// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.cmla.lane.x.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[OP3:%.*]], i32 0, i32 90)506// CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]507//508svint16_t test_svcmla_lane_s16(svint16_t op1, svint16_t op2, svint16_t op3)509{510 return SVE_ACLE_FUNC(svcmla_lane,_s16,,)(op1, op2, op3, 0, 90);511}512 513// CHECK-LABEL: @test_svcmla_lane_s16_1(514// CHECK-NEXT: entry:515// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.cmla.lane.x.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[OP3:%.*]], i32 3, i32 180)516// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]517//518// CPP-CHECK-LABEL: @_Z22test_svcmla_lane_s16_1u11__SVInt16_tS_S_(519// CPP-CHECK-NEXT: entry:520// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.cmla.lane.x.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[OP3:%.*]], i32 3, i32 180)521// CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]522//523svint16_t test_svcmla_lane_s16_1(svint16_t op1, svint16_t op2, svint16_t op3)524{525 return SVE_ACLE_FUNC(svcmla_lane,_s16,,)(op1, op2, op3, 3, 180);526}527 528// CHECK-LABEL: @test_svcmla_lane_s32(529// CHECK-NEXT: entry:530// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.cmla.lane.x.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i32> [[OP3:%.*]], i32 0, i32 270)531// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]532//533// CPP-CHECK-LABEL: @_Z20test_svcmla_lane_s32u11__SVInt32_tS_S_(534// CPP-CHECK-NEXT: entry:535// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.cmla.lane.x.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i32> [[OP3:%.*]], i32 0, i32 270)536// CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]537//538svint32_t test_svcmla_lane_s32(svint32_t op1, svint32_t op2, svint32_t op3)539{540 return SVE_ACLE_FUNC(svcmla_lane,_s32,,)(op1, op2, op3, 0, 270);541}542 543// CHECK-LABEL: @test_svcmla_lane_s32_1(544// CHECK-NEXT: entry:545// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.cmla.lane.x.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i32> [[OP3:%.*]], i32 1, i32 0)546// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]547//548// CPP-CHECK-LABEL: @_Z22test_svcmla_lane_s32_1u11__SVInt32_tS_S_(549// CPP-CHECK-NEXT: entry:550// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.cmla.lane.x.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i32> [[OP3:%.*]], i32 1, i32 0)551// CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]552//553svint32_t test_svcmla_lane_s32_1(svint32_t op1, svint32_t op2, svint32_t op3)554{555 return SVE_ACLE_FUNC(svcmla_lane,_s32,,)(op1, op2, op3, 1, 0);556}557 558// CHECK-LABEL: @test_svcmla_lane_u16(559// CHECK-NEXT: entry:560// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.cmla.lane.x.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[OP3:%.*]], i32 0, i32 90)561// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]562//563// CPP-CHECK-LABEL: @_Z20test_svcmla_lane_u16u12__SVUint16_tS_S_(564// CPP-CHECK-NEXT: entry:565// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.cmla.lane.x.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[OP3:%.*]], i32 0, i32 90)566// CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]567//568svuint16_t test_svcmla_lane_u16(svuint16_t op1, svuint16_t op2, svuint16_t op3)569{570 return SVE_ACLE_FUNC(svcmla_lane,_u16,,)(op1, op2, op3, 0, 90);571}572 573// CHECK-LABEL: @test_svcmla_lane_u16_1(574// CHECK-NEXT: entry:575// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.cmla.lane.x.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[OP3:%.*]], i32 3, i32 180)576// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]577//578// CPP-CHECK-LABEL: @_Z22test_svcmla_lane_u16_1u12__SVUint16_tS_S_(579// CPP-CHECK-NEXT: entry:580// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.cmla.lane.x.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[OP3:%.*]], i32 3, i32 180)581// CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]582//583svuint16_t test_svcmla_lane_u16_1(svuint16_t op1, svuint16_t op2, svuint16_t op3)584{585 return SVE_ACLE_FUNC(svcmla_lane,_u16,,)(op1, op2, op3, 3, 180);586}587 588// CHECK-LABEL: @test_svcmla_lane_u32(589// CHECK-NEXT: entry:590// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.cmla.lane.x.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i32> [[OP3:%.*]], i32 0, i32 270)591// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]592//593// CPP-CHECK-LABEL: @_Z20test_svcmla_lane_u32u12__SVUint32_tS_S_(594// CPP-CHECK-NEXT: entry:595// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.cmla.lane.x.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i32> [[OP3:%.*]], i32 0, i32 270)596// CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]597//598svuint32_t test_svcmla_lane_u32(svuint32_t op1, svuint32_t op2, svuint32_t op3)599{600 return SVE_ACLE_FUNC(svcmla_lane,_u32,,)(op1, op2, op3, 0, 270);601}602 603// CHECK-LABEL: @test_svcmla_lane_u32_1(604// CHECK-NEXT: entry:605// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.cmla.lane.x.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i32> [[OP3:%.*]], i32 1, i32 0)606// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]607//608// CPP-CHECK-LABEL: @_Z22test_svcmla_lane_u32_1u12__SVUint32_tS_S_(609// CPP-CHECK-NEXT: entry:610// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.cmla.lane.x.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i32> [[OP3:%.*]], i32 1, i32 0)611// CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]612//613svuint32_t test_svcmla_lane_u32_1(svuint32_t op1, svuint32_t op2, svuint32_t op3)614{615 return SVE_ACLE_FUNC(svcmla_lane,_u32,,)(op1, op2, op3, 1, 0);616}617