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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py2// REQUIRES: aarch64-registered-target3 4// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s5// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -O1 -Werror -Wall -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefix=CPP-CHECK6// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -target-feature +sve2 -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s7// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -target-feature +sve2 -O1 -Werror -Wall -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefix=CPP-CHECK8 9#include <arm_sve.h>10 11#ifdef SVE_OVERLOADED_FORMS12// A simple used,unused... macro, long enough to represent any SVE builtin.13#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A314#else15#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A416#endif17 18// CHECK-LABEL: @test_svqdmlalb_s16(19// CHECK-NEXT: entry:20// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.sqdmlalb.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i8> [[OP3:%.*]])21// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]22//23// CPP-CHECK-LABEL: @_Z18test_svqdmlalb_s16u11__SVInt16_tu10__SVInt8_tS0_(24// CPP-CHECK-NEXT: entry:25// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.sqdmlalb.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i8> [[OP3:%.*]])26// CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]27//28svint16_t test_svqdmlalb_s16(svint16_t op1, svint8_t op2, svint8_t op3)29{30 return SVE_ACLE_FUNC(svqdmlalb,_s16,,)(op1, op2, op3);31}32 33// CHECK-LABEL: @test_svqdmlalb_s32(34// CHECK-NEXT: entry:35// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sqdmlalb.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[OP3:%.*]])36// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]37//38// CPP-CHECK-LABEL: @_Z18test_svqdmlalb_s32u11__SVInt32_tu11__SVInt16_tS0_(39// CPP-CHECK-NEXT: entry:40// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sqdmlalb.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[OP3:%.*]])41// CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]42//43svint32_t test_svqdmlalb_s32(svint32_t op1, svint16_t op2, svint16_t op3)44{45 return SVE_ACLE_FUNC(svqdmlalb,_s32,,)(op1, op2, op3);46}47 48// CHECK-LABEL: @test_svqdmlalb_s64(49// CHECK-NEXT: entry:50// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.sqdmlalb.nxv2i64(<vscale x 2 x i64> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i32> [[OP3:%.*]])51// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]52//53// CPP-CHECK-LABEL: @_Z18test_svqdmlalb_s64u11__SVInt64_tu11__SVInt32_tS0_(54// CPP-CHECK-NEXT: entry:55// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.sqdmlalb.nxv2i64(<vscale x 2 x i64> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i32> [[OP3:%.*]])56// CPP-CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]57//58svint64_t test_svqdmlalb_s64(svint64_t op1, svint32_t op2, svint32_t op3)59{60 return SVE_ACLE_FUNC(svqdmlalb,_s64,,)(op1, op2, op3);61}62 63// CHECK-LABEL: @test_svqdmlalb_n_s16(64// CHECK-NEXT: entry:65// CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 16 x i8> poison, i8 [[OP3:%.*]], i64 066// CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <vscale x 16 x i8> [[DOTSPLATINSERT]], <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer67// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.sqdmlalb.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i8> [[DOTSPLAT]])68// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]69//70// CPP-CHECK-LABEL: @_Z20test_svqdmlalb_n_s16u11__SVInt16_tu10__SVInt8_ta(71// CPP-CHECK-NEXT: entry:72// CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 16 x i8> poison, i8 [[OP3:%.*]], i64 073// CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <vscale x 16 x i8> [[DOTSPLATINSERT]], <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer74// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.sqdmlalb.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i8> [[DOTSPLAT]])75// CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]76//77svint16_t test_svqdmlalb_n_s16(svint16_t op1, svint8_t op2, int8_t op3)78{79 return SVE_ACLE_FUNC(svqdmlalb,_n_s16,,)(op1, op2, op3);80}81 82// CHECK-LABEL: @test_svqdmlalb_n_s32(83// CHECK-NEXT: entry:84// CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 8 x i16> poison, i16 [[OP3:%.*]], i64 085// CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <vscale x 8 x i16> [[DOTSPLATINSERT]], <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer86// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sqdmlalb.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[DOTSPLAT]])87// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]88//89// CPP-CHECK-LABEL: @_Z20test_svqdmlalb_n_s32u11__SVInt32_tu11__SVInt16_ts(90// CPP-CHECK-NEXT: entry:91// CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 8 x i16> poison, i16 [[OP3:%.*]], i64 092// CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <vscale x 8 x i16> [[DOTSPLATINSERT]], <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer93// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sqdmlalb.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[DOTSPLAT]])94// CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]95//96svint32_t test_svqdmlalb_n_s32(svint32_t op1, svint16_t op2, int16_t op3)97{98 return SVE_ACLE_FUNC(svqdmlalb,_n_s32,,)(op1, op2, op3);99}100 101// CHECK-LABEL: @test_svqdmlalb_n_s64(102// CHECK-NEXT: entry:103// CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 4 x i32> poison, i32 [[OP3:%.*]], i64 0104// CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <vscale x 4 x i32> [[DOTSPLATINSERT]], <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer105// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.sqdmlalb.nxv2i64(<vscale x 2 x i64> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i32> [[DOTSPLAT]])106// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]107//108// CPP-CHECK-LABEL: @_Z20test_svqdmlalb_n_s64u11__SVInt64_tu11__SVInt32_ti(109// CPP-CHECK-NEXT: entry:110// CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 4 x i32> poison, i32 [[OP3:%.*]], i64 0111// CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <vscale x 4 x i32> [[DOTSPLATINSERT]], <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer112// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.sqdmlalb.nxv2i64(<vscale x 2 x i64> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i32> [[DOTSPLAT]])113// CPP-CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]114//115svint64_t test_svqdmlalb_n_s64(svint64_t op1, svint32_t op2, int32_t op3)116{117 return SVE_ACLE_FUNC(svqdmlalb,_n_s64,,)(op1, op2, op3);118}119 120// CHECK-LABEL: @test_svqdmlalb_lane_s32(121// CHECK-NEXT: entry:122// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sqdmlalb.lane.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[OP3:%.*]], i32 0)123// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]124//125// CPP-CHECK-LABEL: @_Z23test_svqdmlalb_lane_s32u11__SVInt32_tu11__SVInt16_tS0_(126// CPP-CHECK-NEXT: entry:127// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sqdmlalb.lane.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[OP3:%.*]], i32 0)128// CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]129//130svint32_t test_svqdmlalb_lane_s32(svint32_t op1, svint16_t op2, svint16_t op3)131{132 return SVE_ACLE_FUNC(svqdmlalb_lane,_s32,,)(op1, op2, op3, 0);133}134 135// CHECK-LABEL: @test_svqdmlalb_lane_s32_1(136// CHECK-NEXT: entry:137// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sqdmlalb.lane.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[OP3:%.*]], i32 7)138// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]139//140// CPP-CHECK-LABEL: @_Z25test_svqdmlalb_lane_s32_1u11__SVInt32_tu11__SVInt16_tS0_(141// CPP-CHECK-NEXT: entry:142// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sqdmlalb.lane.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[OP3:%.*]], i32 7)143// CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]144//145svint32_t test_svqdmlalb_lane_s32_1(svint32_t op1, svint16_t op2, svint16_t op3)146{147 return SVE_ACLE_FUNC(svqdmlalb_lane,_s32,,)(op1, op2, op3, 7);148}149 150// CHECK-LABEL: @test_svqdmlalb_lane_s64(151// CHECK-NEXT: entry:152// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.sqdmlalb.lane.nxv2i64(<vscale x 2 x i64> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i32> [[OP3:%.*]], i32 0)153// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]154//155// CPP-CHECK-LABEL: @_Z23test_svqdmlalb_lane_s64u11__SVInt64_tu11__SVInt32_tS0_(156// CPP-CHECK-NEXT: entry:157// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.sqdmlalb.lane.nxv2i64(<vscale x 2 x i64> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i32> [[OP3:%.*]], i32 0)158// CPP-CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]159//160svint64_t test_svqdmlalb_lane_s64(svint64_t op1, svint32_t op2, svint32_t op3)161{162 return SVE_ACLE_FUNC(svqdmlalb_lane,_s64,,)(op1, op2, op3, 0);163}164 165// CHECK-LABEL: @test_svqdmlalb_lane_s64_1(166// CHECK-NEXT: entry:167// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.sqdmlalb.lane.nxv2i64(<vscale x 2 x i64> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i32> [[OP3:%.*]], i32 3)168// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]169//170// CPP-CHECK-LABEL: @_Z25test_svqdmlalb_lane_s64_1u11__SVInt64_tu11__SVInt32_tS0_(171// CPP-CHECK-NEXT: entry:172// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.sqdmlalb.lane.nxv2i64(<vscale x 2 x i64> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i32> [[OP3:%.*]], i32 3)173// CPP-CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]174//175svint64_t test_svqdmlalb_lane_s64_1(svint64_t op1, svint32_t op2, svint32_t op3)176{177 return SVE_ACLE_FUNC(svqdmlalb_lane,_s64,,)(op1, op2, op3, 3);178}179