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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py2// REQUIRES: aarch64-registered-target3 4// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s5// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -O1 -Werror -Wall -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefix=CPP-CHECK6// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -target-feature +sve2 -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s7// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -target-feature +sve2 -O1 -Werror -Wall -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefix=CPP-CHECK8 9#include <arm_sve.h>10 11#ifdef SVE_OVERLOADED_FORMS12// A simple used,unused... macro, long enough to represent any SVE builtin.13#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A314#else15#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A416#endif17 18// CHECK-LABEL: @test_svqrdmlah_s8(19// CHECK-NEXT: entry:20// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.sqrdmlah.nxv16i8(<vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i8> [[OP3:%.*]])21// CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]22//23// CPP-CHECK-LABEL: @_Z17test_svqrdmlah_s8u10__SVInt8_tS_S_(24// CPP-CHECK-NEXT: entry:25// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.sqrdmlah.nxv16i8(<vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i8> [[OP3:%.*]])26// CPP-CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]27//28svint8_t test_svqrdmlah_s8(svint8_t op1, svint8_t op2, svint8_t op3)29{30 return SVE_ACLE_FUNC(svqrdmlah,_s8,,)(op1, op2, op3);31}32 33// CHECK-LABEL: @test_svqrdmlah_s16(34// CHECK-NEXT: entry:35// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.sqrdmlah.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[OP3:%.*]])36// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]37//38// CPP-CHECK-LABEL: @_Z18test_svqrdmlah_s16u11__SVInt16_tS_S_(39// CPP-CHECK-NEXT: entry:40// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.sqrdmlah.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[OP3:%.*]])41// CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]42//43svint16_t test_svqrdmlah_s16(svint16_t op1, svint16_t op2, svint16_t op3)44{45 return SVE_ACLE_FUNC(svqrdmlah,_s16,,)(op1, op2, op3);46}47 48// CHECK-LABEL: @test_svqrdmlah_s32(49// CHECK-NEXT: entry:50// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sqrdmlah.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i32> [[OP3:%.*]])51// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]52//53// CPP-CHECK-LABEL: @_Z18test_svqrdmlah_s32u11__SVInt32_tS_S_(54// CPP-CHECK-NEXT: entry:55// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sqrdmlah.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i32> [[OP3:%.*]])56// CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]57//58svint32_t test_svqrdmlah_s32(svint32_t op1, svint32_t op2, svint32_t op3)59{60 return SVE_ACLE_FUNC(svqrdmlah,_s32,,)(op1, op2, op3);61}62 63// CHECK-LABEL: @test_svqrdmlah_s64(64// CHECK-NEXT: entry:65// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.sqrdmlah.nxv2i64(<vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i64> [[OP3:%.*]])66// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]67//68// CPP-CHECK-LABEL: @_Z18test_svqrdmlah_s64u11__SVInt64_tS_S_(69// CPP-CHECK-NEXT: entry:70// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.sqrdmlah.nxv2i64(<vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i64> [[OP3:%.*]])71// CPP-CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]72//73svint64_t test_svqrdmlah_s64(svint64_t op1, svint64_t op2, svint64_t op3)74{75 return SVE_ACLE_FUNC(svqrdmlah,_s64,,)(op1, op2, op3);76}77 78// CHECK-LABEL: @test_svqrdmlah_n_s8(79// CHECK-NEXT: entry:80// CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 16 x i8> poison, i8 [[OP3:%.*]], i64 081// CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <vscale x 16 x i8> [[DOTSPLATINSERT]], <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer82// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.sqrdmlah.nxv16i8(<vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i8> [[DOTSPLAT]])83// CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]84//85// CPP-CHECK-LABEL: @_Z19test_svqrdmlah_n_s8u10__SVInt8_tS_a(86// CPP-CHECK-NEXT: entry:87// CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 16 x i8> poison, i8 [[OP3:%.*]], i64 088// CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <vscale x 16 x i8> [[DOTSPLATINSERT]], <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer89// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.sqrdmlah.nxv16i8(<vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i8> [[DOTSPLAT]])90// CPP-CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]91//92svint8_t test_svqrdmlah_n_s8(svint8_t op1, svint8_t op2, int8_t op3)93{94 return SVE_ACLE_FUNC(svqrdmlah,_n_s8,,)(op1, op2, op3);95}96 97// CHECK-LABEL: @test_svqrdmlah_n_s16(98// CHECK-NEXT: entry:99// CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 8 x i16> poison, i16 [[OP3:%.*]], i64 0100// CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <vscale x 8 x i16> [[DOTSPLATINSERT]], <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer101// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.sqrdmlah.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[DOTSPLAT]])102// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]103//104// CPP-CHECK-LABEL: @_Z20test_svqrdmlah_n_s16u11__SVInt16_tS_s(105// CPP-CHECK-NEXT: entry:106// CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 8 x i16> poison, i16 [[OP3:%.*]], i64 0107// CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <vscale x 8 x i16> [[DOTSPLATINSERT]], <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer108// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.sqrdmlah.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[DOTSPLAT]])109// CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]110//111svint16_t test_svqrdmlah_n_s16(svint16_t op1, svint16_t op2, int16_t op3)112{113 return SVE_ACLE_FUNC(svqrdmlah,_n_s16,,)(op1, op2, op3);114}115 116// CHECK-LABEL: @test_svqrdmlah_n_s32(117// CHECK-NEXT: entry:118// CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 4 x i32> poison, i32 [[OP3:%.*]], i64 0119// CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <vscale x 4 x i32> [[DOTSPLATINSERT]], <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer120// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sqrdmlah.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i32> [[DOTSPLAT]])121// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]122//123// CPP-CHECK-LABEL: @_Z20test_svqrdmlah_n_s32u11__SVInt32_tS_i(124// CPP-CHECK-NEXT: entry:125// CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 4 x i32> poison, i32 [[OP3:%.*]], i64 0126// CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <vscale x 4 x i32> [[DOTSPLATINSERT]], <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer127// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sqrdmlah.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i32> [[DOTSPLAT]])128// CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]129//130svint32_t test_svqrdmlah_n_s32(svint32_t op1, svint32_t op2, int32_t op3)131{132 return SVE_ACLE_FUNC(svqrdmlah,_n_s32,,)(op1, op2, op3);133}134 135// CHECK-LABEL: @test_svqrdmlah_n_s64(136// CHECK-NEXT: entry:137// CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 2 x i64> poison, i64 [[OP3:%.*]], i64 0138// CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <vscale x 2 x i64> [[DOTSPLATINSERT]], <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer139// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.sqrdmlah.nxv2i64(<vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i64> [[DOTSPLAT]])140// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]141//142// CPP-CHECK-LABEL: @_Z20test_svqrdmlah_n_s64u11__SVInt64_tS_l(143// CPP-CHECK-NEXT: entry:144// CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 2 x i64> poison, i64 [[OP3:%.*]], i64 0145// CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <vscale x 2 x i64> [[DOTSPLATINSERT]], <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer146// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.sqrdmlah.nxv2i64(<vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i64> [[DOTSPLAT]])147// CPP-CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]148//149svint64_t test_svqrdmlah_n_s64(svint64_t op1, svint64_t op2, int64_t op3)150{151 return SVE_ACLE_FUNC(svqrdmlah,_n_s64,,)(op1, op2, op3);152}153 154// CHECK-LABEL: @test_svqrdmlah_lane_s16(155// CHECK-NEXT: entry:156// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.sqrdmlah.lane.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[OP3:%.*]], i32 0)157// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]158//159// CPP-CHECK-LABEL: @_Z23test_svqrdmlah_lane_s16u11__SVInt16_tS_S_(160// CPP-CHECK-NEXT: entry:161// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.sqrdmlah.lane.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[OP3:%.*]], i32 0)162// CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]163//164svint16_t test_svqrdmlah_lane_s16(svint16_t op1, svint16_t op2, svint16_t op3)165{166 return SVE_ACLE_FUNC(svqrdmlah_lane,_s16,,)(op1, op2, op3, 0);167}168 169// CHECK-LABEL: @test_svqrdmlah_lane_s16_1(170// CHECK-NEXT: entry:171// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.sqrdmlah.lane.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[OP3:%.*]], i32 7)172// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]173//174// CPP-CHECK-LABEL: @_Z25test_svqrdmlah_lane_s16_1u11__SVInt16_tS_S_(175// CPP-CHECK-NEXT: entry:176// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.sqrdmlah.lane.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[OP3:%.*]], i32 7)177// CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]178//179svint16_t test_svqrdmlah_lane_s16_1(svint16_t op1, svint16_t op2, svint16_t op3)180{181 return SVE_ACLE_FUNC(svqrdmlah_lane,_s16,,)(op1, op2, op3, 7);182}183 184// CHECK-LABEL: @test_svqrdmlah_lane_s32(185// CHECK-NEXT: entry:186// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sqrdmlah.lane.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i32> [[OP3:%.*]], i32 0)187// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]188//189// CPP-CHECK-LABEL: @_Z23test_svqrdmlah_lane_s32u11__SVInt32_tS_S_(190// CPP-CHECK-NEXT: entry:191// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sqrdmlah.lane.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i32> [[OP3:%.*]], i32 0)192// CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]193//194svint32_t test_svqrdmlah_lane_s32(svint32_t op1, svint32_t op2, svint32_t op3)195{196 return SVE_ACLE_FUNC(svqrdmlah_lane,_s32,,)(op1, op2, op3, 0);197}198 199// CHECK-LABEL: @test_svqrdmlah_lane_s32_1(200// CHECK-NEXT: entry:201// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sqrdmlah.lane.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i32> [[OP3:%.*]], i32 3)202// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]203//204// CPP-CHECK-LABEL: @_Z25test_svqrdmlah_lane_s32_1u11__SVInt32_tS_S_(205// CPP-CHECK-NEXT: entry:206// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sqrdmlah.lane.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i32> [[OP3:%.*]], i32 3)207// CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]208//209svint32_t test_svqrdmlah_lane_s32_1(svint32_t op1, svint32_t op2, svint32_t op3)210{211 return SVE_ACLE_FUNC(svqrdmlah_lane,_s32,,)(op1, op2, op3, 3);212}213 214// CHECK-LABEL: @test_svqrdmlah_lane_s64(215// CHECK-NEXT: entry:216// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.sqrdmlah.lane.nxv2i64(<vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i64> [[OP3:%.*]], i32 0)217// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]218//219// CPP-CHECK-LABEL: @_Z23test_svqrdmlah_lane_s64u11__SVInt64_tS_S_(220// CPP-CHECK-NEXT: entry:221// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.sqrdmlah.lane.nxv2i64(<vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i64> [[OP3:%.*]], i32 0)222// CPP-CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]223//224svint64_t test_svqrdmlah_lane_s64(svint64_t op1, svint64_t op2, svint64_t op3)225{226 return SVE_ACLE_FUNC(svqrdmlah_lane,_s64,,)(op1, op2, op3, 0);227}228 229// CHECK-LABEL: @test_svqrdmlah_lane_s64_1(230// CHECK-NEXT: entry:231// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.sqrdmlah.lane.nxv2i64(<vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i64> [[OP3:%.*]], i32 1)232// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]233//234// CPP-CHECK-LABEL: @_Z25test_svqrdmlah_lane_s64_1u11__SVInt64_tS_S_(235// CPP-CHECK-NEXT: entry:236// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.sqrdmlah.lane.nxv2i64(<vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i64> [[OP3:%.*]], i32 1)237// CPP-CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]238//239svint64_t test_svqrdmlah_lane_s64_1(svint64_t op1, svint64_t op2, svint64_t op3)240{241 return SVE_ACLE_FUNC(svqrdmlah_lane,_s64,,)(op1, op2, op3, 1);242}243