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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py2// REQUIRES: aarch64-registered-target3// RUN: %clang_cc1 -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s4// RUN: %clang_cc1 -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK5// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s6// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK7// RUN: %clang_cc1 -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -o /dev/null %s8#include <arm_sve.h>9 10#ifdef SVE_OVERLOADED_FORMS11// A simple used,unused... macro, long enough to represent any SVE builtin.12#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3) A1##A313#else14#define SVE_ACLE_FUNC(A1,A2,A3) A1##A2##A315#endif16 17// CHECK-LABEL: @test_svmls_lane_bf16_idx1(18// CHECK-NEXT: entry:19// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmls.lane.nxv8bf16(<vscale x 8 x bfloat> [[OP1:%.*]], <vscale x 8 x bfloat> [[OP2:%.*]], <vscale x 8 x bfloat> [[OP3:%.*]], i32 1)20// CHECK-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]21//22// CPP-CHECK-LABEL: @_Z25test_svmls_lane_bf16_idx1u14__SVBfloat16_tS_S_(23// CPP-CHECK-NEXT: entry:24// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmls.lane.nxv8bf16(<vscale x 8 x bfloat> [[OP1:%.*]], <vscale x 8 x bfloat> [[OP2:%.*]], <vscale x 8 x bfloat> [[OP3:%.*]], i32 1)25// CPP-CHECK-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]26//27svbfloat16_t test_svmls_lane_bf16_idx1(svbfloat16_t op1, svbfloat16_t op2, svbfloat16_t op3)28{29 return SVE_ACLE_FUNC(svmls_lane, _bf16,)(op1, op2, op3, 1);30}31 32// CHECK-LABEL: @test_svmls_lane_bf16_idx3(33// CHECK-NEXT: entry:34// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmls.lane.nxv8bf16(<vscale x 8 x bfloat> [[OP1:%.*]], <vscale x 8 x bfloat> [[OP2:%.*]], <vscale x 8 x bfloat> [[OP3:%.*]], i32 3)35// CHECK-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]36//37// CPP-CHECK-LABEL: @_Z25test_svmls_lane_bf16_idx3u14__SVBfloat16_tS_S_(38// CPP-CHECK-NEXT: entry:39// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmls.lane.nxv8bf16(<vscale x 8 x bfloat> [[OP1:%.*]], <vscale x 8 x bfloat> [[OP2:%.*]], <vscale x 8 x bfloat> [[OP3:%.*]], i32 3)40// CPP-CHECK-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]41//42svbfloat16_t test_svmls_lane_bf16_idx3(svbfloat16_t op1, svbfloat16_t op2, svbfloat16_t op3)43{44 return SVE_ACLE_FUNC(svmls_lane, _bf16,)(op1, op2, op3, 3);45}46 47// CHECK-LABEL: @test_svmls_lane_bf16_idx7(48// CHECK-NEXT: entry:49// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmls.lane.nxv8bf16(<vscale x 8 x bfloat> [[OP1:%.*]], <vscale x 8 x bfloat> [[OP2:%.*]], <vscale x 8 x bfloat> [[OP3:%.*]], i32 7)50// CHECK-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]51//52// CPP-CHECK-LABEL: @_Z25test_svmls_lane_bf16_idx7u14__SVBfloat16_tS_S_(53// CPP-CHECK-NEXT: entry:54// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmls.lane.nxv8bf16(<vscale x 8 x bfloat> [[OP1:%.*]], <vscale x 8 x bfloat> [[OP2:%.*]], <vscale x 8 x bfloat> [[OP3:%.*]], i32 7)55// CPP-CHECK-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]56//57svbfloat16_t test_svmls_lane_bf16_idx7(svbfloat16_t op1, svbfloat16_t op2, svbfloat16_t op3)58{59 return SVE_ACLE_FUNC(svmls_lane, _bf16,)(op1, op2, op3, 7);60}61