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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py2// REQUIRES: aarch64-registered-target3// RUN: %clang_cc1 -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -O1 -Werror -emit-llvm -o - %s | FileCheck %s4// RUN: %clang_cc1 -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefix=CPP-CHECK5// RUN: %clang_cc1 -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s6// RUN: %clang_cc1 -triple aarch64 -target-feature +sme -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s7// RUN: %clang_cc1 -triple aarch64 -target-feature +sme -target-feature +sme2 -O1 -Werror -emit-llvm -o - %s | FileCheck %s8// RUN: %clang_cc1 -triple aarch64 -target-feature +sme -target-feature +sme2 -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefix=CPP-CHECK9// RUN: %clang_cc1 -triple aarch64 -target-feature +sme -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s10 11#include <arm_sve.h>12 13#ifdef __ARM_FEATURE_SME14#define ATTR __arm_streaming15#else16#define ATTR17#endif18 19// CHECK-LABEL: @test_svcntp_c8_vlx2(20// CHECK-NEXT: entry:21// CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntp.c8(target("aarch64.svcount") [[PNN:%.*]], i32 2)22// CHECK-NEXT: ret i64 [[TMP0]]23//24// CPP-CHECK-LABEL: @_Z19test_svcntp_c8_vlx2u11__SVCount_t(25// CPP-CHECK-NEXT: entry:26// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntp.c8(target("aarch64.svcount") [[PNN:%.*]], i32 2)27// CPP-CHECK-NEXT: ret i64 [[TMP0]]28//29uint64_t test_svcntp_c8_vlx2(svcount_t pnn) ATTR {30 return svcntp_c8(pnn, 2);31}32 33// CHECK-LABEL: @test_svcntp_c8_vlx4(34// CHECK-NEXT: entry:35// CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntp.c8(target("aarch64.svcount") [[PNN:%.*]], i32 4)36// CHECK-NEXT: ret i64 [[TMP0]]37//38// CPP-CHECK-LABEL: @_Z19test_svcntp_c8_vlx4u11__SVCount_t(39// CPP-CHECK-NEXT: entry:40// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntp.c8(target("aarch64.svcount") [[PNN:%.*]], i32 4)41// CPP-CHECK-NEXT: ret i64 [[TMP0]]42//43uint64_t test_svcntp_c8_vlx4(svcount_t pnn) ATTR {44 return svcntp_c8(pnn, 4);45}46 47// CHECK-LABEL: @test_svcntp_c16_vlx2(48// CHECK-NEXT: entry:49// CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntp.c16(target("aarch64.svcount") [[PNN:%.*]], i32 2)50// CHECK-NEXT: ret i64 [[TMP0]]51//52// CPP-CHECK-LABEL: @_Z20test_svcntp_c16_vlx2u11__SVCount_t(53// CPP-CHECK-NEXT: entry:54// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntp.c16(target("aarch64.svcount") [[PNN:%.*]], i32 2)55// CPP-CHECK-NEXT: ret i64 [[TMP0]]56//57uint64_t test_svcntp_c16_vlx2(svcount_t pnn) ATTR {58 return svcntp_c16(pnn, 2);59}60 61// CHECK-LABEL: @test_svcntp_c16_vlx4(62// CHECK-NEXT: entry:63// CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntp.c16(target("aarch64.svcount") [[PNN:%.*]], i32 4)64// CHECK-NEXT: ret i64 [[TMP0]]65//66// CPP-CHECK-LABEL: @_Z20test_svcntp_c16_vlx4u11__SVCount_t(67// CPP-CHECK-NEXT: entry:68// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntp.c16(target("aarch64.svcount") [[PNN:%.*]], i32 4)69// CPP-CHECK-NEXT: ret i64 [[TMP0]]70//71uint64_t test_svcntp_c16_vlx4(svcount_t pnn) ATTR {72 return svcntp_c16(pnn, 4);73}74 75// CHECK-LABEL: @test_svcntp_c32_vlx2(76// CHECK-NEXT: entry:77// CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntp.c32(target("aarch64.svcount") [[PNN:%.*]], i32 2)78// CHECK-NEXT: ret i64 [[TMP0]]79//80// CPP-CHECK-LABEL: @_Z20test_svcntp_c32_vlx2u11__SVCount_t(81// CPP-CHECK-NEXT: entry:82// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntp.c32(target("aarch64.svcount") [[PNN:%.*]], i32 2)83// CPP-CHECK-NEXT: ret i64 [[TMP0]]84//85uint64_t test_svcntp_c32_vlx2(svcount_t pnn) ATTR {86 return svcntp_c32(pnn, 2);87}88 89// CHECK-LABEL: @test_svcntp_c32_vlx4(90// CHECK-NEXT: entry:91// CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntp.c32(target("aarch64.svcount") [[PNN:%.*]], i32 4)92// CHECK-NEXT: ret i64 [[TMP0]]93//94// CPP-CHECK-LABEL: @_Z20test_svcntp_c32_vlx4u11__SVCount_t(95// CPP-CHECK-NEXT: entry:96// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntp.c32(target("aarch64.svcount") [[PNN:%.*]], i32 4)97// CPP-CHECK-NEXT: ret i64 [[TMP0]]98//99uint64_t test_svcntp_c32_vlx4(svcount_t pnn) ATTR {100 return svcntp_c32(pnn, 4);101}102 103// CHECK-LABEL: @test_svcntp_c64_vlx2(104// CHECK-NEXT: entry:105// CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntp.c64(target("aarch64.svcount") [[PNN:%.*]], i32 2)106// CHECK-NEXT: ret i64 [[TMP0]]107//108// CPP-CHECK-LABEL: @_Z20test_svcntp_c64_vlx2u11__SVCount_t(109// CPP-CHECK-NEXT: entry:110// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntp.c64(target("aarch64.svcount") [[PNN:%.*]], i32 2)111// CPP-CHECK-NEXT: ret i64 [[TMP0]]112//113uint64_t test_svcntp_c64_vlx2(svcount_t pnn) ATTR {114 return svcntp_c64(pnn, 2);115}116 117// CHECK-LABEL: @test_svcntp_c64_vlx4(118// CHECK-NEXT: entry:119// CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntp.c64(target("aarch64.svcount") [[PNN:%.*]], i32 4)120// CHECK-NEXT: ret i64 [[TMP0]]121//122// CPP-CHECK-LABEL: @_Z20test_svcntp_c64_vlx4u11__SVCount_t(123// CPP-CHECK-NEXT: entry:124// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntp.c64(target("aarch64.svcount") [[PNN:%.*]], i32 4)125// CPP-CHECK-NEXT: ret i64 [[TMP0]]126//127uint64_t test_svcntp_c64_vlx4(svcount_t pnn) ATTR {128 return svcntp_c64(pnn, 4);129}130