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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py2// REQUIRES: aarch64-registered-target3// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s4// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK5// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s6// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK7// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s8// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s9// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s10// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK11// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s12// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s13#include <arm_sve.h>14 15#if defined(__ARM_FEATURE_SME) && defined(__ARM_FEATURE_SVE)16#define ATTR __arm_streaming_compatible17#elif defined(__ARM_FEATURE_SME)18#define ATTR __arm_streaming19#else20#define ATTR21#endif22 23#ifdef SVE_OVERLOADED_FORMS24// A simple used,unused... macro, long enough to represent any SVE builtin.25#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3) A1##A326#else27#define SVE_ACLE_FUNC(A1,A2,A3) A1##A2##A328#endif29 30// CHECK-LABEL: @test_svdot_s32_x2(31// CHECK-NEXT: entry:32// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sdot.x2.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[OP3:%.*]])33// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]34//35// CPP-CHECK-LABEL: @_Z17test_svdot_s32_x2u11__SVInt32_tu11__SVInt16_tS0_(36// CPP-CHECK-NEXT: entry:37// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sdot.x2.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[OP3:%.*]])38// CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]39//40svint32_t test_svdot_s32_x2(svint32_t op1, svint16_t op2, svint16_t op3) ATTR41{42 return SVE_ACLE_FUNC(svdot,_s32_s16,)(op1, op2, op3);43}44 45// CHECK-LABEL: @test_svdot_u32_x2(46// CHECK-NEXT: entry:47// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.udot.x2.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[OP3:%.*]])48// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]49//50// CPP-CHECK-LABEL: @_Z17test_svdot_u32_x2u12__SVUint32_tu12__SVUint16_tS0_(51// CPP-CHECK-NEXT: entry:52// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.udot.x2.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[OP3:%.*]])53// CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]54//55svuint32_t test_svdot_u32_x2(svuint32_t op1, svuint16_t op2, svuint16_t op3) ATTR56{57 return SVE_ACLE_FUNC(svdot,_u32_u16,)(op1, op2, op3);58}59 60// CHECK-LABEL: @test_svdot_f32_x2(61// CHECK-NEXT: entry:62// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.fdot.x2.nxv4f32(<vscale x 4 x float> [[OP1:%.*]], <vscale x 8 x half> [[OP2:%.*]], <vscale x 8 x half> [[OP3:%.*]])63// CHECK-NEXT: ret <vscale x 4 x float> [[TMP0]]64//65// CPP-CHECK-LABEL: @_Z17test_svdot_f32_x2u13__SVFloat32_tu13__SVFloat16_tS0_(66// CPP-CHECK-NEXT: entry:67// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.fdot.x2.nxv4f32(<vscale x 4 x float> [[OP1:%.*]], <vscale x 8 x half> [[OP2:%.*]], <vscale x 8 x half> [[OP3:%.*]])68// CPP-CHECK-NEXT: ret <vscale x 4 x float> [[TMP0]]69//70svfloat32_t test_svdot_f32_x2(svfloat32_t op1, svfloat16_t op2, svfloat16_t op3) ATTR71{72 return SVE_ACLE_FUNC(svdot,_f32_f16,)(op1, op2, op3);73}74 75 76 77// CHECK-LABEL: @test_svdot_lane_s32_x2(78// CHECK-NEXT: entry:79// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sdot.lane.x2.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[OP3:%.*]], i32 3)80// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]81//82// CPP-CHECK-LABEL: @_Z22test_svdot_lane_s32_x2u11__SVInt32_tu11__SVInt16_tS0_(83// CPP-CHECK-NEXT: entry:84// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sdot.lane.x2.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[OP3:%.*]], i32 3)85// CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]86//87svint32_t test_svdot_lane_s32_x2(svint32_t op1, svint16_t op2, svint16_t op3) ATTR88{89 return SVE_ACLE_FUNC(svdot_lane,_s32_s16,)(op1, op2, op3, 3);90}91 92// CHECK-LABEL: @test_svdot_lane_u32_x2(93// CHECK-NEXT: entry:94// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.udot.lane.x2.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[OP3:%.*]], i32 3)95// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]96//97// CPP-CHECK-LABEL: @_Z22test_svdot_lane_u32_x2u12__SVUint32_tu12__SVUint16_tS0_(98// CPP-CHECK-NEXT: entry:99// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.udot.lane.x2.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[OP3:%.*]], i32 3)100// CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]101//102svuint32_t test_svdot_lane_u32_x2(svuint32_t op1, svuint16_t op2, svuint16_t op3) ATTR103{104 return SVE_ACLE_FUNC(svdot_lane,_u32_u16,)(op1, op2, op3, 3);105}106 107// CHECK-LABEL: @test_svdot_lane_f32_x2(108// CHECK-NEXT: entry:109// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.fdot.lane.x2.nxv4f32(<vscale x 4 x float> [[OP1:%.*]], <vscale x 8 x half> [[OP2:%.*]], <vscale x 8 x half> [[OP3:%.*]], i32 3)110// CHECK-NEXT: ret <vscale x 4 x float> [[TMP0]]111//112// CPP-CHECK-LABEL: @_Z22test_svdot_lane_f32_x2u13__SVFloat32_tu13__SVFloat16_tS0_(113// CPP-CHECK-NEXT: entry:114// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.fdot.lane.x2.nxv4f32(<vscale x 4 x float> [[OP1:%.*]], <vscale x 8 x half> [[OP2:%.*]], <vscale x 8 x half> [[OP3:%.*]], i32 3)115// CPP-CHECK-NEXT: ret <vscale x 4 x float> [[TMP0]]116//117svfloat32_t test_svdot_lane_f32_x2(svfloat32_t op1, svfloat16_t op2, svfloat16_t op3) ATTR118{119 return SVE_ACLE_FUNC(svdot_lane,_f32_f16,)(op1, op2, op3, 3);120}121