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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py2 3// REQUIRES: aarch64-registered-target4 5// RUN: %clang_cc1 -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s6// RUN: %clang_cc1 -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK7// RUN: %clang_cc1 -D__SVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s8// RUN: %clang_cc1 -D__SVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK9// RUN: %clang_cc1 -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s10 11// RUN: %clang_cc1 -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s12// RUN: %clang_cc1 -triple aarch64 -target-feature +sve -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s13// RUN: %clang_cc1 -triple aarch64 -target-feature +sme -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s14// RUN: %clang_cc1 -triple aarch64 -target-feature +sme -target-feature +sve -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK15// RUN: %clang_cc1 -triple aarch64 -target-feature +sme -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s16 17#include <arm_sve.h>18 19#ifdef SVE_OVERLOADED_FORMS20// A simple used,unused... macro, long enough to represent any SVE builtin.21#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A322#else23#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A424#endif25 26#if defined(__ARM_FEATURE_SME) && defined(__ARM_FEATURE_SVE)27#define ATTR __arm_streaming_compatible28#elif defined(__ARM_FEATURE_SME)29#define ATTR __arm_streaming30#else31#define ATTR32#endif33 34// CHECK-LABEL: @test_qcvtn_s16_s32_x2(35// CHECK-NEXT: entry:36// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.sqcvtn.x2.nxv4i32(<vscale x 4 x i32> [[ZN_COERCE0:%.*]], <vscale x 4 x i32> [[ZN_COERCE1:%.*]])37// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]38//39// CPP-CHECK-LABEL: @_Z21test_qcvtn_s16_s32_x211svint32x2_t(40// CPP-CHECK-NEXT: entry:41// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.sqcvtn.x2.nxv4i32(<vscale x 4 x i32> [[ZN_COERCE0:%.*]], <vscale x 4 x i32> [[ZN_COERCE1:%.*]])42// CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]43//44svint16_t test_qcvtn_s16_s32_x2(svint32x2_t zn) ATTR {45 return SVE_ACLE_FUNC(svqcvtn_s16,_s32_x2,,)(zn);46}47 48// CHECK-LABEL: @test_qcvtn_u16_u32_x2(49// CHECK-NEXT: entry:50// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.uqcvtn.x2.nxv4i32(<vscale x 4 x i32> [[ZN_COERCE0:%.*]], <vscale x 4 x i32> [[ZN_COERCE1:%.*]])51// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]52//53// CPP-CHECK-LABEL: @_Z21test_qcvtn_u16_u32_x212svuint32x2_t(54// CPP-CHECK-NEXT: entry:55// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.uqcvtn.x2.nxv4i32(<vscale x 4 x i32> [[ZN_COERCE0:%.*]], <vscale x 4 x i32> [[ZN_COERCE1:%.*]])56// CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]57//58svuint16_t test_qcvtn_u16_u32_x2(svuint32x2_t zn) ATTR {59 return SVE_ACLE_FUNC(svqcvtn_u16,_u32_x2,,)(zn);60}61 62// CHECK-LABEL: @test_qcvtn_u16_s32_x2(63// CHECK-NEXT: entry:64// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.sqcvtun.x2.nxv4i32(<vscale x 4 x i32> [[ZN_COERCE0:%.*]], <vscale x 4 x i32> [[ZN_COERCE1:%.*]])65// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]66//67// CPP-CHECK-LABEL: @_Z21test_qcvtn_u16_s32_x211svint32x2_t(68// CPP-CHECK-NEXT: entry:69// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.sqcvtun.x2.nxv4i32(<vscale x 4 x i32> [[ZN_COERCE0:%.*]], <vscale x 4 x i32> [[ZN_COERCE1:%.*]])70// CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]71//72svuint16_t test_qcvtn_u16_s32_x2(svint32x2_t zn) ATTR {73 return SVE_ACLE_FUNC(svqcvtn_u16,_s32_x2,,)(zn);74}75