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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py2// REQUIRES: aarch64-registered-target3// RUN: %clang_cc1 -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s4// RUN: %clang_cc1 -triple aarch64 -target-feature +sve -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s5// RUN: %clang_cc1 -triple aarch64 -target-feature +sme -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s6// RUN: %clang_cc1 -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s7// RUN: %clang_cc1 -triple aarch64 -target-feature +sme -target-feature +sve -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK8// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sme -target-feature +sve -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s9// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sme -target-feature +sve -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK10// RUN: %clang_cc1 -triple aarch64 -target-feature +sme -target-feature +sve -target-feature +sme2 -target-feature +sme-f64f64 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s11// RUN: %clang_cc1 -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s12 13#include <arm_sve.h>14 15#if defined(__ARM_FEATURE_SME) && defined(__ARM_FEATURE_SVE)16#define ATTR __arm_streaming_compatible17#elif defined(__ARM_FEATURE_SME)18#define ATTR __arm_streaming19#else20#define ATTR21#endif22 23#ifdef SVE_OVERLOADED_FORMS24// A simple used,unused... macro, long enough to represent any SVE builtin.25#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED,A5) A1##A3##A526#else27#define SVE_ACLE_FUNC(A1,A2,A3,A4,A5) A1##A2##A3##A4##A528#endif29 30 31// SQRSHRN x 232 33// CHECK-LABEL: @test_svqrshrn_s16_s32_x2(34// CHECK-NEXT: entry:35// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.sqrshrn.x2.nxv4i32(<vscale x 4 x i32> [[ZN_COERCE0:%.*]], <vscale x 4 x i32> [[ZN_COERCE1:%.*]], i32 16)36// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]37//38// CPP-CHECK-LABEL: @_Z24test_svqrshrn_s16_s32_x211svint32x2_t(39// CPP-CHECK-NEXT: entry:40// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.sqrshrn.x2.nxv4i32(<vscale x 4 x i32> [[ZN_COERCE0:%.*]], <vscale x 4 x i32> [[ZN_COERCE1:%.*]], i32 16)41// CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]42//43svint16_t test_svqrshrn_s16_s32_x2(svint32x2_t zn) ATTR {44 return SVE_ACLE_FUNC(svqrshrn,_n,_s16,_s32_x2,)(zn, 16);45}46 47// UQRSHRN x 248 49// CHECK-LABEL: @test_svqrshrn_u16_u32_x2(50// CHECK-NEXT: entry:51// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.uqrshrn.x2.nxv4i32(<vscale x 4 x i32> [[ZN_COERCE0:%.*]], <vscale x 4 x i32> [[ZN_COERCE1:%.*]], i32 16)52// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]53//54// CPP-CHECK-LABEL: @_Z24test_svqrshrn_u16_u32_x212svuint32x2_t(55// CPP-CHECK-NEXT: entry:56// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.uqrshrn.x2.nxv4i32(<vscale x 4 x i32> [[ZN_COERCE0:%.*]], <vscale x 4 x i32> [[ZN_COERCE1:%.*]], i32 16)57// CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]58//59svuint16_t test_svqrshrn_u16_u32_x2(svuint32x2_t zn) ATTR {60 return SVE_ACLE_FUNC(svqrshrn,_n,_u16,_u32_x2,)(zn, 16);61}62 63// SQRSHRUN x 264 65// CHECK-LABEL: @test_svqrshrun_u16_s32_x2(66// CHECK-NEXT: entry:67// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.sqrshrun.x2.nxv4i32(<vscale x 4 x i32> [[ZN_COERCE0:%.*]], <vscale x 4 x i32> [[ZN_COERCE1:%.*]], i32 16)68// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]69//70// CPP-CHECK-LABEL: @_Z25test_svqrshrun_u16_s32_x211svint32x2_t(71// CPP-CHECK-NEXT: entry:72// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.sqrshrun.x2.nxv4i32(<vscale x 4 x i32> [[ZN_COERCE0:%.*]], <vscale x 4 x i32> [[ZN_COERCE1:%.*]], i32 16)73// CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]74//75svuint16_t test_svqrshrun_u16_s32_x2(svint32x2_t zn) ATTR {76 return SVE_ACLE_FUNC(svqrshrun,_n,_u16,_s32_x2,)(zn, 16);77}78