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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 52// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -target-feature +v9.6a -target-feature +f8f16mm -target-feature +fp8 \3// RUN: -disable-O0-optnone -emit-llvm -o - %s \4// RUN: | opt -S -passes=mem2reg,sroa \5// RUN: | FileCheck %s6 7// REQUIRES: aarch64-registered-target8 9#include <arm_neon.h>10 11// CHECK-LABEL: define dso_local <8 x half> @test_vmmlaq_f16_mf8(12// CHECK-SAME: <8 x half> noundef [[P0:%.*]], <16 x i8> [[P1:%.*]], <16 x i8> [[P2:%.*]], i64 noundef [[P3:%.*]]) #[[ATTR0:[0-9]+]] {13// CHECK-NEXT: [[ENTRY:.*:]]14// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x half> [[P0]] to <8 x i16>15// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[TMP0]] to <16 x i8>16// CHECK-NEXT: call void @llvm.aarch64.set.fpmr(i64 [[P3]])17// CHECK-NEXT: [[FMMLA_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x half>18// CHECK-NEXT: [[FMMLA1_I:%.*]] = call <8 x half> @llvm.aarch64.neon.fmmla.v8f16.v16i8(<8 x half> [[FMMLA_I]], <16 x i8> [[P1]], <16 x i8> [[P2]])19// CHECK-NEXT: ret <8 x half> [[FMMLA1_I]]20//21float16x8_t test_vmmlaq_f16_mf8(float16x8_t p0, mfloat8x16_t p1, mfloat8x16_t p2, fpm_t p3) {22 return vmmlaq_f16_mf8_fpm(p0, p1, p2, p3);23}24