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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py2// RUN: %clang_cc1 -triple loongarch32 -O2 -emit-llvm %s -o - | FileCheck %s3// RUN: %clang_cc1 -triple loongarch64 -O2 -emit-llvm %s -o - | FileCheck %s4 5/// Test LoongArch specific operand modifiers (i.e. operand codes).6 7// CHECK-LABEL: @test_z_zero(8// CHECK-NEXT: entry:9// CHECK-NEXT: [[TMP0:%.*]] = tail call i32 asm sideeffect "add.w $0, $1, ${2:z}", "=r,r,ri"(i32 [[A:%.*]], i32 0) #[[ATTR1:[0-9]+]], !srcloc [[META6:![0-9]+]]10// CHECK-NEXT: ret void11//12void test_z_zero(int a) {13 int tmp;14 asm volatile ("add.w %0, %1, %z2" : "=r" (tmp) : "r" (a), "ri" (0));15}16 17// CHECK-LABEL: @test_z_nonzero(18// CHECK-NEXT: entry:19// CHECK-NEXT: [[TMP0:%.*]] = tail call i32 asm sideeffect "add.w $0, $1, ${2:z}", "=r,r,ri"(i32 [[A:%.*]], i32 1) #[[ATTR1]], !srcloc [[META7:![0-9]+]]20// CHECK-NEXT: ret void21//22void test_z_nonzero(int a) {23 int tmp;24 asm volatile ("add.w %0, %1, %z2" : "=r" (tmp) : "r" (a), "ri" (1));25}26