2468 lines · c
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py2// REQUIRES: powerpc-registered-target3// RUN: %clang_cc1 -flax-vector-conversions=none -triple powerpc64-unknown-unknown -emit-llvm %s \4// RUN: -target-cpu pwr8 -o - | FileCheck %s -check-prefix=BE-PWR85// RUN: %clang_cc1 -flax-vector-conversions=none -triple powerpc64le-unknown-unknown -emit-llvm %s \6// RUN: -target-cpu pwr8 -o - | FileCheck %s -check-prefix=LE-PWR87 8// RUN: %clang_cc1 -flax-vector-conversions=none -triple powerpc64-unknown-unknown -emit-llvm %s \9// RUN: -target-cpu pwr9 -o - | FileCheck %s -check-prefix=BE-PWR910// RUN: %clang_cc1 -flax-vector-conversions=none -triple powerpc64le-unknown-unknown -emit-llvm %s \11// RUN: -target-cpu pwr9 -o - | FileCheck %s -check-prefix=LE-PWR912// RUN: %clang_cc1 -flax-vector-conversions=none -triple powerpc-unknown-unknown -emit-llvm %s \13// RUN: -target-cpu pwr9 -o - | FileCheck %s -check-prefix=BE32-PWR914 15#include <altivec.h>16// BE-PWR8-LABEL: @test_ldrmb1(17// BE-PWR8-NEXT: entry:18// BE-PWR8-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 819// BE-PWR8-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 820// BE-PWR8-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 821// BE-PWR8-NEXT: [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 022// BE-PWR8-NEXT: [[LD_LO:%.*]] = call <4 x i32> @llvm.ppc.altivec.lvx(ptr [[TMP0]])23// BE-PWR8-NEXT: [[LD_HI:%.*]] = call <4 x i32> @llvm.ppc.altivec.lvx(ptr [[TMP1]])24// BE-PWR8-NEXT: [[MASK1:%.*]] = call <16 x i8> @llvm.ppc.altivec.lvsl(ptr [[TMP0]])25// BE-PWR8-NEXT: [[SHUFFLE1:%.*]] = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> [[LD_LO]], <4 x i32> [[LD_HI]], <16 x i8> [[MASK1]])26// BE-PWR8-NEXT: [[SHUFFLE2:%.*]] = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> zeroinitializer, <4 x i32> [[SHUFFLE1]], <16 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 16>)27// BE-PWR8-NEXT: [[TMP2:%.*]] = bitcast <4 x i32> [[SHUFFLE2]] to <16 x i8>28// BE-PWR8-NEXT: ret <16 x i8> [[TMP2]]29//30// LE-PWR8-LABEL: @test_ldrmb1(31// LE-PWR8-NEXT: entry:32// LE-PWR8-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 833// LE-PWR8-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 834// LE-PWR8-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 835// LE-PWR8-NEXT: [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 036// LE-PWR8-NEXT: [[LD_LO:%.*]] = call <4 x i32> @llvm.ppc.altivec.lvx(ptr [[TMP0]])37// LE-PWR8-NEXT: [[LD_HI:%.*]] = call <4 x i32> @llvm.ppc.altivec.lvx(ptr [[TMP1]])38// LE-PWR8-NEXT: [[MASK1:%.*]] = call <16 x i8> @llvm.ppc.altivec.lvsr(ptr [[TMP0]])39// LE-PWR8-NEXT: [[SHUFFLE1:%.*]] = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> [[LD_HI]], <4 x i32> [[LD_LO]], <16 x i8> [[MASK1]])40// LE-PWR8-NEXT: [[TMP2:%.*]] = bitcast <4 x i32> [[SHUFFLE1]] to <16 x i8>41// LE-PWR8-NEXT: [[TMP3:%.*]] = shufflevector <16 x i8> [[TMP2]], <16 x i8> zeroinitializer, <16 x i32> <i32 0, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30>42// LE-PWR8-NEXT: ret <16 x i8> [[TMP3]]43//44// BE-PWR9-LABEL: @test_ldrmb1(45// BE-PWR9-NEXT: entry:46// BE-PWR9-NEXT: [[__A_ADDR_I:%.*]] = alloca ptr, align 847// BE-PWR9-NEXT: [[__B_ADDR_I:%.*]] = alloca i64, align 848// BE-PWR9-NEXT: [[__RES_I:%.*]] = alloca <16 x i8>, align 1649// BE-PWR9-NEXT: [[__MASK_I:%.*]] = alloca <16 x i8>, align 1650// BE-PWR9-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 851// BE-PWR9-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 852// BE-PWR9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 853// BE-PWR9-NEXT: store ptr [[TMP0]], ptr [[__A_ADDR_I]], align 854// BE-PWR9-NEXT: store i64 1, ptr [[__B_ADDR_I]], align 855// BE-PWR9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__A_ADDR_I]], align 856// BE-PWR9-NEXT: [[TMP2:%.*]] = load i64, ptr [[__B_ADDR_I]], align 857// BE-PWR9-NEXT: [[SHL_I:%.*]] = shl i64 [[TMP2]], 5658// BE-PWR9-NEXT: [[TMP3:%.*]] = call <4 x i32> @llvm.ppc.vsx.lxvll(ptr [[TMP1]], i64 [[SHL_I]])59// BE-PWR9-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP3]] to <16 x i8>60// BE-PWR9-NEXT: store <16 x i8> [[TMP4]], ptr [[__RES_I]], align 1661// BE-PWR9-NEXT: [[TMP5:%.*]] = load i64, ptr [[__B_ADDR_I]], align 862// BE-PWR9-NEXT: [[SUB_I:%.*]] = sub i64 16, [[TMP5]]63// BE-PWR9-NEXT: [[CONV_I:%.*]] = trunc i64 [[SUB_I]] to i864// BE-PWR9-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr null, i8 [[CONV_I]]65// BE-PWR9-NEXT: [[TMP7:%.*]] = call <16 x i8> @llvm.ppc.altivec.lvsr(ptr [[TMP6]])66// BE-PWR9-NEXT: store <16 x i8> [[TMP7]], ptr [[__MASK_I]], align 1667// BE-PWR9-NEXT: [[TMP8:%.*]] = load <16 x i8>, ptr [[__RES_I]], align 1668// BE-PWR9-NEXT: [[TMP9:%.*]] = bitcast <16 x i8> [[TMP8]] to <4 x i32>69// BE-PWR9-NEXT: [[TMP10:%.*]] = load <16 x i8>, ptr [[__RES_I]], align 1670// BE-PWR9-NEXT: [[TMP11:%.*]] = bitcast <16 x i8> [[TMP10]] to <4 x i32>71// BE-PWR9-NEXT: [[TMP12:%.*]] = load <16 x i8>, ptr [[__MASK_I]], align 1672// BE-PWR9-NEXT: [[TMP13:%.*]] = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> [[TMP9]], <4 x i32> [[TMP11]], <16 x i8> [[TMP12]])73// BE-PWR9-NEXT: [[TMP14:%.*]] = bitcast <4 x i32> [[TMP13]] to <16 x i8>74// BE-PWR9-NEXT: ret <16 x i8> [[TMP14]]75//76// LE-PWR9-LABEL: @test_ldrmb1(77// LE-PWR9-NEXT: entry:78// LE-PWR9-NEXT: [[__A_ADDR_I:%.*]] = alloca ptr, align 879// LE-PWR9-NEXT: [[__B_ADDR_I:%.*]] = alloca i64, align 880// LE-PWR9-NEXT: [[__RES_I:%.*]] = alloca <16 x i8>, align 1681// LE-PWR9-NEXT: [[__MASK_I:%.*]] = alloca <16 x i8>, align 1682// LE-PWR9-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 883// LE-PWR9-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 884// LE-PWR9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 885// LE-PWR9-NEXT: store ptr [[TMP0]], ptr [[__A_ADDR_I]], align 886// LE-PWR9-NEXT: store i64 1, ptr [[__B_ADDR_I]], align 887// LE-PWR9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__A_ADDR_I]], align 888// LE-PWR9-NEXT: [[TMP2:%.*]] = load i64, ptr [[__B_ADDR_I]], align 889// LE-PWR9-NEXT: [[SHL_I:%.*]] = shl i64 [[TMP2]], 5690// LE-PWR9-NEXT: [[TMP3:%.*]] = call <4 x i32> @llvm.ppc.vsx.lxvll(ptr [[TMP1]], i64 [[SHL_I]])91// LE-PWR9-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP3]] to <16 x i8>92// LE-PWR9-NEXT: store <16 x i8> [[TMP4]], ptr [[__RES_I]], align 1693// LE-PWR9-NEXT: [[TMP5:%.*]] = load i64, ptr [[__B_ADDR_I]], align 894// LE-PWR9-NEXT: [[SUB_I:%.*]] = sub i64 16, [[TMP5]]95// LE-PWR9-NEXT: [[CONV_I:%.*]] = trunc i64 [[SUB_I]] to i896// LE-PWR9-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr null, i8 [[CONV_I]]97// LE-PWR9-NEXT: [[TMP7:%.*]] = call <16 x i8> @llvm.ppc.altivec.lvsr(ptr [[TMP6]])98// LE-PWR9-NEXT: store <16 x i8> [[TMP7]], ptr [[__MASK_I]], align 1699// LE-PWR9-NEXT: [[TMP8:%.*]] = load <16 x i8>, ptr [[__RES_I]], align 16100// LE-PWR9-NEXT: [[TMP9:%.*]] = bitcast <16 x i8> [[TMP8]] to <4 x i32>101// LE-PWR9-NEXT: [[TMP10:%.*]] = load <16 x i8>, ptr [[__RES_I]], align 16102// LE-PWR9-NEXT: [[TMP11:%.*]] = bitcast <16 x i8> [[TMP10]] to <4 x i32>103// LE-PWR9-NEXT: [[TMP12:%.*]] = load <16 x i8>, ptr [[__MASK_I]], align 16104// LE-PWR9-NEXT: [[TMP13:%.*]] = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> [[TMP9]], <4 x i32> [[TMP11]], <16 x i8> [[TMP12]])105// LE-PWR9-NEXT: [[TMP14:%.*]] = bitcast <4 x i32> [[TMP13]] to <16 x i8>106// LE-PWR9-NEXT: ret <16 x i8> [[TMP14]]107//108// BE32-PWR9-LABEL: @test_ldrmb1(109// BE32-PWR9-NEXT: entry:110// BE32-PWR9-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 4111// BE32-PWR9-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 4112// BE32-PWR9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 4113// BE32-PWR9-NEXT: [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 0114// BE32-PWR9-NEXT: [[LD_LO:%.*]] = call <4 x i32> @llvm.ppc.altivec.lvx(ptr [[TMP0]])115// BE32-PWR9-NEXT: [[LD_HI:%.*]] = call <4 x i32> @llvm.ppc.altivec.lvx(ptr [[TMP1]])116// BE32-PWR9-NEXT: [[MASK1:%.*]] = call <16 x i8> @llvm.ppc.altivec.lvsl(ptr [[TMP0]])117// BE32-PWR9-NEXT: [[SHUFFLE1:%.*]] = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> [[LD_LO]], <4 x i32> [[LD_HI]], <16 x i8> [[MASK1]])118// BE32-PWR9-NEXT: [[SHUFFLE2:%.*]] = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> zeroinitializer, <4 x i32> [[SHUFFLE1]], <16 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 16>)119// BE32-PWR9-NEXT: [[TMP2:%.*]] = bitcast <4 x i32> [[SHUFFLE2]] to <16 x i8>120// BE32-PWR9-NEXT: ret <16 x i8> [[TMP2]]121//122vector unsigned char test_ldrmb1(char *ptr) { return __vec_ldrmb(ptr, 1); }123 124// BE-PWR8-LABEL: @test_strmb1(125// BE-PWR8-NEXT: entry:126// BE-PWR8-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8127// BE-PWR8-NEXT: [[DATA_ADDR:%.*]] = alloca <16 x i8>, align 16128// BE-PWR8-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 8129// BE-PWR8-NEXT: store <16 x i8> [[DATA:%.*]], ptr [[DATA_ADDR]], align 16130// BE-PWR8-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8131// BE-PWR8-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr [[DATA_ADDR]], align 16132// BE-PWR8-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP0]], i64 0133// BE-PWR8-NEXT: [[TMP3:%.*]] = extractelement <16 x i8> [[TMP1]], i64 15134// BE-PWR8-NEXT: store i8 [[TMP3]], ptr [[TMP2]], align 1135// BE-PWR8-NEXT: ret void136//137// LE-PWR8-LABEL: @test_strmb1(138// LE-PWR8-NEXT: entry:139// LE-PWR8-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8140// LE-PWR8-NEXT: [[DATA_ADDR:%.*]] = alloca <16 x i8>, align 16141// LE-PWR8-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 8142// LE-PWR8-NEXT: store <16 x i8> [[DATA:%.*]], ptr [[DATA_ADDR]], align 16143// LE-PWR8-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8144// LE-PWR8-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr [[DATA_ADDR]], align 16145// LE-PWR8-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP0]], i64 0146// LE-PWR8-NEXT: [[TMP3:%.*]] = extractelement <16 x i8> [[TMP1]], i64 0147// LE-PWR8-NEXT: store i8 [[TMP3]], ptr [[TMP2]], align 1148// LE-PWR8-NEXT: ret void149//150// BE-PWR9-LABEL: @test_strmb1(151// BE-PWR9-NEXT: entry:152// BE-PWR9-NEXT: [[__A_ADDR_I:%.*]] = alloca <16 x i8>, align 16153// BE-PWR9-NEXT: [[__B_ADDR_I:%.*]] = alloca ptr, align 8154// BE-PWR9-NEXT: [[__C_ADDR_I:%.*]] = alloca i64, align 8155// BE-PWR9-NEXT: [[__MASK_I:%.*]] = alloca <16 x i8>, align 16156// BE-PWR9-NEXT: [[__RES_I:%.*]] = alloca <16 x i8>, align 16157// BE-PWR9-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8158// BE-PWR9-NEXT: [[DATA_ADDR:%.*]] = alloca <16 x i8>, align 16159// BE-PWR9-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 8160// BE-PWR9-NEXT: store <16 x i8> [[DATA:%.*]], ptr [[DATA_ADDR]], align 16161// BE-PWR9-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr [[DATA_ADDR]], align 16162// BE-PWR9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8163// BE-PWR9-NEXT: store <16 x i8> [[TMP0]], ptr [[__A_ADDR_I]], align 16164// BE-PWR9-NEXT: store ptr [[TMP1]], ptr [[__B_ADDR_I]], align 8165// BE-PWR9-NEXT: store i64 1, ptr [[__C_ADDR_I]], align 8166// BE-PWR9-NEXT: [[TMP2:%.*]] = load i64, ptr [[__C_ADDR_I]], align 8167// BE-PWR9-NEXT: [[SUB_I:%.*]] = sub i64 16, [[TMP2]]168// BE-PWR9-NEXT: [[CONV_I:%.*]] = trunc i64 [[SUB_I]] to i8169// BE-PWR9-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr null, i8 [[CONV_I]]170// BE-PWR9-NEXT: [[TMP4:%.*]] = call <16 x i8> @llvm.ppc.altivec.lvsl(ptr [[TMP3]])171// BE-PWR9-NEXT: store <16 x i8> [[TMP4]], ptr [[__MASK_I]], align 16172// BE-PWR9-NEXT: [[TMP5:%.*]] = load <16 x i8>, ptr [[__A_ADDR_I]], align 16173// BE-PWR9-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x i32>174// BE-PWR9-NEXT: [[TMP7:%.*]] = load <16 x i8>, ptr [[__A_ADDR_I]], align 16175// BE-PWR9-NEXT: [[TMP8:%.*]] = bitcast <16 x i8> [[TMP7]] to <4 x i32>176// BE-PWR9-NEXT: [[TMP9:%.*]] = load <16 x i8>, ptr [[__MASK_I]], align 16177// BE-PWR9-NEXT: [[TMP10:%.*]] = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> [[TMP6]], <4 x i32> [[TMP8]], <16 x i8> [[TMP9]])178// BE-PWR9-NEXT: [[TMP11:%.*]] = bitcast <4 x i32> [[TMP10]] to <16 x i8>179// BE-PWR9-NEXT: store <16 x i8> [[TMP11]], ptr [[__RES_I]], align 16180// BE-PWR9-NEXT: [[TMP12:%.*]] = load <16 x i8>, ptr [[__RES_I]], align 16181// BE-PWR9-NEXT: [[TMP13:%.*]] = bitcast <16 x i8> [[TMP12]] to <4 x i32>182// BE-PWR9-NEXT: [[TMP14:%.*]] = load ptr, ptr [[__B_ADDR_I]], align 8183// BE-PWR9-NEXT: [[TMP15:%.*]] = load i64, ptr [[__C_ADDR_I]], align 8184// BE-PWR9-NEXT: [[SHL_I:%.*]] = shl i64 [[TMP15]], 56185// BE-PWR9-NEXT: call void @llvm.ppc.vsx.stxvll(<4 x i32> [[TMP13]], ptr [[TMP14]], i64 [[SHL_I]])186// BE-PWR9-NEXT: ret void187//188// LE-PWR9-LABEL: @test_strmb1(189// LE-PWR9-NEXT: entry:190// LE-PWR9-NEXT: [[__A_ADDR_I:%.*]] = alloca <16 x i8>, align 16191// LE-PWR9-NEXT: [[__B_ADDR_I:%.*]] = alloca ptr, align 8192// LE-PWR9-NEXT: [[__C_ADDR_I:%.*]] = alloca i64, align 8193// LE-PWR9-NEXT: [[__MASK_I:%.*]] = alloca <16 x i8>, align 16194// LE-PWR9-NEXT: [[__RES_I:%.*]] = alloca <16 x i8>, align 16195// LE-PWR9-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8196// LE-PWR9-NEXT: [[DATA_ADDR:%.*]] = alloca <16 x i8>, align 16197// LE-PWR9-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 8198// LE-PWR9-NEXT: store <16 x i8> [[DATA:%.*]], ptr [[DATA_ADDR]], align 16199// LE-PWR9-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr [[DATA_ADDR]], align 16200// LE-PWR9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8201// LE-PWR9-NEXT: store <16 x i8> [[TMP0]], ptr [[__A_ADDR_I]], align 16202// LE-PWR9-NEXT: store ptr [[TMP1]], ptr [[__B_ADDR_I]], align 8203// LE-PWR9-NEXT: store i64 1, ptr [[__C_ADDR_I]], align 8204// LE-PWR9-NEXT: [[TMP2:%.*]] = load i64, ptr [[__C_ADDR_I]], align 8205// LE-PWR9-NEXT: [[SUB_I:%.*]] = sub i64 16, [[TMP2]]206// LE-PWR9-NEXT: [[CONV_I:%.*]] = trunc i64 [[SUB_I]] to i8207// LE-PWR9-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr null, i8 [[CONV_I]]208// LE-PWR9-NEXT: [[TMP4:%.*]] = call <16 x i8> @llvm.ppc.altivec.lvsl(ptr [[TMP3]])209// LE-PWR9-NEXT: store <16 x i8> [[TMP4]], ptr [[__MASK_I]], align 16210// LE-PWR9-NEXT: [[TMP5:%.*]] = load <16 x i8>, ptr [[__A_ADDR_I]], align 16211// LE-PWR9-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x i32>212// LE-PWR9-NEXT: [[TMP7:%.*]] = load <16 x i8>, ptr [[__A_ADDR_I]], align 16213// LE-PWR9-NEXT: [[TMP8:%.*]] = bitcast <16 x i8> [[TMP7]] to <4 x i32>214// LE-PWR9-NEXT: [[TMP9:%.*]] = load <16 x i8>, ptr [[__MASK_I]], align 16215// LE-PWR9-NEXT: [[TMP10:%.*]] = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> [[TMP6]], <4 x i32> [[TMP8]], <16 x i8> [[TMP9]])216// LE-PWR9-NEXT: [[TMP11:%.*]] = bitcast <4 x i32> [[TMP10]] to <16 x i8>217// LE-PWR9-NEXT: store <16 x i8> [[TMP11]], ptr [[__RES_I]], align 16218// LE-PWR9-NEXT: [[TMP12:%.*]] = load <16 x i8>, ptr [[__RES_I]], align 16219// LE-PWR9-NEXT: [[TMP13:%.*]] = bitcast <16 x i8> [[TMP12]] to <4 x i32>220// LE-PWR9-NEXT: [[TMP14:%.*]] = load ptr, ptr [[__B_ADDR_I]], align 8221// LE-PWR9-NEXT: [[TMP15:%.*]] = load i64, ptr [[__C_ADDR_I]], align 8222// LE-PWR9-NEXT: [[SHL_I:%.*]] = shl i64 [[TMP15]], 56223// LE-PWR9-NEXT: call void @llvm.ppc.vsx.stxvll(<4 x i32> [[TMP13]], ptr [[TMP14]], i64 [[SHL_I]])224// LE-PWR9-NEXT: ret void225//226// BE32-PWR9-LABEL: @test_strmb1(227// BE32-PWR9-NEXT: entry:228// BE32-PWR9-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 4229// BE32-PWR9-NEXT: [[DATA_ADDR:%.*]] = alloca <16 x i8>, align 16230// BE32-PWR9-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 4231// BE32-PWR9-NEXT: store <16 x i8> [[DATA:%.*]], ptr [[DATA_ADDR]], align 16232// BE32-PWR9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 4233// BE32-PWR9-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr [[DATA_ADDR]], align 16234// BE32-PWR9-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP0]], i64 0235// BE32-PWR9-NEXT: [[TMP3:%.*]] = extractelement <16 x i8> [[TMP1]], i64 15236// BE32-PWR9-NEXT: store i8 [[TMP3]], ptr [[TMP2]], align 1237// BE32-PWR9-NEXT: ret void238//239void test_strmb1(char *ptr, vector unsigned char data) {240 __vec_strmb(ptr, 1, data);241}242 243// BE-PWR8-LABEL: @test_strmb2(244// BE-PWR8-NEXT: entry:245// BE-PWR8-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8246// BE-PWR8-NEXT: [[DATA_ADDR:%.*]] = alloca <16 x i8>, align 16247// BE-PWR8-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 8248// BE-PWR8-NEXT: store <16 x i8> [[DATA:%.*]], ptr [[DATA_ADDR]], align 16249// BE-PWR8-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8250// BE-PWR8-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr [[DATA_ADDR]], align 16251// BE-PWR8-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>252// BE-PWR8-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr [[TMP0]], i64 0253// BE-PWR8-NEXT: [[TMP5:%.*]] = extractelement <8 x i16> [[TMP2]], i64 7254// BE-PWR8-NEXT: store i16 [[TMP5]], ptr [[TMP3]], align 1255// BE-PWR8-NEXT: ret void256//257// LE-PWR8-LABEL: @test_strmb2(258// LE-PWR8-NEXT: entry:259// LE-PWR8-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8260// LE-PWR8-NEXT: [[DATA_ADDR:%.*]] = alloca <16 x i8>, align 16261// LE-PWR8-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 8262// LE-PWR8-NEXT: store <16 x i8> [[DATA:%.*]], ptr [[DATA_ADDR]], align 16263// LE-PWR8-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8264// LE-PWR8-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr [[DATA_ADDR]], align 16265// LE-PWR8-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>266// LE-PWR8-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr [[TMP0]], i64 0267// LE-PWR8-NEXT: [[TMP5:%.*]] = extractelement <8 x i16> [[TMP2]], i64 0268// LE-PWR8-NEXT: [[TMP6:%.*]] = call i16 @llvm.bswap.i16(i16 [[TMP5]])269// LE-PWR8-NEXT: store i16 [[TMP6]], ptr [[TMP3]], align 1270// LE-PWR8-NEXT: ret void271//272// BE-PWR9-LABEL: @test_strmb2(273// BE-PWR9-NEXT: entry:274// BE-PWR9-NEXT: [[__A_ADDR_I:%.*]] = alloca <16 x i8>, align 16275// BE-PWR9-NEXT: [[__B_ADDR_I:%.*]] = alloca ptr, align 8276// BE-PWR9-NEXT: [[__C_ADDR_I:%.*]] = alloca i64, align 8277// BE-PWR9-NEXT: [[__MASK_I:%.*]] = alloca <16 x i8>, align 16278// BE-PWR9-NEXT: [[__RES_I:%.*]] = alloca <16 x i8>, align 16279// BE-PWR9-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8280// BE-PWR9-NEXT: [[DATA_ADDR:%.*]] = alloca <16 x i8>, align 16281// BE-PWR9-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 8282// BE-PWR9-NEXT: store <16 x i8> [[DATA:%.*]], ptr [[DATA_ADDR]], align 16283// BE-PWR9-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr [[DATA_ADDR]], align 16284// BE-PWR9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8285// BE-PWR9-NEXT: store <16 x i8> [[TMP0]], ptr [[__A_ADDR_I]], align 16286// BE-PWR9-NEXT: store ptr [[TMP1]], ptr [[__B_ADDR_I]], align 8287// BE-PWR9-NEXT: store i64 2, ptr [[__C_ADDR_I]], align 8288// BE-PWR9-NEXT: [[TMP2:%.*]] = load i64, ptr [[__C_ADDR_I]], align 8289// BE-PWR9-NEXT: [[SUB_I:%.*]] = sub i64 16, [[TMP2]]290// BE-PWR9-NEXT: [[CONV_I:%.*]] = trunc i64 [[SUB_I]] to i8291// BE-PWR9-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr null, i8 [[CONV_I]]292// BE-PWR9-NEXT: [[TMP4:%.*]] = call <16 x i8> @llvm.ppc.altivec.lvsl(ptr [[TMP3]])293// BE-PWR9-NEXT: store <16 x i8> [[TMP4]], ptr [[__MASK_I]], align 16294// BE-PWR9-NEXT: [[TMP5:%.*]] = load <16 x i8>, ptr [[__A_ADDR_I]], align 16295// BE-PWR9-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x i32>296// BE-PWR9-NEXT: [[TMP7:%.*]] = load <16 x i8>, ptr [[__A_ADDR_I]], align 16297// BE-PWR9-NEXT: [[TMP8:%.*]] = bitcast <16 x i8> [[TMP7]] to <4 x i32>298// BE-PWR9-NEXT: [[TMP9:%.*]] = load <16 x i8>, ptr [[__MASK_I]], align 16299// BE-PWR9-NEXT: [[TMP10:%.*]] = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> [[TMP6]], <4 x i32> [[TMP8]], <16 x i8> [[TMP9]])300// BE-PWR9-NEXT: [[TMP11:%.*]] = bitcast <4 x i32> [[TMP10]] to <16 x i8>301// BE-PWR9-NEXT: store <16 x i8> [[TMP11]], ptr [[__RES_I]], align 16302// BE-PWR9-NEXT: [[TMP12:%.*]] = load <16 x i8>, ptr [[__RES_I]], align 16303// BE-PWR9-NEXT: [[TMP13:%.*]] = bitcast <16 x i8> [[TMP12]] to <4 x i32>304// BE-PWR9-NEXT: [[TMP14:%.*]] = load ptr, ptr [[__B_ADDR_I]], align 8305// BE-PWR9-NEXT: [[TMP15:%.*]] = load i64, ptr [[__C_ADDR_I]], align 8306// BE-PWR9-NEXT: [[SHL_I:%.*]] = shl i64 [[TMP15]], 56307// BE-PWR9-NEXT: call void @llvm.ppc.vsx.stxvll(<4 x i32> [[TMP13]], ptr [[TMP14]], i64 [[SHL_I]])308// BE-PWR9-NEXT: ret void309//310// LE-PWR9-LABEL: @test_strmb2(311// LE-PWR9-NEXT: entry:312// LE-PWR9-NEXT: [[__A_ADDR_I:%.*]] = alloca <16 x i8>, align 16313// LE-PWR9-NEXT: [[__B_ADDR_I:%.*]] = alloca ptr, align 8314// LE-PWR9-NEXT: [[__C_ADDR_I:%.*]] = alloca i64, align 8315// LE-PWR9-NEXT: [[__MASK_I:%.*]] = alloca <16 x i8>, align 16316// LE-PWR9-NEXT: [[__RES_I:%.*]] = alloca <16 x i8>, align 16317// LE-PWR9-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8318// LE-PWR9-NEXT: [[DATA_ADDR:%.*]] = alloca <16 x i8>, align 16319// LE-PWR9-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 8320// LE-PWR9-NEXT: store <16 x i8> [[DATA:%.*]], ptr [[DATA_ADDR]], align 16321// LE-PWR9-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr [[DATA_ADDR]], align 16322// LE-PWR9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8323// LE-PWR9-NEXT: store <16 x i8> [[TMP0]], ptr [[__A_ADDR_I]], align 16324// LE-PWR9-NEXT: store ptr [[TMP1]], ptr [[__B_ADDR_I]], align 8325// LE-PWR9-NEXT: store i64 2, ptr [[__C_ADDR_I]], align 8326// LE-PWR9-NEXT: [[TMP2:%.*]] = load i64, ptr [[__C_ADDR_I]], align 8327// LE-PWR9-NEXT: [[SUB_I:%.*]] = sub i64 16, [[TMP2]]328// LE-PWR9-NEXT: [[CONV_I:%.*]] = trunc i64 [[SUB_I]] to i8329// LE-PWR9-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr null, i8 [[CONV_I]]330// LE-PWR9-NEXT: [[TMP4:%.*]] = call <16 x i8> @llvm.ppc.altivec.lvsl(ptr [[TMP3]])331// LE-PWR9-NEXT: store <16 x i8> [[TMP4]], ptr [[__MASK_I]], align 16332// LE-PWR9-NEXT: [[TMP5:%.*]] = load <16 x i8>, ptr [[__A_ADDR_I]], align 16333// LE-PWR9-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x i32>334// LE-PWR9-NEXT: [[TMP7:%.*]] = load <16 x i8>, ptr [[__A_ADDR_I]], align 16335// LE-PWR9-NEXT: [[TMP8:%.*]] = bitcast <16 x i8> [[TMP7]] to <4 x i32>336// LE-PWR9-NEXT: [[TMP9:%.*]] = load <16 x i8>, ptr [[__MASK_I]], align 16337// LE-PWR9-NEXT: [[TMP10:%.*]] = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> [[TMP6]], <4 x i32> [[TMP8]], <16 x i8> [[TMP9]])338// LE-PWR9-NEXT: [[TMP11:%.*]] = bitcast <4 x i32> [[TMP10]] to <16 x i8>339// LE-PWR9-NEXT: store <16 x i8> [[TMP11]], ptr [[__RES_I]], align 16340// LE-PWR9-NEXT: [[TMP12:%.*]] = load <16 x i8>, ptr [[__RES_I]], align 16341// LE-PWR9-NEXT: [[TMP13:%.*]] = bitcast <16 x i8> [[TMP12]] to <4 x i32>342// LE-PWR9-NEXT: [[TMP14:%.*]] = load ptr, ptr [[__B_ADDR_I]], align 8343// LE-PWR9-NEXT: [[TMP15:%.*]] = load i64, ptr [[__C_ADDR_I]], align 8344// LE-PWR9-NEXT: [[SHL_I:%.*]] = shl i64 [[TMP15]], 56345// LE-PWR9-NEXT: call void @llvm.ppc.vsx.stxvll(<4 x i32> [[TMP13]], ptr [[TMP14]], i64 [[SHL_I]])346// LE-PWR9-NEXT: ret void347//348// BE32-PWR9-LABEL: @test_strmb2(349// BE32-PWR9-NEXT: entry:350// BE32-PWR9-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 4351// BE32-PWR9-NEXT: [[DATA_ADDR:%.*]] = alloca <16 x i8>, align 16352// BE32-PWR9-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 4353// BE32-PWR9-NEXT: store <16 x i8> [[DATA:%.*]], ptr [[DATA_ADDR]], align 16354// BE32-PWR9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 4355// BE32-PWR9-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr [[DATA_ADDR]], align 16356// BE32-PWR9-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>357// BE32-PWR9-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr [[TMP0]], i64 0358// BE32-PWR9-NEXT: [[TMP5:%.*]] = extractelement <8 x i16> [[TMP2]], i64 7359// BE32-PWR9-NEXT: store i16 [[TMP5]], ptr [[TMP3]], align 1360// BE32-PWR9-NEXT: ret void361//362void test_strmb2(char *ptr, vector unsigned char data) {363 __vec_strmb(ptr, 2, data);364}365 366// BE-PWR8-LABEL: @test_strmb3(367// BE-PWR8-NEXT: entry:368// BE-PWR8-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8369// BE-PWR8-NEXT: [[DATA_ADDR:%.*]] = alloca <16 x i8>, align 16370// BE-PWR8-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 8371// BE-PWR8-NEXT: store <16 x i8> [[DATA:%.*]], ptr [[DATA_ADDR]], align 16372// BE-PWR8-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8373// BE-PWR8-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr [[DATA_ADDR]], align 16374// BE-PWR8-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>375// BE-PWR8-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr [[TMP0]], i64 1376// BE-PWR8-NEXT: [[TMP5:%.*]] = extractelement <8 x i16> [[TMP2]], i64 7377// BE-PWR8-NEXT: store i16 [[TMP5]], ptr [[TMP3]], align 1378// BE-PWR8-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr [[TMP0]], i64 0379// BE-PWR8-NEXT: [[TMP7:%.*]] = extractelement <16 x i8> [[TMP1]], i64 13380// BE-PWR8-NEXT: store i8 [[TMP7]], ptr [[TMP6]], align 1381// BE-PWR8-NEXT: ret void382//383// LE-PWR8-LABEL: @test_strmb3(384// LE-PWR8-NEXT: entry:385// LE-PWR8-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8386// LE-PWR8-NEXT: [[DATA_ADDR:%.*]] = alloca <16 x i8>, align 16387// LE-PWR8-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 8388// LE-PWR8-NEXT: store <16 x i8> [[DATA:%.*]], ptr [[DATA_ADDR]], align 16389// LE-PWR8-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8390// LE-PWR8-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr [[DATA_ADDR]], align 16391// LE-PWR8-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>392// LE-PWR8-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr [[TMP0]], i64 1393// LE-PWR8-NEXT: [[TMP5:%.*]] = extractelement <8 x i16> [[TMP2]], i64 0394// LE-PWR8-NEXT: [[TMP6:%.*]] = call i16 @llvm.bswap.i16(i16 [[TMP5]])395// LE-PWR8-NEXT: store i16 [[TMP6]], ptr [[TMP3]], align 1396// LE-PWR8-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr [[TMP0]], i64 0397// LE-PWR8-NEXT: [[TMP8:%.*]] = extractelement <16 x i8> [[TMP1]], i64 2398// LE-PWR8-NEXT: store i8 [[TMP8]], ptr [[TMP7]], align 1399// LE-PWR8-NEXT: ret void400//401// BE-PWR9-LABEL: @test_strmb3(402// BE-PWR9-NEXT: entry:403// BE-PWR9-NEXT: [[__A_ADDR_I:%.*]] = alloca <16 x i8>, align 16404// BE-PWR9-NEXT: [[__B_ADDR_I:%.*]] = alloca ptr, align 8405// BE-PWR9-NEXT: [[__C_ADDR_I:%.*]] = alloca i64, align 8406// BE-PWR9-NEXT: [[__MASK_I:%.*]] = alloca <16 x i8>, align 16407// BE-PWR9-NEXT: [[__RES_I:%.*]] = alloca <16 x i8>, align 16408// BE-PWR9-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8409// BE-PWR9-NEXT: [[DATA_ADDR:%.*]] = alloca <16 x i8>, align 16410// BE-PWR9-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 8411// BE-PWR9-NEXT: store <16 x i8> [[DATA:%.*]], ptr [[DATA_ADDR]], align 16412// BE-PWR9-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr [[DATA_ADDR]], align 16413// BE-PWR9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8414// BE-PWR9-NEXT: store <16 x i8> [[TMP0]], ptr [[__A_ADDR_I]], align 16415// BE-PWR9-NEXT: store ptr [[TMP1]], ptr [[__B_ADDR_I]], align 8416// BE-PWR9-NEXT: store i64 3, ptr [[__C_ADDR_I]], align 8417// BE-PWR9-NEXT: [[TMP2:%.*]] = load i64, ptr [[__C_ADDR_I]], align 8418// BE-PWR9-NEXT: [[SUB_I:%.*]] = sub i64 16, [[TMP2]]419// BE-PWR9-NEXT: [[CONV_I:%.*]] = trunc i64 [[SUB_I]] to i8420// BE-PWR9-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr null, i8 [[CONV_I]]421// BE-PWR9-NEXT: [[TMP4:%.*]] = call <16 x i8> @llvm.ppc.altivec.lvsl(ptr [[TMP3]])422// BE-PWR9-NEXT: store <16 x i8> [[TMP4]], ptr [[__MASK_I]], align 16423// BE-PWR9-NEXT: [[TMP5:%.*]] = load <16 x i8>, ptr [[__A_ADDR_I]], align 16424// BE-PWR9-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x i32>425// BE-PWR9-NEXT: [[TMP7:%.*]] = load <16 x i8>, ptr [[__A_ADDR_I]], align 16426// BE-PWR9-NEXT: [[TMP8:%.*]] = bitcast <16 x i8> [[TMP7]] to <4 x i32>427// BE-PWR9-NEXT: [[TMP9:%.*]] = load <16 x i8>, ptr [[__MASK_I]], align 16428// BE-PWR9-NEXT: [[TMP10:%.*]] = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> [[TMP6]], <4 x i32> [[TMP8]], <16 x i8> [[TMP9]])429// BE-PWR9-NEXT: [[TMP11:%.*]] = bitcast <4 x i32> [[TMP10]] to <16 x i8>430// BE-PWR9-NEXT: store <16 x i8> [[TMP11]], ptr [[__RES_I]], align 16431// BE-PWR9-NEXT: [[TMP12:%.*]] = load <16 x i8>, ptr [[__RES_I]], align 16432// BE-PWR9-NEXT: [[TMP13:%.*]] = bitcast <16 x i8> [[TMP12]] to <4 x i32>433// BE-PWR9-NEXT: [[TMP14:%.*]] = load ptr, ptr [[__B_ADDR_I]], align 8434// BE-PWR9-NEXT: [[TMP15:%.*]] = load i64, ptr [[__C_ADDR_I]], align 8435// BE-PWR9-NEXT: [[SHL_I:%.*]] = shl i64 [[TMP15]], 56436// BE-PWR9-NEXT: call void @llvm.ppc.vsx.stxvll(<4 x i32> [[TMP13]], ptr [[TMP14]], i64 [[SHL_I]])437// BE-PWR9-NEXT: ret void438//439// LE-PWR9-LABEL: @test_strmb3(440// LE-PWR9-NEXT: entry:441// LE-PWR9-NEXT: [[__A_ADDR_I:%.*]] = alloca <16 x i8>, align 16442// LE-PWR9-NEXT: [[__B_ADDR_I:%.*]] = alloca ptr, align 8443// LE-PWR9-NEXT: [[__C_ADDR_I:%.*]] = alloca i64, align 8444// LE-PWR9-NEXT: [[__MASK_I:%.*]] = alloca <16 x i8>, align 16445// LE-PWR9-NEXT: [[__RES_I:%.*]] = alloca <16 x i8>, align 16446// LE-PWR9-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8447// LE-PWR9-NEXT: [[DATA_ADDR:%.*]] = alloca <16 x i8>, align 16448// LE-PWR9-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 8449// LE-PWR9-NEXT: store <16 x i8> [[DATA:%.*]], ptr [[DATA_ADDR]], align 16450// LE-PWR9-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr [[DATA_ADDR]], align 16451// LE-PWR9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8452// LE-PWR9-NEXT: store <16 x i8> [[TMP0]], ptr [[__A_ADDR_I]], align 16453// LE-PWR9-NEXT: store ptr [[TMP1]], ptr [[__B_ADDR_I]], align 8454// LE-PWR9-NEXT: store i64 3, ptr [[__C_ADDR_I]], align 8455// LE-PWR9-NEXT: [[TMP2:%.*]] = load i64, ptr [[__C_ADDR_I]], align 8456// LE-PWR9-NEXT: [[SUB_I:%.*]] = sub i64 16, [[TMP2]]457// LE-PWR9-NEXT: [[CONV_I:%.*]] = trunc i64 [[SUB_I]] to i8458// LE-PWR9-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr null, i8 [[CONV_I]]459// LE-PWR9-NEXT: [[TMP4:%.*]] = call <16 x i8> @llvm.ppc.altivec.lvsl(ptr [[TMP3]])460// LE-PWR9-NEXT: store <16 x i8> [[TMP4]], ptr [[__MASK_I]], align 16461// LE-PWR9-NEXT: [[TMP5:%.*]] = load <16 x i8>, ptr [[__A_ADDR_I]], align 16462// LE-PWR9-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x i32>463// LE-PWR9-NEXT: [[TMP7:%.*]] = load <16 x i8>, ptr [[__A_ADDR_I]], align 16464// LE-PWR9-NEXT: [[TMP8:%.*]] = bitcast <16 x i8> [[TMP7]] to <4 x i32>465// LE-PWR9-NEXT: [[TMP9:%.*]] = load <16 x i8>, ptr [[__MASK_I]], align 16466// LE-PWR9-NEXT: [[TMP10:%.*]] = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> [[TMP6]], <4 x i32> [[TMP8]], <16 x i8> [[TMP9]])467// LE-PWR9-NEXT: [[TMP11:%.*]] = bitcast <4 x i32> [[TMP10]] to <16 x i8>468// LE-PWR9-NEXT: store <16 x i8> [[TMP11]], ptr [[__RES_I]], align 16469// LE-PWR9-NEXT: [[TMP12:%.*]] = load <16 x i8>, ptr [[__RES_I]], align 16470// LE-PWR9-NEXT: [[TMP13:%.*]] = bitcast <16 x i8> [[TMP12]] to <4 x i32>471// LE-PWR9-NEXT: [[TMP14:%.*]] = load ptr, ptr [[__B_ADDR_I]], align 8472// LE-PWR9-NEXT: [[TMP15:%.*]] = load i64, ptr [[__C_ADDR_I]], align 8473// LE-PWR9-NEXT: [[SHL_I:%.*]] = shl i64 [[TMP15]], 56474// LE-PWR9-NEXT: call void @llvm.ppc.vsx.stxvll(<4 x i32> [[TMP13]], ptr [[TMP14]], i64 [[SHL_I]])475// LE-PWR9-NEXT: ret void476//477// BE32-PWR9-LABEL: @test_strmb3(478// BE32-PWR9-NEXT: entry:479// BE32-PWR9-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 4480// BE32-PWR9-NEXT: [[DATA_ADDR:%.*]] = alloca <16 x i8>, align 16481// BE32-PWR9-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 4482// BE32-PWR9-NEXT: store <16 x i8> [[DATA:%.*]], ptr [[DATA_ADDR]], align 16483// BE32-PWR9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 4484// BE32-PWR9-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr [[DATA_ADDR]], align 16485// BE32-PWR9-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>486// BE32-PWR9-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr [[TMP0]], i64 1487// BE32-PWR9-NEXT: [[TMP5:%.*]] = extractelement <8 x i16> [[TMP2]], i64 7488// BE32-PWR9-NEXT: store i16 [[TMP5]], ptr [[TMP3]], align 1489// BE32-PWR9-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr [[TMP0]], i64 0490// BE32-PWR9-NEXT: [[TMP7:%.*]] = extractelement <16 x i8> [[TMP1]], i64 13491// BE32-PWR9-NEXT: store i8 [[TMP7]], ptr [[TMP6]], align 1492// BE32-PWR9-NEXT: ret void493//494void test_strmb3(char *ptr, vector unsigned char data) {495 __vec_strmb(ptr, 3, data);496}497 498// BE-PWR8-LABEL: @test_strmb4(499// BE-PWR8-NEXT: entry:500// BE-PWR8-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8501// BE-PWR8-NEXT: [[DATA_ADDR:%.*]] = alloca <16 x i8>, align 16502// BE-PWR8-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 8503// BE-PWR8-NEXT: store <16 x i8> [[DATA:%.*]], ptr [[DATA_ADDR]], align 16504// BE-PWR8-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8505// BE-PWR8-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr [[DATA_ADDR]], align 16506// BE-PWR8-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>507// BE-PWR8-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr [[TMP0]], i64 0508// BE-PWR8-NEXT: [[TMP5:%.*]] = extractelement <4 x i32> [[TMP2]], i64 3509// BE-PWR8-NEXT: store i32 [[TMP5]], ptr [[TMP3]], align 1510// BE-PWR8-NEXT: ret void511//512// LE-PWR8-LABEL: @test_strmb4(513// LE-PWR8-NEXT: entry:514// LE-PWR8-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8515// LE-PWR8-NEXT: [[DATA_ADDR:%.*]] = alloca <16 x i8>, align 16516// LE-PWR8-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 8517// LE-PWR8-NEXT: store <16 x i8> [[DATA:%.*]], ptr [[DATA_ADDR]], align 16518// LE-PWR8-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8519// LE-PWR8-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr [[DATA_ADDR]], align 16520// LE-PWR8-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>521// LE-PWR8-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr [[TMP0]], i64 0522// LE-PWR8-NEXT: [[TMP5:%.*]] = extractelement <4 x i32> [[TMP2]], i64 0523// LE-PWR8-NEXT: [[TMP6:%.*]] = call i32 @llvm.bswap.i32(i32 [[TMP5]])524// LE-PWR8-NEXT: store i32 [[TMP6]], ptr [[TMP3]], align 1525// LE-PWR8-NEXT: ret void526//527// BE-PWR9-LABEL: @test_strmb4(528// BE-PWR9-NEXT: entry:529// BE-PWR9-NEXT: [[__A_ADDR_I:%.*]] = alloca <16 x i8>, align 16530// BE-PWR9-NEXT: [[__B_ADDR_I:%.*]] = alloca ptr, align 8531// BE-PWR9-NEXT: [[__C_ADDR_I:%.*]] = alloca i64, align 8532// BE-PWR9-NEXT: [[__MASK_I:%.*]] = alloca <16 x i8>, align 16533// BE-PWR9-NEXT: [[__RES_I:%.*]] = alloca <16 x i8>, align 16534// BE-PWR9-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8535// BE-PWR9-NEXT: [[DATA_ADDR:%.*]] = alloca <16 x i8>, align 16536// BE-PWR9-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 8537// BE-PWR9-NEXT: store <16 x i8> [[DATA:%.*]], ptr [[DATA_ADDR]], align 16538// BE-PWR9-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr [[DATA_ADDR]], align 16539// BE-PWR9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8540// BE-PWR9-NEXT: store <16 x i8> [[TMP0]], ptr [[__A_ADDR_I]], align 16541// BE-PWR9-NEXT: store ptr [[TMP1]], ptr [[__B_ADDR_I]], align 8542// BE-PWR9-NEXT: store i64 4, ptr [[__C_ADDR_I]], align 8543// BE-PWR9-NEXT: [[TMP2:%.*]] = load i64, ptr [[__C_ADDR_I]], align 8544// BE-PWR9-NEXT: [[SUB_I:%.*]] = sub i64 16, [[TMP2]]545// BE-PWR9-NEXT: [[CONV_I:%.*]] = trunc i64 [[SUB_I]] to i8546// BE-PWR9-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr null, i8 [[CONV_I]]547// BE-PWR9-NEXT: [[TMP4:%.*]] = call <16 x i8> @llvm.ppc.altivec.lvsl(ptr [[TMP3]])548// BE-PWR9-NEXT: store <16 x i8> [[TMP4]], ptr [[__MASK_I]], align 16549// BE-PWR9-NEXT: [[TMP5:%.*]] = load <16 x i8>, ptr [[__A_ADDR_I]], align 16550// BE-PWR9-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x i32>551// BE-PWR9-NEXT: [[TMP7:%.*]] = load <16 x i8>, ptr [[__A_ADDR_I]], align 16552// BE-PWR9-NEXT: [[TMP8:%.*]] = bitcast <16 x i8> [[TMP7]] to <4 x i32>553// BE-PWR9-NEXT: [[TMP9:%.*]] = load <16 x i8>, ptr [[__MASK_I]], align 16554// BE-PWR9-NEXT: [[TMP10:%.*]] = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> [[TMP6]], <4 x i32> [[TMP8]], <16 x i8> [[TMP9]])555// BE-PWR9-NEXT: [[TMP11:%.*]] = bitcast <4 x i32> [[TMP10]] to <16 x i8>556// BE-PWR9-NEXT: store <16 x i8> [[TMP11]], ptr [[__RES_I]], align 16557// BE-PWR9-NEXT: [[TMP12:%.*]] = load <16 x i8>, ptr [[__RES_I]], align 16558// BE-PWR9-NEXT: [[TMP13:%.*]] = bitcast <16 x i8> [[TMP12]] to <4 x i32>559// BE-PWR9-NEXT: [[TMP14:%.*]] = load ptr, ptr [[__B_ADDR_I]], align 8560// BE-PWR9-NEXT: [[TMP15:%.*]] = load i64, ptr [[__C_ADDR_I]], align 8561// BE-PWR9-NEXT: [[SHL_I:%.*]] = shl i64 [[TMP15]], 56562// BE-PWR9-NEXT: call void @llvm.ppc.vsx.stxvll(<4 x i32> [[TMP13]], ptr [[TMP14]], i64 [[SHL_I]])563// BE-PWR9-NEXT: ret void564//565// LE-PWR9-LABEL: @test_strmb4(566// LE-PWR9-NEXT: entry:567// LE-PWR9-NEXT: [[__A_ADDR_I:%.*]] = alloca <16 x i8>, align 16568// LE-PWR9-NEXT: [[__B_ADDR_I:%.*]] = alloca ptr, align 8569// LE-PWR9-NEXT: [[__C_ADDR_I:%.*]] = alloca i64, align 8570// LE-PWR9-NEXT: [[__MASK_I:%.*]] = alloca <16 x i8>, align 16571// LE-PWR9-NEXT: [[__RES_I:%.*]] = alloca <16 x i8>, align 16572// LE-PWR9-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8573// LE-PWR9-NEXT: [[DATA_ADDR:%.*]] = alloca <16 x i8>, align 16574// LE-PWR9-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 8575// LE-PWR9-NEXT: store <16 x i8> [[DATA:%.*]], ptr [[DATA_ADDR]], align 16576// LE-PWR9-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr [[DATA_ADDR]], align 16577// LE-PWR9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8578// LE-PWR9-NEXT: store <16 x i8> [[TMP0]], ptr [[__A_ADDR_I]], align 16579// LE-PWR9-NEXT: store ptr [[TMP1]], ptr [[__B_ADDR_I]], align 8580// LE-PWR9-NEXT: store i64 4, ptr [[__C_ADDR_I]], align 8581// LE-PWR9-NEXT: [[TMP2:%.*]] = load i64, ptr [[__C_ADDR_I]], align 8582// LE-PWR9-NEXT: [[SUB_I:%.*]] = sub i64 16, [[TMP2]]583// LE-PWR9-NEXT: [[CONV_I:%.*]] = trunc i64 [[SUB_I]] to i8584// LE-PWR9-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr null, i8 [[CONV_I]]585// LE-PWR9-NEXT: [[TMP4:%.*]] = call <16 x i8> @llvm.ppc.altivec.lvsl(ptr [[TMP3]])586// LE-PWR9-NEXT: store <16 x i8> [[TMP4]], ptr [[__MASK_I]], align 16587// LE-PWR9-NEXT: [[TMP5:%.*]] = load <16 x i8>, ptr [[__A_ADDR_I]], align 16588// LE-PWR9-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x i32>589// LE-PWR9-NEXT: [[TMP7:%.*]] = load <16 x i8>, ptr [[__A_ADDR_I]], align 16590// LE-PWR9-NEXT: [[TMP8:%.*]] = bitcast <16 x i8> [[TMP7]] to <4 x i32>591// LE-PWR9-NEXT: [[TMP9:%.*]] = load <16 x i8>, ptr [[__MASK_I]], align 16592// LE-PWR9-NEXT: [[TMP10:%.*]] = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> [[TMP6]], <4 x i32> [[TMP8]], <16 x i8> [[TMP9]])593// LE-PWR9-NEXT: [[TMP11:%.*]] = bitcast <4 x i32> [[TMP10]] to <16 x i8>594// LE-PWR9-NEXT: store <16 x i8> [[TMP11]], ptr [[__RES_I]], align 16595// LE-PWR9-NEXT: [[TMP12:%.*]] = load <16 x i8>, ptr [[__RES_I]], align 16596// LE-PWR9-NEXT: [[TMP13:%.*]] = bitcast <16 x i8> [[TMP12]] to <4 x i32>597// LE-PWR9-NEXT: [[TMP14:%.*]] = load ptr, ptr [[__B_ADDR_I]], align 8598// LE-PWR9-NEXT: [[TMP15:%.*]] = load i64, ptr [[__C_ADDR_I]], align 8599// LE-PWR9-NEXT: [[SHL_I:%.*]] = shl i64 [[TMP15]], 56600// LE-PWR9-NEXT: call void @llvm.ppc.vsx.stxvll(<4 x i32> [[TMP13]], ptr [[TMP14]], i64 [[SHL_I]])601// LE-PWR9-NEXT: ret void602//603// BE32-PWR9-LABEL: @test_strmb4(604// BE32-PWR9-NEXT: entry:605// BE32-PWR9-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 4606// BE32-PWR9-NEXT: [[DATA_ADDR:%.*]] = alloca <16 x i8>, align 16607// BE32-PWR9-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 4608// BE32-PWR9-NEXT: store <16 x i8> [[DATA:%.*]], ptr [[DATA_ADDR]], align 16609// BE32-PWR9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 4610// BE32-PWR9-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr [[DATA_ADDR]], align 16611// BE32-PWR9-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>612// BE32-PWR9-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr [[TMP0]], i64 0613// BE32-PWR9-NEXT: [[TMP5:%.*]] = extractelement <4 x i32> [[TMP2]], i64 3614// BE32-PWR9-NEXT: store i32 [[TMP5]], ptr [[TMP3]], align 1615// BE32-PWR9-NEXT: ret void616//617void test_strmb4(char *ptr, vector unsigned char data) {618 __vec_strmb(ptr, 4, data);619}620 621// BE-PWR8-LABEL: @test_strmb5(622// BE-PWR8-NEXT: entry:623// BE-PWR8-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8624// BE-PWR8-NEXT: [[DATA_ADDR:%.*]] = alloca <16 x i8>, align 16625// BE-PWR8-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 8626// BE-PWR8-NEXT: store <16 x i8> [[DATA:%.*]], ptr [[DATA_ADDR]], align 16627// BE-PWR8-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8628// BE-PWR8-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr [[DATA_ADDR]], align 16629// BE-PWR8-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>630// BE-PWR8-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr [[TMP0]], i64 1631// BE-PWR8-NEXT: [[TMP5:%.*]] = extractelement <4 x i32> [[TMP2]], i64 3632// BE-PWR8-NEXT: store i32 [[TMP5]], ptr [[TMP3]], align 1633// BE-PWR8-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr [[TMP0]], i64 0634// BE-PWR8-NEXT: [[TMP7:%.*]] = extractelement <16 x i8> [[TMP1]], i64 11635// BE-PWR8-NEXT: store i8 [[TMP7]], ptr [[TMP6]], align 1636// BE-PWR8-NEXT: ret void637//638// LE-PWR8-LABEL: @test_strmb5(639// LE-PWR8-NEXT: entry:640// LE-PWR8-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8641// LE-PWR8-NEXT: [[DATA_ADDR:%.*]] = alloca <16 x i8>, align 16642// LE-PWR8-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 8643// LE-PWR8-NEXT: store <16 x i8> [[DATA:%.*]], ptr [[DATA_ADDR]], align 16644// LE-PWR8-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8645// LE-PWR8-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr [[DATA_ADDR]], align 16646// LE-PWR8-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>647// LE-PWR8-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr [[TMP0]], i64 1648// LE-PWR8-NEXT: [[TMP5:%.*]] = extractelement <4 x i32> [[TMP2]], i64 0649// LE-PWR8-NEXT: [[TMP6:%.*]] = call i32 @llvm.bswap.i32(i32 [[TMP5]])650// LE-PWR8-NEXT: store i32 [[TMP6]], ptr [[TMP3]], align 1651// LE-PWR8-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr [[TMP0]], i64 0652// LE-PWR8-NEXT: [[TMP8:%.*]] = extractelement <16 x i8> [[TMP1]], i64 4653// LE-PWR8-NEXT: store i8 [[TMP8]], ptr [[TMP7]], align 1654// LE-PWR8-NEXT: ret void655//656// BE-PWR9-LABEL: @test_strmb5(657// BE-PWR9-NEXT: entry:658// BE-PWR9-NEXT: [[__A_ADDR_I:%.*]] = alloca <16 x i8>, align 16659// BE-PWR9-NEXT: [[__B_ADDR_I:%.*]] = alloca ptr, align 8660// BE-PWR9-NEXT: [[__C_ADDR_I:%.*]] = alloca i64, align 8661// BE-PWR9-NEXT: [[__MASK_I:%.*]] = alloca <16 x i8>, align 16662// BE-PWR9-NEXT: [[__RES_I:%.*]] = alloca <16 x i8>, align 16663// BE-PWR9-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8664// BE-PWR9-NEXT: [[DATA_ADDR:%.*]] = alloca <16 x i8>, align 16665// BE-PWR9-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 8666// BE-PWR9-NEXT: store <16 x i8> [[DATA:%.*]], ptr [[DATA_ADDR]], align 16667// BE-PWR9-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr [[DATA_ADDR]], align 16668// BE-PWR9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8669// BE-PWR9-NEXT: store <16 x i8> [[TMP0]], ptr [[__A_ADDR_I]], align 16670// BE-PWR9-NEXT: store ptr [[TMP1]], ptr [[__B_ADDR_I]], align 8671// BE-PWR9-NEXT: store i64 5, ptr [[__C_ADDR_I]], align 8672// BE-PWR9-NEXT: [[TMP2:%.*]] = load i64, ptr [[__C_ADDR_I]], align 8673// BE-PWR9-NEXT: [[SUB_I:%.*]] = sub i64 16, [[TMP2]]674// BE-PWR9-NEXT: [[CONV_I:%.*]] = trunc i64 [[SUB_I]] to i8675// BE-PWR9-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr null, i8 [[CONV_I]]676// BE-PWR9-NEXT: [[TMP4:%.*]] = call <16 x i8> @llvm.ppc.altivec.lvsl(ptr [[TMP3]])677// BE-PWR9-NEXT: store <16 x i8> [[TMP4]], ptr [[__MASK_I]], align 16678// BE-PWR9-NEXT: [[TMP5:%.*]] = load <16 x i8>, ptr [[__A_ADDR_I]], align 16679// BE-PWR9-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x i32>680// BE-PWR9-NEXT: [[TMP7:%.*]] = load <16 x i8>, ptr [[__A_ADDR_I]], align 16681// BE-PWR9-NEXT: [[TMP8:%.*]] = bitcast <16 x i8> [[TMP7]] to <4 x i32>682// BE-PWR9-NEXT: [[TMP9:%.*]] = load <16 x i8>, ptr [[__MASK_I]], align 16683// BE-PWR9-NEXT: [[TMP10:%.*]] = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> [[TMP6]], <4 x i32> [[TMP8]], <16 x i8> [[TMP9]])684// BE-PWR9-NEXT: [[TMP11:%.*]] = bitcast <4 x i32> [[TMP10]] to <16 x i8>685// BE-PWR9-NEXT: store <16 x i8> [[TMP11]], ptr [[__RES_I]], align 16686// BE-PWR9-NEXT: [[TMP12:%.*]] = load <16 x i8>, ptr [[__RES_I]], align 16687// BE-PWR9-NEXT: [[TMP13:%.*]] = bitcast <16 x i8> [[TMP12]] to <4 x i32>688// BE-PWR9-NEXT: [[TMP14:%.*]] = load ptr, ptr [[__B_ADDR_I]], align 8689// BE-PWR9-NEXT: [[TMP15:%.*]] = load i64, ptr [[__C_ADDR_I]], align 8690// BE-PWR9-NEXT: [[SHL_I:%.*]] = shl i64 [[TMP15]], 56691// BE-PWR9-NEXT: call void @llvm.ppc.vsx.stxvll(<4 x i32> [[TMP13]], ptr [[TMP14]], i64 [[SHL_I]])692// BE-PWR9-NEXT: ret void693//694// LE-PWR9-LABEL: @test_strmb5(695// LE-PWR9-NEXT: entry:696// LE-PWR9-NEXT: [[__A_ADDR_I:%.*]] = alloca <16 x i8>, align 16697// LE-PWR9-NEXT: [[__B_ADDR_I:%.*]] = alloca ptr, align 8698// LE-PWR9-NEXT: [[__C_ADDR_I:%.*]] = alloca i64, align 8699// LE-PWR9-NEXT: [[__MASK_I:%.*]] = alloca <16 x i8>, align 16700// LE-PWR9-NEXT: [[__RES_I:%.*]] = alloca <16 x i8>, align 16701// LE-PWR9-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8702// LE-PWR9-NEXT: [[DATA_ADDR:%.*]] = alloca <16 x i8>, align 16703// LE-PWR9-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 8704// LE-PWR9-NEXT: store <16 x i8> [[DATA:%.*]], ptr [[DATA_ADDR]], align 16705// LE-PWR9-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr [[DATA_ADDR]], align 16706// LE-PWR9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8707// LE-PWR9-NEXT: store <16 x i8> [[TMP0]], ptr [[__A_ADDR_I]], align 16708// LE-PWR9-NEXT: store ptr [[TMP1]], ptr [[__B_ADDR_I]], align 8709// LE-PWR9-NEXT: store i64 5, ptr [[__C_ADDR_I]], align 8710// LE-PWR9-NEXT: [[TMP2:%.*]] = load i64, ptr [[__C_ADDR_I]], align 8711// LE-PWR9-NEXT: [[SUB_I:%.*]] = sub i64 16, [[TMP2]]712// LE-PWR9-NEXT: [[CONV_I:%.*]] = trunc i64 [[SUB_I]] to i8713// LE-PWR9-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr null, i8 [[CONV_I]]714// LE-PWR9-NEXT: [[TMP4:%.*]] = call <16 x i8> @llvm.ppc.altivec.lvsl(ptr [[TMP3]])715// LE-PWR9-NEXT: store <16 x i8> [[TMP4]], ptr [[__MASK_I]], align 16716// LE-PWR9-NEXT: [[TMP5:%.*]] = load <16 x i8>, ptr [[__A_ADDR_I]], align 16717// LE-PWR9-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x i32>718// LE-PWR9-NEXT: [[TMP7:%.*]] = load <16 x i8>, ptr [[__A_ADDR_I]], align 16719// LE-PWR9-NEXT: [[TMP8:%.*]] = bitcast <16 x i8> [[TMP7]] to <4 x i32>720// LE-PWR9-NEXT: [[TMP9:%.*]] = load <16 x i8>, ptr [[__MASK_I]], align 16721// LE-PWR9-NEXT: [[TMP10:%.*]] = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> [[TMP6]], <4 x i32> [[TMP8]], <16 x i8> [[TMP9]])722// LE-PWR9-NEXT: [[TMP11:%.*]] = bitcast <4 x i32> [[TMP10]] to <16 x i8>723// LE-PWR9-NEXT: store <16 x i8> [[TMP11]], ptr [[__RES_I]], align 16724// LE-PWR9-NEXT: [[TMP12:%.*]] = load <16 x i8>, ptr [[__RES_I]], align 16725// LE-PWR9-NEXT: [[TMP13:%.*]] = bitcast <16 x i8> [[TMP12]] to <4 x i32>726// LE-PWR9-NEXT: [[TMP14:%.*]] = load ptr, ptr [[__B_ADDR_I]], align 8727// LE-PWR9-NEXT: [[TMP15:%.*]] = load i64, ptr [[__C_ADDR_I]], align 8728// LE-PWR9-NEXT: [[SHL_I:%.*]] = shl i64 [[TMP15]], 56729// LE-PWR9-NEXT: call void @llvm.ppc.vsx.stxvll(<4 x i32> [[TMP13]], ptr [[TMP14]], i64 [[SHL_I]])730// LE-PWR9-NEXT: ret void731//732// BE32-PWR9-LABEL: @test_strmb5(733// BE32-PWR9-NEXT: entry:734// BE32-PWR9-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 4735// BE32-PWR9-NEXT: [[DATA_ADDR:%.*]] = alloca <16 x i8>, align 16736// BE32-PWR9-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 4737// BE32-PWR9-NEXT: store <16 x i8> [[DATA:%.*]], ptr [[DATA_ADDR]], align 16738// BE32-PWR9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 4739// BE32-PWR9-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr [[DATA_ADDR]], align 16740// BE32-PWR9-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>741// BE32-PWR9-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr [[TMP0]], i64 1742// BE32-PWR9-NEXT: [[TMP5:%.*]] = extractelement <4 x i32> [[TMP2]], i64 3743// BE32-PWR9-NEXT: store i32 [[TMP5]], ptr [[TMP3]], align 1744// BE32-PWR9-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr [[TMP0]], i64 0745// BE32-PWR9-NEXT: [[TMP7:%.*]] = extractelement <16 x i8> [[TMP1]], i64 11746// BE32-PWR9-NEXT: store i8 [[TMP7]], ptr [[TMP6]], align 1747// BE32-PWR9-NEXT: ret void748//749void test_strmb5(char *ptr, vector unsigned char data) {750 __vec_strmb(ptr, 5, data);751}752 753// BE-PWR8-LABEL: @test_strmb6(754// BE-PWR8-NEXT: entry:755// BE-PWR8-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8756// BE-PWR8-NEXT: [[DATA_ADDR:%.*]] = alloca <16 x i8>, align 16757// BE-PWR8-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 8758// BE-PWR8-NEXT: store <16 x i8> [[DATA:%.*]], ptr [[DATA_ADDR]], align 16759// BE-PWR8-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8760// BE-PWR8-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr [[DATA_ADDR]], align 16761// BE-PWR8-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>762// BE-PWR8-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr [[TMP0]], i64 2763// BE-PWR8-NEXT: [[TMP5:%.*]] = extractelement <4 x i32> [[TMP2]], i64 3764// BE-PWR8-NEXT: store i32 [[TMP5]], ptr [[TMP3]], align 1765// BE-PWR8-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>766// BE-PWR8-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr [[TMP0]], i64 0767// BE-PWR8-NEXT: [[TMP9:%.*]] = extractelement <8 x i16> [[TMP6]], i64 5768// BE-PWR8-NEXT: store i16 [[TMP9]], ptr [[TMP7]], align 1769// BE-PWR8-NEXT: ret void770//771// LE-PWR8-LABEL: @test_strmb6(772// LE-PWR8-NEXT: entry:773// LE-PWR8-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8774// LE-PWR8-NEXT: [[DATA_ADDR:%.*]] = alloca <16 x i8>, align 16775// LE-PWR8-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 8776// LE-PWR8-NEXT: store <16 x i8> [[DATA:%.*]], ptr [[DATA_ADDR]], align 16777// LE-PWR8-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8778// LE-PWR8-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr [[DATA_ADDR]], align 16779// LE-PWR8-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>780// LE-PWR8-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr [[TMP0]], i64 2781// LE-PWR8-NEXT: [[TMP5:%.*]] = extractelement <4 x i32> [[TMP2]], i64 0782// LE-PWR8-NEXT: [[TMP6:%.*]] = call i32 @llvm.bswap.i32(i32 [[TMP5]])783// LE-PWR8-NEXT: store i32 [[TMP6]], ptr [[TMP3]], align 1784// LE-PWR8-NEXT: [[TMP7:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>785// LE-PWR8-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[TMP0]], i64 0786// LE-PWR8-NEXT: [[TMP10:%.*]] = extractelement <8 x i16> [[TMP7]], i64 2787// LE-PWR8-NEXT: [[TMP11:%.*]] = call i16 @llvm.bswap.i16(i16 [[TMP10]])788// LE-PWR8-NEXT: store i16 [[TMP11]], ptr [[TMP8]], align 1789// LE-PWR8-NEXT: ret void790//791// BE-PWR9-LABEL: @test_strmb6(792// BE-PWR9-NEXT: entry:793// BE-PWR9-NEXT: [[__A_ADDR_I:%.*]] = alloca <16 x i8>, align 16794// BE-PWR9-NEXT: [[__B_ADDR_I:%.*]] = alloca ptr, align 8795// BE-PWR9-NEXT: [[__C_ADDR_I:%.*]] = alloca i64, align 8796// BE-PWR9-NEXT: [[__MASK_I:%.*]] = alloca <16 x i8>, align 16797// BE-PWR9-NEXT: [[__RES_I:%.*]] = alloca <16 x i8>, align 16798// BE-PWR9-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8799// BE-PWR9-NEXT: [[DATA_ADDR:%.*]] = alloca <16 x i8>, align 16800// BE-PWR9-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 8801// BE-PWR9-NEXT: store <16 x i8> [[DATA:%.*]], ptr [[DATA_ADDR]], align 16802// BE-PWR9-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr [[DATA_ADDR]], align 16803// BE-PWR9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8804// BE-PWR9-NEXT: store <16 x i8> [[TMP0]], ptr [[__A_ADDR_I]], align 16805// BE-PWR9-NEXT: store ptr [[TMP1]], ptr [[__B_ADDR_I]], align 8806// BE-PWR9-NEXT: store i64 6, ptr [[__C_ADDR_I]], align 8807// BE-PWR9-NEXT: [[TMP2:%.*]] = load i64, ptr [[__C_ADDR_I]], align 8808// BE-PWR9-NEXT: [[SUB_I:%.*]] = sub i64 16, [[TMP2]]809// BE-PWR9-NEXT: [[CONV_I:%.*]] = trunc i64 [[SUB_I]] to i8810// BE-PWR9-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr null, i8 [[CONV_I]]811// BE-PWR9-NEXT: [[TMP4:%.*]] = call <16 x i8> @llvm.ppc.altivec.lvsl(ptr [[TMP3]])812// BE-PWR9-NEXT: store <16 x i8> [[TMP4]], ptr [[__MASK_I]], align 16813// BE-PWR9-NEXT: [[TMP5:%.*]] = load <16 x i8>, ptr [[__A_ADDR_I]], align 16814// BE-PWR9-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x i32>815// BE-PWR9-NEXT: [[TMP7:%.*]] = load <16 x i8>, ptr [[__A_ADDR_I]], align 16816// BE-PWR9-NEXT: [[TMP8:%.*]] = bitcast <16 x i8> [[TMP7]] to <4 x i32>817// BE-PWR9-NEXT: [[TMP9:%.*]] = load <16 x i8>, ptr [[__MASK_I]], align 16818// BE-PWR9-NEXT: [[TMP10:%.*]] = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> [[TMP6]], <4 x i32> [[TMP8]], <16 x i8> [[TMP9]])819// BE-PWR9-NEXT: [[TMP11:%.*]] = bitcast <4 x i32> [[TMP10]] to <16 x i8>820// BE-PWR9-NEXT: store <16 x i8> [[TMP11]], ptr [[__RES_I]], align 16821// BE-PWR9-NEXT: [[TMP12:%.*]] = load <16 x i8>, ptr [[__RES_I]], align 16822// BE-PWR9-NEXT: [[TMP13:%.*]] = bitcast <16 x i8> [[TMP12]] to <4 x i32>823// BE-PWR9-NEXT: [[TMP14:%.*]] = load ptr, ptr [[__B_ADDR_I]], align 8824// BE-PWR9-NEXT: [[TMP15:%.*]] = load i64, ptr [[__C_ADDR_I]], align 8825// BE-PWR9-NEXT: [[SHL_I:%.*]] = shl i64 [[TMP15]], 56826// BE-PWR9-NEXT: call void @llvm.ppc.vsx.stxvll(<4 x i32> [[TMP13]], ptr [[TMP14]], i64 [[SHL_I]])827// BE-PWR9-NEXT: ret void828//829// LE-PWR9-LABEL: @test_strmb6(830// LE-PWR9-NEXT: entry:831// LE-PWR9-NEXT: [[__A_ADDR_I:%.*]] = alloca <16 x i8>, align 16832// LE-PWR9-NEXT: [[__B_ADDR_I:%.*]] = alloca ptr, align 8833// LE-PWR9-NEXT: [[__C_ADDR_I:%.*]] = alloca i64, align 8834// LE-PWR9-NEXT: [[__MASK_I:%.*]] = alloca <16 x i8>, align 16835// LE-PWR9-NEXT: [[__RES_I:%.*]] = alloca <16 x i8>, align 16836// LE-PWR9-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8837// LE-PWR9-NEXT: [[DATA_ADDR:%.*]] = alloca <16 x i8>, align 16838// LE-PWR9-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 8839// LE-PWR9-NEXT: store <16 x i8> [[DATA:%.*]], ptr [[DATA_ADDR]], align 16840// LE-PWR9-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr [[DATA_ADDR]], align 16841// LE-PWR9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8842// LE-PWR9-NEXT: store <16 x i8> [[TMP0]], ptr [[__A_ADDR_I]], align 16843// LE-PWR9-NEXT: store ptr [[TMP1]], ptr [[__B_ADDR_I]], align 8844// LE-PWR9-NEXT: store i64 6, ptr [[__C_ADDR_I]], align 8845// LE-PWR9-NEXT: [[TMP2:%.*]] = load i64, ptr [[__C_ADDR_I]], align 8846// LE-PWR9-NEXT: [[SUB_I:%.*]] = sub i64 16, [[TMP2]]847// LE-PWR9-NEXT: [[CONV_I:%.*]] = trunc i64 [[SUB_I]] to i8848// LE-PWR9-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr null, i8 [[CONV_I]]849// LE-PWR9-NEXT: [[TMP4:%.*]] = call <16 x i8> @llvm.ppc.altivec.lvsl(ptr [[TMP3]])850// LE-PWR9-NEXT: store <16 x i8> [[TMP4]], ptr [[__MASK_I]], align 16851// LE-PWR9-NEXT: [[TMP5:%.*]] = load <16 x i8>, ptr [[__A_ADDR_I]], align 16852// LE-PWR9-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x i32>853// LE-PWR9-NEXT: [[TMP7:%.*]] = load <16 x i8>, ptr [[__A_ADDR_I]], align 16854// LE-PWR9-NEXT: [[TMP8:%.*]] = bitcast <16 x i8> [[TMP7]] to <4 x i32>855// LE-PWR9-NEXT: [[TMP9:%.*]] = load <16 x i8>, ptr [[__MASK_I]], align 16856// LE-PWR9-NEXT: [[TMP10:%.*]] = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> [[TMP6]], <4 x i32> [[TMP8]], <16 x i8> [[TMP9]])857// LE-PWR9-NEXT: [[TMP11:%.*]] = bitcast <4 x i32> [[TMP10]] to <16 x i8>858// LE-PWR9-NEXT: store <16 x i8> [[TMP11]], ptr [[__RES_I]], align 16859// LE-PWR9-NEXT: [[TMP12:%.*]] = load <16 x i8>, ptr [[__RES_I]], align 16860// LE-PWR9-NEXT: [[TMP13:%.*]] = bitcast <16 x i8> [[TMP12]] to <4 x i32>861// LE-PWR9-NEXT: [[TMP14:%.*]] = load ptr, ptr [[__B_ADDR_I]], align 8862// LE-PWR9-NEXT: [[TMP15:%.*]] = load i64, ptr [[__C_ADDR_I]], align 8863// LE-PWR9-NEXT: [[SHL_I:%.*]] = shl i64 [[TMP15]], 56864// LE-PWR9-NEXT: call void @llvm.ppc.vsx.stxvll(<4 x i32> [[TMP13]], ptr [[TMP14]], i64 [[SHL_I]])865// LE-PWR9-NEXT: ret void866//867// BE32-PWR9-LABEL: @test_strmb6(868// BE32-PWR9-NEXT: entry:869// BE32-PWR9-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 4870// BE32-PWR9-NEXT: [[DATA_ADDR:%.*]] = alloca <16 x i8>, align 16871// BE32-PWR9-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 4872// BE32-PWR9-NEXT: store <16 x i8> [[DATA:%.*]], ptr [[DATA_ADDR]], align 16873// BE32-PWR9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 4874// BE32-PWR9-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr [[DATA_ADDR]], align 16875// BE32-PWR9-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>876// BE32-PWR9-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr [[TMP0]], i64 2877// BE32-PWR9-NEXT: [[TMP5:%.*]] = extractelement <4 x i32> [[TMP2]], i64 3878// BE32-PWR9-NEXT: store i32 [[TMP5]], ptr [[TMP3]], align 1879// BE32-PWR9-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>880// BE32-PWR9-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr [[TMP0]], i64 0881// BE32-PWR9-NEXT: [[TMP9:%.*]] = extractelement <8 x i16> [[TMP6]], i64 5882// BE32-PWR9-NEXT: store i16 [[TMP9]], ptr [[TMP7]], align 1883// BE32-PWR9-NEXT: ret void884//885void test_strmb6(char *ptr, vector unsigned char data) {886 __vec_strmb(ptr, 6, data);887}888 889// BE-PWR8-LABEL: @test_strmb7(890// BE-PWR8-NEXT: entry:891// BE-PWR8-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8892// BE-PWR8-NEXT: [[DATA_ADDR:%.*]] = alloca <16 x i8>, align 16893// BE-PWR8-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 8894// BE-PWR8-NEXT: store <16 x i8> [[DATA:%.*]], ptr [[DATA_ADDR]], align 16895// BE-PWR8-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8896// BE-PWR8-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr [[DATA_ADDR]], align 16897// BE-PWR8-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>898// BE-PWR8-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr [[TMP0]], i64 3899// BE-PWR8-NEXT: [[TMP5:%.*]] = extractelement <4 x i32> [[TMP2]], i64 3900// BE-PWR8-NEXT: store i32 [[TMP5]], ptr [[TMP3]], align 1901// BE-PWR8-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>902// BE-PWR8-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr [[TMP0]], i64 1903// BE-PWR8-NEXT: [[TMP9:%.*]] = extractelement <8 x i16> [[TMP6]], i64 5904// BE-PWR8-NEXT: store i16 [[TMP9]], ptr [[TMP7]], align 1905// BE-PWR8-NEXT: [[TMP10:%.*]] = getelementptr i8, ptr [[TMP0]], i64 0906// BE-PWR8-NEXT: [[TMP11:%.*]] = extractelement <16 x i8> [[TMP1]], i64 9907// BE-PWR8-NEXT: store i8 [[TMP11]], ptr [[TMP10]], align 1908// BE-PWR8-NEXT: ret void909//910// LE-PWR8-LABEL: @test_strmb7(911// LE-PWR8-NEXT: entry:912// LE-PWR8-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8913// LE-PWR8-NEXT: [[DATA_ADDR:%.*]] = alloca <16 x i8>, align 16914// LE-PWR8-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 8915// LE-PWR8-NEXT: store <16 x i8> [[DATA:%.*]], ptr [[DATA_ADDR]], align 16916// LE-PWR8-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8917// LE-PWR8-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr [[DATA_ADDR]], align 16918// LE-PWR8-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>919// LE-PWR8-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr [[TMP0]], i64 3920// LE-PWR8-NEXT: [[TMP5:%.*]] = extractelement <4 x i32> [[TMP2]], i64 0921// LE-PWR8-NEXT: [[TMP6:%.*]] = call i32 @llvm.bswap.i32(i32 [[TMP5]])922// LE-PWR8-NEXT: store i32 [[TMP6]], ptr [[TMP3]], align 1923// LE-PWR8-NEXT: [[TMP7:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>924// LE-PWR8-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[TMP0]], i64 1925// LE-PWR8-NEXT: [[TMP10:%.*]] = extractelement <8 x i16> [[TMP7]], i64 2926// LE-PWR8-NEXT: [[TMP11:%.*]] = call i16 @llvm.bswap.i16(i16 [[TMP10]])927// LE-PWR8-NEXT: store i16 [[TMP11]], ptr [[TMP8]], align 1928// LE-PWR8-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[TMP0]], i64 0929// LE-PWR8-NEXT: [[TMP13:%.*]] = extractelement <16 x i8> [[TMP1]], i64 6930// LE-PWR8-NEXT: store i8 [[TMP13]], ptr [[TMP12]], align 1931// LE-PWR8-NEXT: ret void932//933// BE-PWR9-LABEL: @test_strmb7(934// BE-PWR9-NEXT: entry:935// BE-PWR9-NEXT: [[__A_ADDR_I:%.*]] = alloca <16 x i8>, align 16936// BE-PWR9-NEXT: [[__B_ADDR_I:%.*]] = alloca ptr, align 8937// BE-PWR9-NEXT: [[__C_ADDR_I:%.*]] = alloca i64, align 8938// BE-PWR9-NEXT: [[__MASK_I:%.*]] = alloca <16 x i8>, align 16939// BE-PWR9-NEXT: [[__RES_I:%.*]] = alloca <16 x i8>, align 16940// BE-PWR9-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8941// BE-PWR9-NEXT: [[DATA_ADDR:%.*]] = alloca <16 x i8>, align 16942// BE-PWR9-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 8943// BE-PWR9-NEXT: store <16 x i8> [[DATA:%.*]], ptr [[DATA_ADDR]], align 16944// BE-PWR9-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr [[DATA_ADDR]], align 16945// BE-PWR9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8946// BE-PWR9-NEXT: store <16 x i8> [[TMP0]], ptr [[__A_ADDR_I]], align 16947// BE-PWR9-NEXT: store ptr [[TMP1]], ptr [[__B_ADDR_I]], align 8948// BE-PWR9-NEXT: store i64 7, ptr [[__C_ADDR_I]], align 8949// BE-PWR9-NEXT: [[TMP2:%.*]] = load i64, ptr [[__C_ADDR_I]], align 8950// BE-PWR9-NEXT: [[SUB_I:%.*]] = sub i64 16, [[TMP2]]951// BE-PWR9-NEXT: [[CONV_I:%.*]] = trunc i64 [[SUB_I]] to i8952// BE-PWR9-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr null, i8 [[CONV_I]]953// BE-PWR9-NEXT: [[TMP4:%.*]] = call <16 x i8> @llvm.ppc.altivec.lvsl(ptr [[TMP3]])954// BE-PWR9-NEXT: store <16 x i8> [[TMP4]], ptr [[__MASK_I]], align 16955// BE-PWR9-NEXT: [[TMP5:%.*]] = load <16 x i8>, ptr [[__A_ADDR_I]], align 16956// BE-PWR9-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x i32>957// BE-PWR9-NEXT: [[TMP7:%.*]] = load <16 x i8>, ptr [[__A_ADDR_I]], align 16958// BE-PWR9-NEXT: [[TMP8:%.*]] = bitcast <16 x i8> [[TMP7]] to <4 x i32>959// BE-PWR9-NEXT: [[TMP9:%.*]] = load <16 x i8>, ptr [[__MASK_I]], align 16960// BE-PWR9-NEXT: [[TMP10:%.*]] = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> [[TMP6]], <4 x i32> [[TMP8]], <16 x i8> [[TMP9]])961// BE-PWR9-NEXT: [[TMP11:%.*]] = bitcast <4 x i32> [[TMP10]] to <16 x i8>962// BE-PWR9-NEXT: store <16 x i8> [[TMP11]], ptr [[__RES_I]], align 16963// BE-PWR9-NEXT: [[TMP12:%.*]] = load <16 x i8>, ptr [[__RES_I]], align 16964// BE-PWR9-NEXT: [[TMP13:%.*]] = bitcast <16 x i8> [[TMP12]] to <4 x i32>965// BE-PWR9-NEXT: [[TMP14:%.*]] = load ptr, ptr [[__B_ADDR_I]], align 8966// BE-PWR9-NEXT: [[TMP15:%.*]] = load i64, ptr [[__C_ADDR_I]], align 8967// BE-PWR9-NEXT: [[SHL_I:%.*]] = shl i64 [[TMP15]], 56968// BE-PWR9-NEXT: call void @llvm.ppc.vsx.stxvll(<4 x i32> [[TMP13]], ptr [[TMP14]], i64 [[SHL_I]])969// BE-PWR9-NEXT: ret void970//971// LE-PWR9-LABEL: @test_strmb7(972// LE-PWR9-NEXT: entry:973// LE-PWR9-NEXT: [[__A_ADDR_I:%.*]] = alloca <16 x i8>, align 16974// LE-PWR9-NEXT: [[__B_ADDR_I:%.*]] = alloca ptr, align 8975// LE-PWR9-NEXT: [[__C_ADDR_I:%.*]] = alloca i64, align 8976// LE-PWR9-NEXT: [[__MASK_I:%.*]] = alloca <16 x i8>, align 16977// LE-PWR9-NEXT: [[__RES_I:%.*]] = alloca <16 x i8>, align 16978// LE-PWR9-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8979// LE-PWR9-NEXT: [[DATA_ADDR:%.*]] = alloca <16 x i8>, align 16980// LE-PWR9-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 8981// LE-PWR9-NEXT: store <16 x i8> [[DATA:%.*]], ptr [[DATA_ADDR]], align 16982// LE-PWR9-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr [[DATA_ADDR]], align 16983// LE-PWR9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8984// LE-PWR9-NEXT: store <16 x i8> [[TMP0]], ptr [[__A_ADDR_I]], align 16985// LE-PWR9-NEXT: store ptr [[TMP1]], ptr [[__B_ADDR_I]], align 8986// LE-PWR9-NEXT: store i64 7, ptr [[__C_ADDR_I]], align 8987// LE-PWR9-NEXT: [[TMP2:%.*]] = load i64, ptr [[__C_ADDR_I]], align 8988// LE-PWR9-NEXT: [[SUB_I:%.*]] = sub i64 16, [[TMP2]]989// LE-PWR9-NEXT: [[CONV_I:%.*]] = trunc i64 [[SUB_I]] to i8990// LE-PWR9-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr null, i8 [[CONV_I]]991// LE-PWR9-NEXT: [[TMP4:%.*]] = call <16 x i8> @llvm.ppc.altivec.lvsl(ptr [[TMP3]])992// LE-PWR9-NEXT: store <16 x i8> [[TMP4]], ptr [[__MASK_I]], align 16993// LE-PWR9-NEXT: [[TMP5:%.*]] = load <16 x i8>, ptr [[__A_ADDR_I]], align 16994// LE-PWR9-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x i32>995// LE-PWR9-NEXT: [[TMP7:%.*]] = load <16 x i8>, ptr [[__A_ADDR_I]], align 16996// LE-PWR9-NEXT: [[TMP8:%.*]] = bitcast <16 x i8> [[TMP7]] to <4 x i32>997// LE-PWR9-NEXT: [[TMP9:%.*]] = load <16 x i8>, ptr [[__MASK_I]], align 16998// LE-PWR9-NEXT: [[TMP10:%.*]] = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> [[TMP6]], <4 x i32> [[TMP8]], <16 x i8> [[TMP9]])999// LE-PWR9-NEXT: [[TMP11:%.*]] = bitcast <4 x i32> [[TMP10]] to <16 x i8>1000// LE-PWR9-NEXT: store <16 x i8> [[TMP11]], ptr [[__RES_I]], align 161001// LE-PWR9-NEXT: [[TMP12:%.*]] = load <16 x i8>, ptr [[__RES_I]], align 161002// LE-PWR9-NEXT: [[TMP13:%.*]] = bitcast <16 x i8> [[TMP12]] to <4 x i32>1003// LE-PWR9-NEXT: [[TMP14:%.*]] = load ptr, ptr [[__B_ADDR_I]], align 81004// LE-PWR9-NEXT: [[TMP15:%.*]] = load i64, ptr [[__C_ADDR_I]], align 81005// LE-PWR9-NEXT: [[SHL_I:%.*]] = shl i64 [[TMP15]], 561006// LE-PWR9-NEXT: call void @llvm.ppc.vsx.stxvll(<4 x i32> [[TMP13]], ptr [[TMP14]], i64 [[SHL_I]])1007// LE-PWR9-NEXT: ret void1008//1009// BE32-PWR9-LABEL: @test_strmb7(1010// BE32-PWR9-NEXT: entry:1011// BE32-PWR9-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 41012// BE32-PWR9-NEXT: [[DATA_ADDR:%.*]] = alloca <16 x i8>, align 161013// BE32-PWR9-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 41014// BE32-PWR9-NEXT: store <16 x i8> [[DATA:%.*]], ptr [[DATA_ADDR]], align 161015// BE32-PWR9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 41016// BE32-PWR9-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr [[DATA_ADDR]], align 161017// BE32-PWR9-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>1018// BE32-PWR9-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr [[TMP0]], i64 31019// BE32-PWR9-NEXT: [[TMP5:%.*]] = extractelement <4 x i32> [[TMP2]], i64 31020// BE32-PWR9-NEXT: store i32 [[TMP5]], ptr [[TMP3]], align 11021// BE32-PWR9-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>1022// BE32-PWR9-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr [[TMP0]], i64 11023// BE32-PWR9-NEXT: [[TMP9:%.*]] = extractelement <8 x i16> [[TMP6]], i64 51024// BE32-PWR9-NEXT: store i16 [[TMP9]], ptr [[TMP7]], align 11025// BE32-PWR9-NEXT: [[TMP10:%.*]] = getelementptr i8, ptr [[TMP0]], i64 01026// BE32-PWR9-NEXT: [[TMP11:%.*]] = extractelement <16 x i8> [[TMP1]], i64 91027// BE32-PWR9-NEXT: store i8 [[TMP11]], ptr [[TMP10]], align 11028// BE32-PWR9-NEXT: ret void1029//1030void test_strmb7(char *ptr, vector unsigned char data) {1031 __vec_strmb(ptr, 7, data);1032}1033 1034// BE-PWR8-LABEL: @test_strmb8(1035// BE-PWR8-NEXT: entry:1036// BE-PWR8-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 81037// BE-PWR8-NEXT: [[DATA_ADDR:%.*]] = alloca <16 x i8>, align 161038// BE-PWR8-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 81039// BE-PWR8-NEXT: store <16 x i8> [[DATA:%.*]], ptr [[DATA_ADDR]], align 161040// BE-PWR8-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 81041// BE-PWR8-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr [[DATA_ADDR]], align 161042// BE-PWR8-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>1043// BE-PWR8-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr [[TMP0]], i64 01044// BE-PWR8-NEXT: [[TMP5:%.*]] = extractelement <2 x i64> [[TMP2]], i64 11045// BE-PWR8-NEXT: store i64 [[TMP5]], ptr [[TMP3]], align 11046// BE-PWR8-NEXT: ret void1047//1048// LE-PWR8-LABEL: @test_strmb8(1049// LE-PWR8-NEXT: entry:1050// LE-PWR8-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 81051// LE-PWR8-NEXT: [[DATA_ADDR:%.*]] = alloca <16 x i8>, align 161052// LE-PWR8-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 81053// LE-PWR8-NEXT: store <16 x i8> [[DATA:%.*]], ptr [[DATA_ADDR]], align 161054// LE-PWR8-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 81055// LE-PWR8-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr [[DATA_ADDR]], align 161056// LE-PWR8-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>1057// LE-PWR8-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr [[TMP0]], i64 01058// LE-PWR8-NEXT: [[TMP5:%.*]] = extractelement <2 x i64> [[TMP2]], i64 01059// LE-PWR8-NEXT: [[TMP6:%.*]] = call i64 @llvm.bswap.i64(i64 [[TMP5]])1060// LE-PWR8-NEXT: store i64 [[TMP6]], ptr [[TMP3]], align 11061// LE-PWR8-NEXT: ret void1062//1063// BE-PWR9-LABEL: @test_strmb8(1064// BE-PWR9-NEXT: entry:1065// BE-PWR9-NEXT: [[__A_ADDR_I:%.*]] = alloca <16 x i8>, align 161066// BE-PWR9-NEXT: [[__B_ADDR_I:%.*]] = alloca ptr, align 81067// BE-PWR9-NEXT: [[__C_ADDR_I:%.*]] = alloca i64, align 81068// BE-PWR9-NEXT: [[__MASK_I:%.*]] = alloca <16 x i8>, align 161069// BE-PWR9-NEXT: [[__RES_I:%.*]] = alloca <16 x i8>, align 161070// BE-PWR9-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 81071// BE-PWR9-NEXT: [[DATA_ADDR:%.*]] = alloca <16 x i8>, align 161072// BE-PWR9-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 81073// BE-PWR9-NEXT: store <16 x i8> [[DATA:%.*]], ptr [[DATA_ADDR]], align 161074// BE-PWR9-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr [[DATA_ADDR]], align 161075// BE-PWR9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[PTR_ADDR]], align 81076// BE-PWR9-NEXT: store <16 x i8> [[TMP0]], ptr [[__A_ADDR_I]], align 161077// BE-PWR9-NEXT: store ptr [[TMP1]], ptr [[__B_ADDR_I]], align 81078// BE-PWR9-NEXT: store i64 8, ptr [[__C_ADDR_I]], align 81079// BE-PWR9-NEXT: [[TMP2:%.*]] = load i64, ptr [[__C_ADDR_I]], align 81080// BE-PWR9-NEXT: [[SUB_I:%.*]] = sub i64 16, [[TMP2]]1081// BE-PWR9-NEXT: [[CONV_I:%.*]] = trunc i64 [[SUB_I]] to i81082// BE-PWR9-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr null, i8 [[CONV_I]]1083// BE-PWR9-NEXT: [[TMP4:%.*]] = call <16 x i8> @llvm.ppc.altivec.lvsl(ptr [[TMP3]])1084// BE-PWR9-NEXT: store <16 x i8> [[TMP4]], ptr [[__MASK_I]], align 161085// BE-PWR9-NEXT: [[TMP5:%.*]] = load <16 x i8>, ptr [[__A_ADDR_I]], align 161086// BE-PWR9-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x i32>1087// BE-PWR9-NEXT: [[TMP7:%.*]] = load <16 x i8>, ptr [[__A_ADDR_I]], align 161088// BE-PWR9-NEXT: [[TMP8:%.*]] = bitcast <16 x i8> [[TMP7]] to <4 x i32>1089// BE-PWR9-NEXT: [[TMP9:%.*]] = load <16 x i8>, ptr [[__MASK_I]], align 161090// BE-PWR9-NEXT: [[TMP10:%.*]] = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> [[TMP6]], <4 x i32> [[TMP8]], <16 x i8> [[TMP9]])1091// BE-PWR9-NEXT: [[TMP11:%.*]] = bitcast <4 x i32> [[TMP10]] to <16 x i8>1092// BE-PWR9-NEXT: store <16 x i8> [[TMP11]], ptr [[__RES_I]], align 161093// BE-PWR9-NEXT: [[TMP12:%.*]] = load <16 x i8>, ptr [[__RES_I]], align 161094// BE-PWR9-NEXT: [[TMP13:%.*]] = bitcast <16 x i8> [[TMP12]] to <4 x i32>1095// BE-PWR9-NEXT: [[TMP14:%.*]] = load ptr, ptr [[__B_ADDR_I]], align 81096// BE-PWR9-NEXT: [[TMP15:%.*]] = load i64, ptr [[__C_ADDR_I]], align 81097// BE-PWR9-NEXT: [[SHL_I:%.*]] = shl i64 [[TMP15]], 561098// BE-PWR9-NEXT: call void @llvm.ppc.vsx.stxvll(<4 x i32> [[TMP13]], ptr [[TMP14]], i64 [[SHL_I]])1099// BE-PWR9-NEXT: ret void1100//1101// LE-PWR9-LABEL: @test_strmb8(1102// LE-PWR9-NEXT: entry:1103// LE-PWR9-NEXT: [[__A_ADDR_I:%.*]] = alloca <16 x i8>, align 161104// LE-PWR9-NEXT: [[__B_ADDR_I:%.*]] = alloca ptr, align 81105// LE-PWR9-NEXT: [[__C_ADDR_I:%.*]] = alloca i64, align 81106// LE-PWR9-NEXT: [[__MASK_I:%.*]] = alloca <16 x i8>, align 161107// LE-PWR9-NEXT: [[__RES_I:%.*]] = alloca <16 x i8>, align 161108// LE-PWR9-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 81109// LE-PWR9-NEXT: [[DATA_ADDR:%.*]] = alloca <16 x i8>, align 161110// LE-PWR9-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 81111// LE-PWR9-NEXT: store <16 x i8> [[DATA:%.*]], ptr [[DATA_ADDR]], align 161112// LE-PWR9-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr [[DATA_ADDR]], align 161113// LE-PWR9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[PTR_ADDR]], align 81114// LE-PWR9-NEXT: store <16 x i8> [[TMP0]], ptr [[__A_ADDR_I]], align 161115// LE-PWR9-NEXT: store ptr [[TMP1]], ptr [[__B_ADDR_I]], align 81116// LE-PWR9-NEXT: store i64 8, ptr [[__C_ADDR_I]], align 81117// LE-PWR9-NEXT: [[TMP2:%.*]] = load i64, ptr [[__C_ADDR_I]], align 81118// LE-PWR9-NEXT: [[SUB_I:%.*]] = sub i64 16, [[TMP2]]1119// LE-PWR9-NEXT: [[CONV_I:%.*]] = trunc i64 [[SUB_I]] to i81120// LE-PWR9-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr null, i8 [[CONV_I]]1121// LE-PWR9-NEXT: [[TMP4:%.*]] = call <16 x i8> @llvm.ppc.altivec.lvsl(ptr [[TMP3]])1122// LE-PWR9-NEXT: store <16 x i8> [[TMP4]], ptr [[__MASK_I]], align 161123// LE-PWR9-NEXT: [[TMP5:%.*]] = load <16 x i8>, ptr [[__A_ADDR_I]], align 161124// LE-PWR9-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x i32>1125// LE-PWR9-NEXT: [[TMP7:%.*]] = load <16 x i8>, ptr [[__A_ADDR_I]], align 161126// LE-PWR9-NEXT: [[TMP8:%.*]] = bitcast <16 x i8> [[TMP7]] to <4 x i32>1127// LE-PWR9-NEXT: [[TMP9:%.*]] = load <16 x i8>, ptr [[__MASK_I]], align 161128// LE-PWR9-NEXT: [[TMP10:%.*]] = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> [[TMP6]], <4 x i32> [[TMP8]], <16 x i8> [[TMP9]])1129// LE-PWR9-NEXT: [[TMP11:%.*]] = bitcast <4 x i32> [[TMP10]] to <16 x i8>1130// LE-PWR9-NEXT: store <16 x i8> [[TMP11]], ptr [[__RES_I]], align 161131// LE-PWR9-NEXT: [[TMP12:%.*]] = load <16 x i8>, ptr [[__RES_I]], align 161132// LE-PWR9-NEXT: [[TMP13:%.*]] = bitcast <16 x i8> [[TMP12]] to <4 x i32>1133// LE-PWR9-NEXT: [[TMP14:%.*]] = load ptr, ptr [[__B_ADDR_I]], align 81134// LE-PWR9-NEXT: [[TMP15:%.*]] = load i64, ptr [[__C_ADDR_I]], align 81135// LE-PWR9-NEXT: [[SHL_I:%.*]] = shl i64 [[TMP15]], 561136// LE-PWR9-NEXT: call void @llvm.ppc.vsx.stxvll(<4 x i32> [[TMP13]], ptr [[TMP14]], i64 [[SHL_I]])1137// LE-PWR9-NEXT: ret void1138//1139// BE32-PWR9-LABEL: @test_strmb8(1140// BE32-PWR9-NEXT: entry:1141// BE32-PWR9-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 41142// BE32-PWR9-NEXT: [[DATA_ADDR:%.*]] = alloca <16 x i8>, align 161143// BE32-PWR9-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 41144// BE32-PWR9-NEXT: store <16 x i8> [[DATA:%.*]], ptr [[DATA_ADDR]], align 161145// BE32-PWR9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 41146// BE32-PWR9-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr [[DATA_ADDR]], align 161147// BE32-PWR9-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>1148// BE32-PWR9-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr [[TMP0]], i64 01149// BE32-PWR9-NEXT: [[TMP5:%.*]] = extractelement <2 x i64> [[TMP2]], i64 11150// BE32-PWR9-NEXT: store i64 [[TMP5]], ptr [[TMP3]], align 11151// BE32-PWR9-NEXT: ret void1152//1153void test_strmb8(char *ptr, vector unsigned char data) {1154 __vec_strmb(ptr, 8, data);1155}1156// BE-PWR8-LABEL: @test_ldrmb9(1157// BE-PWR8-NEXT: entry:1158// BE-PWR8-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 81159// BE-PWR8-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 81160// BE-PWR8-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 81161// BE-PWR8-NEXT: [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 81162// BE-PWR8-NEXT: [[LD_LO:%.*]] = call <4 x i32> @llvm.ppc.altivec.lvx(ptr [[TMP0]])1163// BE-PWR8-NEXT: [[LD_HI:%.*]] = call <4 x i32> @llvm.ppc.altivec.lvx(ptr [[TMP1]])1164// BE-PWR8-NEXT: [[MASK1:%.*]] = call <16 x i8> @llvm.ppc.altivec.lvsl(ptr [[TMP0]])1165// BE-PWR8-NEXT: [[SHUFFLE1:%.*]] = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> [[LD_LO]], <4 x i32> [[LD_HI]], <16 x i8> [[MASK1]])1166// BE-PWR8-NEXT: [[SHUFFLE2:%.*]] = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> zeroinitializer, <4 x i32> [[SHUFFLE1]], <16 x i8> <i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24>)1167// BE-PWR8-NEXT: [[TMP2:%.*]] = bitcast <4 x i32> [[SHUFFLE2]] to <16 x i8>1168// BE-PWR8-NEXT: ret <16 x i8> [[TMP2]]1169//1170// LE-PWR8-LABEL: @test_ldrmb9(1171// LE-PWR8-NEXT: entry:1172// LE-PWR8-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 81173// LE-PWR8-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 81174// LE-PWR8-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 81175// LE-PWR8-NEXT: [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 81176// LE-PWR8-NEXT: [[LD_LO:%.*]] = call <4 x i32> @llvm.ppc.altivec.lvx(ptr [[TMP0]])1177// LE-PWR8-NEXT: [[LD_HI:%.*]] = call <4 x i32> @llvm.ppc.altivec.lvx(ptr [[TMP1]])1178// LE-PWR8-NEXT: [[MASK1:%.*]] = call <16 x i8> @llvm.ppc.altivec.lvsr(ptr [[TMP0]])1179// LE-PWR8-NEXT: [[SHUFFLE1:%.*]] = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> [[LD_HI]], <4 x i32> [[LD_LO]], <16 x i8> [[MASK1]])1180// LE-PWR8-NEXT: [[TMP2:%.*]] = bitcast <4 x i32> [[SHUFFLE1]] to <16 x i8>1181// LE-PWR8-NEXT: [[TMP3:%.*]] = shufflevector <16 x i8> [[TMP2]], <16 x i8> zeroinitializer, <16 x i32> <i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22>1182// LE-PWR8-NEXT: ret <16 x i8> [[TMP3]]1183//1184// BE-PWR9-LABEL: @test_ldrmb9(1185// BE-PWR9-NEXT: entry:1186// BE-PWR9-NEXT: [[__A_ADDR_I:%.*]] = alloca ptr, align 81187// BE-PWR9-NEXT: [[__B_ADDR_I:%.*]] = alloca i64, align 81188// BE-PWR9-NEXT: [[__RES_I:%.*]] = alloca <16 x i8>, align 161189// BE-PWR9-NEXT: [[__MASK_I:%.*]] = alloca <16 x i8>, align 161190// BE-PWR9-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 81191// BE-PWR9-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 81192// BE-PWR9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 81193// BE-PWR9-NEXT: store ptr [[TMP0]], ptr [[__A_ADDR_I]], align 81194// BE-PWR9-NEXT: store i64 9, ptr [[__B_ADDR_I]], align 81195// BE-PWR9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__A_ADDR_I]], align 81196// BE-PWR9-NEXT: [[TMP2:%.*]] = load i64, ptr [[__B_ADDR_I]], align 81197// BE-PWR9-NEXT: [[SHL_I:%.*]] = shl i64 [[TMP2]], 561198// BE-PWR9-NEXT: [[TMP3:%.*]] = call <4 x i32> @llvm.ppc.vsx.lxvll(ptr [[TMP1]], i64 [[SHL_I]])1199// BE-PWR9-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP3]] to <16 x i8>1200// BE-PWR9-NEXT: store <16 x i8> [[TMP4]], ptr [[__RES_I]], align 161201// BE-PWR9-NEXT: [[TMP5:%.*]] = load i64, ptr [[__B_ADDR_I]], align 81202// BE-PWR9-NEXT: [[SUB_I:%.*]] = sub i64 16, [[TMP5]]1203// BE-PWR9-NEXT: [[CONV_I:%.*]] = trunc i64 [[SUB_I]] to i81204// BE-PWR9-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr null, i8 [[CONV_I]]1205// BE-PWR9-NEXT: [[TMP7:%.*]] = call <16 x i8> @llvm.ppc.altivec.lvsr(ptr [[TMP6]])1206// BE-PWR9-NEXT: store <16 x i8> [[TMP7]], ptr [[__MASK_I]], align 161207// BE-PWR9-NEXT: [[TMP8:%.*]] = load <16 x i8>, ptr [[__RES_I]], align 161208// BE-PWR9-NEXT: [[TMP9:%.*]] = bitcast <16 x i8> [[TMP8]] to <4 x i32>1209// BE-PWR9-NEXT: [[TMP10:%.*]] = load <16 x i8>, ptr [[__RES_I]], align 161210// BE-PWR9-NEXT: [[TMP11:%.*]] = bitcast <16 x i8> [[TMP10]] to <4 x i32>1211// BE-PWR9-NEXT: [[TMP12:%.*]] = load <16 x i8>, ptr [[__MASK_I]], align 161212// BE-PWR9-NEXT: [[TMP13:%.*]] = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> [[TMP9]], <4 x i32> [[TMP11]], <16 x i8> [[TMP12]])1213// BE-PWR9-NEXT: [[TMP14:%.*]] = bitcast <4 x i32> [[TMP13]] to <16 x i8>1214// BE-PWR9-NEXT: ret <16 x i8> [[TMP14]]1215//1216// LE-PWR9-LABEL: @test_ldrmb9(1217// LE-PWR9-NEXT: entry:1218// LE-PWR9-NEXT: [[__A_ADDR_I:%.*]] = alloca ptr, align 81219// LE-PWR9-NEXT: [[__B_ADDR_I:%.*]] = alloca i64, align 81220// LE-PWR9-NEXT: [[__RES_I:%.*]] = alloca <16 x i8>, align 161221// LE-PWR9-NEXT: [[__MASK_I:%.*]] = alloca <16 x i8>, align 161222// LE-PWR9-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 81223// LE-PWR9-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 81224// LE-PWR9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 81225// LE-PWR9-NEXT: store ptr [[TMP0]], ptr [[__A_ADDR_I]], align 81226// LE-PWR9-NEXT: store i64 9, ptr [[__B_ADDR_I]], align 81227// LE-PWR9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__A_ADDR_I]], align 81228// LE-PWR9-NEXT: [[TMP2:%.*]] = load i64, ptr [[__B_ADDR_I]], align 81229// LE-PWR9-NEXT: [[SHL_I:%.*]] = shl i64 [[TMP2]], 561230// LE-PWR9-NEXT: [[TMP3:%.*]] = call <4 x i32> @llvm.ppc.vsx.lxvll(ptr [[TMP1]], i64 [[SHL_I]])1231// LE-PWR9-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP3]] to <16 x i8>1232// LE-PWR9-NEXT: store <16 x i8> [[TMP4]], ptr [[__RES_I]], align 161233// LE-PWR9-NEXT: [[TMP5:%.*]] = load i64, ptr [[__B_ADDR_I]], align 81234// LE-PWR9-NEXT: [[SUB_I:%.*]] = sub i64 16, [[TMP5]]1235// LE-PWR9-NEXT: [[CONV_I:%.*]] = trunc i64 [[SUB_I]] to i81236// LE-PWR9-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr null, i8 [[CONV_I]]1237// LE-PWR9-NEXT: [[TMP7:%.*]] = call <16 x i8> @llvm.ppc.altivec.lvsr(ptr [[TMP6]])1238// LE-PWR9-NEXT: store <16 x i8> [[TMP7]], ptr [[__MASK_I]], align 161239// LE-PWR9-NEXT: [[TMP8:%.*]] = load <16 x i8>, ptr [[__RES_I]], align 161240// LE-PWR9-NEXT: [[TMP9:%.*]] = bitcast <16 x i8> [[TMP8]] to <4 x i32>1241// LE-PWR9-NEXT: [[TMP10:%.*]] = load <16 x i8>, ptr [[__RES_I]], align 161242// LE-PWR9-NEXT: [[TMP11:%.*]] = bitcast <16 x i8> [[TMP10]] to <4 x i32>1243// LE-PWR9-NEXT: [[TMP12:%.*]] = load <16 x i8>, ptr [[__MASK_I]], align 161244// LE-PWR9-NEXT: [[TMP13:%.*]] = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> [[TMP9]], <4 x i32> [[TMP11]], <16 x i8> [[TMP12]])1245// LE-PWR9-NEXT: [[TMP14:%.*]] = bitcast <4 x i32> [[TMP13]] to <16 x i8>1246// LE-PWR9-NEXT: ret <16 x i8> [[TMP14]]1247//1248// BE32-PWR9-LABEL: @test_ldrmb9(1249// BE32-PWR9-NEXT: entry:1250// BE32-PWR9-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 41251// BE32-PWR9-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 41252// BE32-PWR9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 41253// BE32-PWR9-NEXT: [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 81254// BE32-PWR9-NEXT: [[LD_LO:%.*]] = call <4 x i32> @llvm.ppc.altivec.lvx(ptr [[TMP0]])1255// BE32-PWR9-NEXT: [[LD_HI:%.*]] = call <4 x i32> @llvm.ppc.altivec.lvx(ptr [[TMP1]])1256// BE32-PWR9-NEXT: [[MASK1:%.*]] = call <16 x i8> @llvm.ppc.altivec.lvsl(ptr [[TMP0]])1257// BE32-PWR9-NEXT: [[SHUFFLE1:%.*]] = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> [[LD_LO]], <4 x i32> [[LD_HI]], <16 x i8> [[MASK1]])1258// BE32-PWR9-NEXT: [[SHUFFLE2:%.*]] = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> zeroinitializer, <4 x i32> [[SHUFFLE1]], <16 x i8> <i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24>)1259// BE32-PWR9-NEXT: [[TMP2:%.*]] = bitcast <4 x i32> [[SHUFFLE2]] to <16 x i8>1260// BE32-PWR9-NEXT: ret <16 x i8> [[TMP2]]1261//1262vector unsigned char test_ldrmb9(char *ptr) { return __vec_ldrmb(ptr, 9); }1263 1264// BE-PWR8-LABEL: @test_strmb9(1265// BE-PWR8-NEXT: entry:1266// BE-PWR8-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 81267// BE-PWR8-NEXT: [[DATA_ADDR:%.*]] = alloca <16 x i8>, align 161268// BE-PWR8-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 81269// BE-PWR8-NEXT: store <16 x i8> [[DATA:%.*]], ptr [[DATA_ADDR]], align 161270// BE-PWR8-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 81271// BE-PWR8-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr [[DATA_ADDR]], align 161272// BE-PWR8-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>1273// BE-PWR8-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr [[TMP0]], i64 11274// BE-PWR8-NEXT: [[TMP5:%.*]] = extractelement <2 x i64> [[TMP2]], i64 11275// BE-PWR8-NEXT: store i64 [[TMP5]], ptr [[TMP3]], align 11276// BE-PWR8-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr [[TMP0]], i64 01277// BE-PWR8-NEXT: [[TMP7:%.*]] = extractelement <16 x i8> [[TMP1]], i64 71278// BE-PWR8-NEXT: store i8 [[TMP7]], ptr [[TMP6]], align 11279// BE-PWR8-NEXT: ret void1280//1281// LE-PWR8-LABEL: @test_strmb9(1282// LE-PWR8-NEXT: entry:1283// LE-PWR8-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 81284// LE-PWR8-NEXT: [[DATA_ADDR:%.*]] = alloca <16 x i8>, align 161285// LE-PWR8-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 81286// LE-PWR8-NEXT: store <16 x i8> [[DATA:%.*]], ptr [[DATA_ADDR]], align 161287// LE-PWR8-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 81288// LE-PWR8-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr [[DATA_ADDR]], align 161289// LE-PWR8-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>1290// LE-PWR8-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr [[TMP0]], i64 11291// LE-PWR8-NEXT: [[TMP5:%.*]] = extractelement <2 x i64> [[TMP2]], i64 01292// LE-PWR8-NEXT: [[TMP6:%.*]] = call i64 @llvm.bswap.i64(i64 [[TMP5]])1293// LE-PWR8-NEXT: store i64 [[TMP6]], ptr [[TMP3]], align 11294// LE-PWR8-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr [[TMP0]], i64 01295// LE-PWR8-NEXT: [[TMP8:%.*]] = extractelement <16 x i8> [[TMP1]], i64 81296// LE-PWR8-NEXT: store i8 [[TMP8]], ptr [[TMP7]], align 11297// LE-PWR8-NEXT: ret void1298//1299// BE-PWR9-LABEL: @test_strmb9(1300// BE-PWR9-NEXT: entry:1301// BE-PWR9-NEXT: [[__A_ADDR_I:%.*]] = alloca <16 x i8>, align 161302// BE-PWR9-NEXT: [[__B_ADDR_I:%.*]] = alloca ptr, align 81303// BE-PWR9-NEXT: [[__C_ADDR_I:%.*]] = alloca i64, align 81304// BE-PWR9-NEXT: [[__MASK_I:%.*]] = alloca <16 x i8>, align 161305// BE-PWR9-NEXT: [[__RES_I:%.*]] = alloca <16 x i8>, align 161306// BE-PWR9-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 81307// BE-PWR9-NEXT: [[DATA_ADDR:%.*]] = alloca <16 x i8>, align 161308// BE-PWR9-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 81309// BE-PWR9-NEXT: store <16 x i8> [[DATA:%.*]], ptr [[DATA_ADDR]], align 161310// BE-PWR9-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr [[DATA_ADDR]], align 161311// BE-PWR9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[PTR_ADDR]], align 81312// BE-PWR9-NEXT: store <16 x i8> [[TMP0]], ptr [[__A_ADDR_I]], align 161313// BE-PWR9-NEXT: store ptr [[TMP1]], ptr [[__B_ADDR_I]], align 81314// BE-PWR9-NEXT: store i64 9, ptr [[__C_ADDR_I]], align 81315// BE-PWR9-NEXT: [[TMP2:%.*]] = load i64, ptr [[__C_ADDR_I]], align 81316// BE-PWR9-NEXT: [[SUB_I:%.*]] = sub i64 16, [[TMP2]]1317// BE-PWR9-NEXT: [[CONV_I:%.*]] = trunc i64 [[SUB_I]] to i81318// BE-PWR9-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr null, i8 [[CONV_I]]1319// BE-PWR9-NEXT: [[TMP4:%.*]] = call <16 x i8> @llvm.ppc.altivec.lvsl(ptr [[TMP3]])1320// BE-PWR9-NEXT: store <16 x i8> [[TMP4]], ptr [[__MASK_I]], align 161321// BE-PWR9-NEXT: [[TMP5:%.*]] = load <16 x i8>, ptr [[__A_ADDR_I]], align 161322// BE-PWR9-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x i32>1323// BE-PWR9-NEXT: [[TMP7:%.*]] = load <16 x i8>, ptr [[__A_ADDR_I]], align 161324// BE-PWR9-NEXT: [[TMP8:%.*]] = bitcast <16 x i8> [[TMP7]] to <4 x i32>1325// BE-PWR9-NEXT: [[TMP9:%.*]] = load <16 x i8>, ptr [[__MASK_I]], align 161326// BE-PWR9-NEXT: [[TMP10:%.*]] = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> [[TMP6]], <4 x i32> [[TMP8]], <16 x i8> [[TMP9]])1327// BE-PWR9-NEXT: [[TMP11:%.*]] = bitcast <4 x i32> [[TMP10]] to <16 x i8>1328// BE-PWR9-NEXT: store <16 x i8> [[TMP11]], ptr [[__RES_I]], align 161329// BE-PWR9-NEXT: [[TMP12:%.*]] = load <16 x i8>, ptr [[__RES_I]], align 161330// BE-PWR9-NEXT: [[TMP13:%.*]] = bitcast <16 x i8> [[TMP12]] to <4 x i32>1331// BE-PWR9-NEXT: [[TMP14:%.*]] = load ptr, ptr [[__B_ADDR_I]], align 81332// BE-PWR9-NEXT: [[TMP15:%.*]] = load i64, ptr [[__C_ADDR_I]], align 81333// BE-PWR9-NEXT: [[SHL_I:%.*]] = shl i64 [[TMP15]], 561334// BE-PWR9-NEXT: call void @llvm.ppc.vsx.stxvll(<4 x i32> [[TMP13]], ptr [[TMP14]], i64 [[SHL_I]])1335// BE-PWR9-NEXT: ret void1336//1337// LE-PWR9-LABEL: @test_strmb9(1338// LE-PWR9-NEXT: entry:1339// LE-PWR9-NEXT: [[__A_ADDR_I:%.*]] = alloca <16 x i8>, align 161340// LE-PWR9-NEXT: [[__B_ADDR_I:%.*]] = alloca ptr, align 81341// LE-PWR9-NEXT: [[__C_ADDR_I:%.*]] = alloca i64, align 81342// LE-PWR9-NEXT: [[__MASK_I:%.*]] = alloca <16 x i8>, align 161343// LE-PWR9-NEXT: [[__RES_I:%.*]] = alloca <16 x i8>, align 161344// LE-PWR9-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 81345// LE-PWR9-NEXT: [[DATA_ADDR:%.*]] = alloca <16 x i8>, align 161346// LE-PWR9-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 81347// LE-PWR9-NEXT: store <16 x i8> [[DATA:%.*]], ptr [[DATA_ADDR]], align 161348// LE-PWR9-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr [[DATA_ADDR]], align 161349// LE-PWR9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[PTR_ADDR]], align 81350// LE-PWR9-NEXT: store <16 x i8> [[TMP0]], ptr [[__A_ADDR_I]], align 161351// LE-PWR9-NEXT: store ptr [[TMP1]], ptr [[__B_ADDR_I]], align 81352// LE-PWR9-NEXT: store i64 9, ptr [[__C_ADDR_I]], align 81353// LE-PWR9-NEXT: [[TMP2:%.*]] = load i64, ptr [[__C_ADDR_I]], align 81354// LE-PWR9-NEXT: [[SUB_I:%.*]] = sub i64 16, [[TMP2]]1355// LE-PWR9-NEXT: [[CONV_I:%.*]] = trunc i64 [[SUB_I]] to i81356// LE-PWR9-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr null, i8 [[CONV_I]]1357// LE-PWR9-NEXT: [[TMP4:%.*]] = call <16 x i8> @llvm.ppc.altivec.lvsl(ptr [[TMP3]])1358// LE-PWR9-NEXT: store <16 x i8> [[TMP4]], ptr [[__MASK_I]], align 161359// LE-PWR9-NEXT: [[TMP5:%.*]] = load <16 x i8>, ptr [[__A_ADDR_I]], align 161360// LE-PWR9-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x i32>1361// LE-PWR9-NEXT: [[TMP7:%.*]] = load <16 x i8>, ptr [[__A_ADDR_I]], align 161362// LE-PWR9-NEXT: [[TMP8:%.*]] = bitcast <16 x i8> [[TMP7]] to <4 x i32>1363// LE-PWR9-NEXT: [[TMP9:%.*]] = load <16 x i8>, ptr [[__MASK_I]], align 161364// LE-PWR9-NEXT: [[TMP10:%.*]] = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> [[TMP6]], <4 x i32> [[TMP8]], <16 x i8> [[TMP9]])1365// LE-PWR9-NEXT: [[TMP11:%.*]] = bitcast <4 x i32> [[TMP10]] to <16 x i8>1366// LE-PWR9-NEXT: store <16 x i8> [[TMP11]], ptr [[__RES_I]], align 161367// LE-PWR9-NEXT: [[TMP12:%.*]] = load <16 x i8>, ptr [[__RES_I]], align 161368// LE-PWR9-NEXT: [[TMP13:%.*]] = bitcast <16 x i8> [[TMP12]] to <4 x i32>1369// LE-PWR9-NEXT: [[TMP14:%.*]] = load ptr, ptr [[__B_ADDR_I]], align 81370// LE-PWR9-NEXT: [[TMP15:%.*]] = load i64, ptr [[__C_ADDR_I]], align 81371// LE-PWR9-NEXT: [[SHL_I:%.*]] = shl i64 [[TMP15]], 561372// LE-PWR9-NEXT: call void @llvm.ppc.vsx.stxvll(<4 x i32> [[TMP13]], ptr [[TMP14]], i64 [[SHL_I]])1373// LE-PWR9-NEXT: ret void1374//1375// BE32-PWR9-LABEL: @test_strmb9(1376// BE32-PWR9-NEXT: entry:1377// BE32-PWR9-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 41378// BE32-PWR9-NEXT: [[DATA_ADDR:%.*]] = alloca <16 x i8>, align 161379// BE32-PWR9-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 41380// BE32-PWR9-NEXT: store <16 x i8> [[DATA:%.*]], ptr [[DATA_ADDR]], align 161381// BE32-PWR9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 41382// BE32-PWR9-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr [[DATA_ADDR]], align 161383// BE32-PWR9-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>1384// BE32-PWR9-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr [[TMP0]], i64 11385// BE32-PWR9-NEXT: [[TMP5:%.*]] = extractelement <2 x i64> [[TMP2]], i64 11386// BE32-PWR9-NEXT: store i64 [[TMP5]], ptr [[TMP3]], align 11387// BE32-PWR9-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr [[TMP0]], i64 01388// BE32-PWR9-NEXT: [[TMP7:%.*]] = extractelement <16 x i8> [[TMP1]], i64 71389// BE32-PWR9-NEXT: store i8 [[TMP7]], ptr [[TMP6]], align 11390// BE32-PWR9-NEXT: ret void1391//1392void test_strmb9(char *ptr, vector unsigned char data) {1393 __vec_strmb(ptr, 9, data);1394}1395 1396// BE-PWR8-LABEL: @test_strmb10(1397// BE-PWR8-NEXT: entry:1398// BE-PWR8-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 81399// BE-PWR8-NEXT: [[DATA_ADDR:%.*]] = alloca <16 x i8>, align 161400// BE-PWR8-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 81401// BE-PWR8-NEXT: store <16 x i8> [[DATA:%.*]], ptr [[DATA_ADDR]], align 161402// BE-PWR8-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 81403// BE-PWR8-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr [[DATA_ADDR]], align 161404// BE-PWR8-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>1405// BE-PWR8-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr [[TMP0]], i64 21406// BE-PWR8-NEXT: [[TMP5:%.*]] = extractelement <2 x i64> [[TMP2]], i64 11407// BE-PWR8-NEXT: store i64 [[TMP5]], ptr [[TMP3]], align 11408// BE-PWR8-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>1409// BE-PWR8-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr [[TMP0]], i64 01410// BE-PWR8-NEXT: [[TMP9:%.*]] = extractelement <8 x i16> [[TMP6]], i64 31411// BE-PWR8-NEXT: store i16 [[TMP9]], ptr [[TMP7]], align 11412// BE-PWR8-NEXT: ret void1413//1414// LE-PWR8-LABEL: @test_strmb10(1415// LE-PWR8-NEXT: entry:1416// LE-PWR8-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 81417// LE-PWR8-NEXT: [[DATA_ADDR:%.*]] = alloca <16 x i8>, align 161418// LE-PWR8-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 81419// LE-PWR8-NEXT: store <16 x i8> [[DATA:%.*]], ptr [[DATA_ADDR]], align 161420// LE-PWR8-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 81421// LE-PWR8-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr [[DATA_ADDR]], align 161422// LE-PWR8-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>1423// LE-PWR8-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr [[TMP0]], i64 21424// LE-PWR8-NEXT: [[TMP5:%.*]] = extractelement <2 x i64> [[TMP2]], i64 01425// LE-PWR8-NEXT: [[TMP6:%.*]] = call i64 @llvm.bswap.i64(i64 [[TMP5]])1426// LE-PWR8-NEXT: store i64 [[TMP6]], ptr [[TMP3]], align 11427// LE-PWR8-NEXT: [[TMP7:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>1428// LE-PWR8-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[TMP0]], i64 01429// LE-PWR8-NEXT: [[TMP10:%.*]] = extractelement <8 x i16> [[TMP7]], i64 41430// LE-PWR8-NEXT: [[TMP11:%.*]] = call i16 @llvm.bswap.i16(i16 [[TMP10]])1431// LE-PWR8-NEXT: store i16 [[TMP11]], ptr [[TMP8]], align 11432// LE-PWR8-NEXT: ret void1433//1434// BE-PWR9-LABEL: @test_strmb10(1435// BE-PWR9-NEXT: entry:1436// BE-PWR9-NEXT: [[__A_ADDR_I:%.*]] = alloca <16 x i8>, align 161437// BE-PWR9-NEXT: [[__B_ADDR_I:%.*]] = alloca ptr, align 81438// BE-PWR9-NEXT: [[__C_ADDR_I:%.*]] = alloca i64, align 81439// BE-PWR9-NEXT: [[__MASK_I:%.*]] = alloca <16 x i8>, align 161440// BE-PWR9-NEXT: [[__RES_I:%.*]] = alloca <16 x i8>, align 161441// BE-PWR9-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 81442// BE-PWR9-NEXT: [[DATA_ADDR:%.*]] = alloca <16 x i8>, align 161443// BE-PWR9-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 81444// BE-PWR9-NEXT: store <16 x i8> [[DATA:%.*]], ptr [[DATA_ADDR]], align 161445// BE-PWR9-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr [[DATA_ADDR]], align 161446// BE-PWR9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[PTR_ADDR]], align 81447// BE-PWR9-NEXT: store <16 x i8> [[TMP0]], ptr [[__A_ADDR_I]], align 161448// BE-PWR9-NEXT: store ptr [[TMP1]], ptr [[__B_ADDR_I]], align 81449// BE-PWR9-NEXT: store i64 10, ptr [[__C_ADDR_I]], align 81450// BE-PWR9-NEXT: [[TMP2:%.*]] = load i64, ptr [[__C_ADDR_I]], align 81451// BE-PWR9-NEXT: [[SUB_I:%.*]] = sub i64 16, [[TMP2]]1452// BE-PWR9-NEXT: [[CONV_I:%.*]] = trunc i64 [[SUB_I]] to i81453// BE-PWR9-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr null, i8 [[CONV_I]]1454// BE-PWR9-NEXT: [[TMP4:%.*]] = call <16 x i8> @llvm.ppc.altivec.lvsl(ptr [[TMP3]])1455// BE-PWR9-NEXT: store <16 x i8> [[TMP4]], ptr [[__MASK_I]], align 161456// BE-PWR9-NEXT: [[TMP5:%.*]] = load <16 x i8>, ptr [[__A_ADDR_I]], align 161457// BE-PWR9-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x i32>1458// BE-PWR9-NEXT: [[TMP7:%.*]] = load <16 x i8>, ptr [[__A_ADDR_I]], align 161459// BE-PWR9-NEXT: [[TMP8:%.*]] = bitcast <16 x i8> [[TMP7]] to <4 x i32>1460// BE-PWR9-NEXT: [[TMP9:%.*]] = load <16 x i8>, ptr [[__MASK_I]], align 161461// BE-PWR9-NEXT: [[TMP10:%.*]] = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> [[TMP6]], <4 x i32> [[TMP8]], <16 x i8> [[TMP9]])1462// BE-PWR9-NEXT: [[TMP11:%.*]] = bitcast <4 x i32> [[TMP10]] to <16 x i8>1463// BE-PWR9-NEXT: store <16 x i8> [[TMP11]], ptr [[__RES_I]], align 161464// BE-PWR9-NEXT: [[TMP12:%.*]] = load <16 x i8>, ptr [[__RES_I]], align 161465// BE-PWR9-NEXT: [[TMP13:%.*]] = bitcast <16 x i8> [[TMP12]] to <4 x i32>1466// BE-PWR9-NEXT: [[TMP14:%.*]] = load ptr, ptr [[__B_ADDR_I]], align 81467// BE-PWR9-NEXT: [[TMP15:%.*]] = load i64, ptr [[__C_ADDR_I]], align 81468// BE-PWR9-NEXT: [[SHL_I:%.*]] = shl i64 [[TMP15]], 561469// BE-PWR9-NEXT: call void @llvm.ppc.vsx.stxvll(<4 x i32> [[TMP13]], ptr [[TMP14]], i64 [[SHL_I]])1470// BE-PWR9-NEXT: ret void1471//1472// LE-PWR9-LABEL: @test_strmb10(1473// LE-PWR9-NEXT: entry:1474// LE-PWR9-NEXT: [[__A_ADDR_I:%.*]] = alloca <16 x i8>, align 161475// LE-PWR9-NEXT: [[__B_ADDR_I:%.*]] = alloca ptr, align 81476// LE-PWR9-NEXT: [[__C_ADDR_I:%.*]] = alloca i64, align 81477// LE-PWR9-NEXT: [[__MASK_I:%.*]] = alloca <16 x i8>, align 161478// LE-PWR9-NEXT: [[__RES_I:%.*]] = alloca <16 x i8>, align 161479// LE-PWR9-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 81480// LE-PWR9-NEXT: [[DATA_ADDR:%.*]] = alloca <16 x i8>, align 161481// LE-PWR9-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 81482// LE-PWR9-NEXT: store <16 x i8> [[DATA:%.*]], ptr [[DATA_ADDR]], align 161483// LE-PWR9-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr [[DATA_ADDR]], align 161484// LE-PWR9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[PTR_ADDR]], align 81485// LE-PWR9-NEXT: store <16 x i8> [[TMP0]], ptr [[__A_ADDR_I]], align 161486// LE-PWR9-NEXT: store ptr [[TMP1]], ptr [[__B_ADDR_I]], align 81487// LE-PWR9-NEXT: store i64 10, ptr [[__C_ADDR_I]], align 81488// LE-PWR9-NEXT: [[TMP2:%.*]] = load i64, ptr [[__C_ADDR_I]], align 81489// LE-PWR9-NEXT: [[SUB_I:%.*]] = sub i64 16, [[TMP2]]1490// LE-PWR9-NEXT: [[CONV_I:%.*]] = trunc i64 [[SUB_I]] to i81491// LE-PWR9-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr null, i8 [[CONV_I]]1492// LE-PWR9-NEXT: [[TMP4:%.*]] = call <16 x i8> @llvm.ppc.altivec.lvsl(ptr [[TMP3]])1493// LE-PWR9-NEXT: store <16 x i8> [[TMP4]], ptr [[__MASK_I]], align 161494// LE-PWR9-NEXT: [[TMP5:%.*]] = load <16 x i8>, ptr [[__A_ADDR_I]], align 161495// LE-PWR9-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x i32>1496// LE-PWR9-NEXT: [[TMP7:%.*]] = load <16 x i8>, ptr [[__A_ADDR_I]], align 161497// LE-PWR9-NEXT: [[TMP8:%.*]] = bitcast <16 x i8> [[TMP7]] to <4 x i32>1498// LE-PWR9-NEXT: [[TMP9:%.*]] = load <16 x i8>, ptr [[__MASK_I]], align 161499// LE-PWR9-NEXT: [[TMP10:%.*]] = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> [[TMP6]], <4 x i32> [[TMP8]], <16 x i8> [[TMP9]])1500// LE-PWR9-NEXT: [[TMP11:%.*]] = bitcast <4 x i32> [[TMP10]] to <16 x i8>1501// LE-PWR9-NEXT: store <16 x i8> [[TMP11]], ptr [[__RES_I]], align 161502// LE-PWR9-NEXT: [[TMP12:%.*]] = load <16 x i8>, ptr [[__RES_I]], align 161503// LE-PWR9-NEXT: [[TMP13:%.*]] = bitcast <16 x i8> [[TMP12]] to <4 x i32>1504// LE-PWR9-NEXT: [[TMP14:%.*]] = load ptr, ptr [[__B_ADDR_I]], align 81505// LE-PWR9-NEXT: [[TMP15:%.*]] = load i64, ptr [[__C_ADDR_I]], align 81506// LE-PWR9-NEXT: [[SHL_I:%.*]] = shl i64 [[TMP15]], 561507// LE-PWR9-NEXT: call void @llvm.ppc.vsx.stxvll(<4 x i32> [[TMP13]], ptr [[TMP14]], i64 [[SHL_I]])1508// LE-PWR9-NEXT: ret void1509//1510// BE32-PWR9-LABEL: @test_strmb10(1511// BE32-PWR9-NEXT: entry:1512// BE32-PWR9-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 41513// BE32-PWR9-NEXT: [[DATA_ADDR:%.*]] = alloca <16 x i8>, align 161514// BE32-PWR9-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 41515// BE32-PWR9-NEXT: store <16 x i8> [[DATA:%.*]], ptr [[DATA_ADDR]], align 161516// BE32-PWR9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 41517// BE32-PWR9-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr [[DATA_ADDR]], align 161518// BE32-PWR9-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>1519// BE32-PWR9-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr [[TMP0]], i64 21520// BE32-PWR9-NEXT: [[TMP5:%.*]] = extractelement <2 x i64> [[TMP2]], i64 11521// BE32-PWR9-NEXT: store i64 [[TMP5]], ptr [[TMP3]], align 11522// BE32-PWR9-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>1523// BE32-PWR9-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr [[TMP0]], i64 01524// BE32-PWR9-NEXT: [[TMP9:%.*]] = extractelement <8 x i16> [[TMP6]], i64 31525// BE32-PWR9-NEXT: store i16 [[TMP9]], ptr [[TMP7]], align 11526// BE32-PWR9-NEXT: ret void1527//1528void test_strmb10(char *ptr, vector unsigned char data) {1529 __vec_strmb(ptr, 10, data);1530}1531 1532// BE-PWR8-LABEL: @test_strmb11(1533// BE-PWR8-NEXT: entry:1534// BE-PWR8-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 81535// BE-PWR8-NEXT: [[DATA_ADDR:%.*]] = alloca <16 x i8>, align 161536// BE-PWR8-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 81537// BE-PWR8-NEXT: store <16 x i8> [[DATA:%.*]], ptr [[DATA_ADDR]], align 161538// BE-PWR8-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 81539// BE-PWR8-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr [[DATA_ADDR]], align 161540// BE-PWR8-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>1541// BE-PWR8-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr [[TMP0]], i64 31542// BE-PWR8-NEXT: [[TMP5:%.*]] = extractelement <2 x i64> [[TMP2]], i64 11543// BE-PWR8-NEXT: store i64 [[TMP5]], ptr [[TMP3]], align 11544// BE-PWR8-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>1545// BE-PWR8-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr [[TMP0]], i64 11546// BE-PWR8-NEXT: [[TMP9:%.*]] = extractelement <8 x i16> [[TMP6]], i64 31547// BE-PWR8-NEXT: store i16 [[TMP9]], ptr [[TMP7]], align 11548// BE-PWR8-NEXT: [[TMP10:%.*]] = getelementptr i8, ptr [[TMP0]], i64 01549// BE-PWR8-NEXT: [[TMP11:%.*]] = extractelement <16 x i8> [[TMP1]], i64 51550// BE-PWR8-NEXT: store i8 [[TMP11]], ptr [[TMP10]], align 11551// BE-PWR8-NEXT: ret void1552//1553// LE-PWR8-LABEL: @test_strmb11(1554// LE-PWR8-NEXT: entry:1555// LE-PWR8-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 81556// LE-PWR8-NEXT: [[DATA_ADDR:%.*]] = alloca <16 x i8>, align 161557// LE-PWR8-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 81558// LE-PWR8-NEXT: store <16 x i8> [[DATA:%.*]], ptr [[DATA_ADDR]], align 161559// LE-PWR8-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 81560// LE-PWR8-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr [[DATA_ADDR]], align 161561// LE-PWR8-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>1562// LE-PWR8-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr [[TMP0]], i64 31563// LE-PWR8-NEXT: [[TMP5:%.*]] = extractelement <2 x i64> [[TMP2]], i64 01564// LE-PWR8-NEXT: [[TMP6:%.*]] = call i64 @llvm.bswap.i64(i64 [[TMP5]])1565// LE-PWR8-NEXT: store i64 [[TMP6]], ptr [[TMP3]], align 11566// LE-PWR8-NEXT: [[TMP7:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>1567// LE-PWR8-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[TMP0]], i64 11568// LE-PWR8-NEXT: [[TMP10:%.*]] = extractelement <8 x i16> [[TMP7]], i64 41569// LE-PWR8-NEXT: [[TMP11:%.*]] = call i16 @llvm.bswap.i16(i16 [[TMP10]])1570// LE-PWR8-NEXT: store i16 [[TMP11]], ptr [[TMP8]], align 11571// LE-PWR8-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[TMP0]], i64 01572// LE-PWR8-NEXT: [[TMP13:%.*]] = extractelement <16 x i8> [[TMP1]], i64 101573// LE-PWR8-NEXT: store i8 [[TMP13]], ptr [[TMP12]], align 11574// LE-PWR8-NEXT: ret void1575//1576// BE-PWR9-LABEL: @test_strmb11(1577// BE-PWR9-NEXT: entry:1578// BE-PWR9-NEXT: [[__A_ADDR_I:%.*]] = alloca <16 x i8>, align 161579// BE-PWR9-NEXT: [[__B_ADDR_I:%.*]] = alloca ptr, align 81580// BE-PWR9-NEXT: [[__C_ADDR_I:%.*]] = alloca i64, align 81581// BE-PWR9-NEXT: [[__MASK_I:%.*]] = alloca <16 x i8>, align 161582// BE-PWR9-NEXT: [[__RES_I:%.*]] = alloca <16 x i8>, align 161583// BE-PWR9-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 81584// BE-PWR9-NEXT: [[DATA_ADDR:%.*]] = alloca <16 x i8>, align 161585// BE-PWR9-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 81586// BE-PWR9-NEXT: store <16 x i8> [[DATA:%.*]], ptr [[DATA_ADDR]], align 161587// BE-PWR9-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr [[DATA_ADDR]], align 161588// BE-PWR9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[PTR_ADDR]], align 81589// BE-PWR9-NEXT: store <16 x i8> [[TMP0]], ptr [[__A_ADDR_I]], align 161590// BE-PWR9-NEXT: store ptr [[TMP1]], ptr [[__B_ADDR_I]], align 81591// BE-PWR9-NEXT: store i64 11, ptr [[__C_ADDR_I]], align 81592// BE-PWR9-NEXT: [[TMP2:%.*]] = load i64, ptr [[__C_ADDR_I]], align 81593// BE-PWR9-NEXT: [[SUB_I:%.*]] = sub i64 16, [[TMP2]]1594// BE-PWR9-NEXT: [[CONV_I:%.*]] = trunc i64 [[SUB_I]] to i81595// BE-PWR9-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr null, i8 [[CONV_I]]1596// BE-PWR9-NEXT: [[TMP4:%.*]] = call <16 x i8> @llvm.ppc.altivec.lvsl(ptr [[TMP3]])1597// BE-PWR9-NEXT: store <16 x i8> [[TMP4]], ptr [[__MASK_I]], align 161598// BE-PWR9-NEXT: [[TMP5:%.*]] = load <16 x i8>, ptr [[__A_ADDR_I]], align 161599// BE-PWR9-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x i32>1600// BE-PWR9-NEXT: [[TMP7:%.*]] = load <16 x i8>, ptr [[__A_ADDR_I]], align 161601// BE-PWR9-NEXT: [[TMP8:%.*]] = bitcast <16 x i8> [[TMP7]] to <4 x i32>1602// BE-PWR9-NEXT: [[TMP9:%.*]] = load <16 x i8>, ptr [[__MASK_I]], align 161603// BE-PWR9-NEXT: [[TMP10:%.*]] = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> [[TMP6]], <4 x i32> [[TMP8]], <16 x i8> [[TMP9]])1604// BE-PWR9-NEXT: [[TMP11:%.*]] = bitcast <4 x i32> [[TMP10]] to <16 x i8>1605// BE-PWR9-NEXT: store <16 x i8> [[TMP11]], ptr [[__RES_I]], align 161606// BE-PWR9-NEXT: [[TMP12:%.*]] = load <16 x i8>, ptr [[__RES_I]], align 161607// BE-PWR9-NEXT: [[TMP13:%.*]] = bitcast <16 x i8> [[TMP12]] to <4 x i32>1608// BE-PWR9-NEXT: [[TMP14:%.*]] = load ptr, ptr [[__B_ADDR_I]], align 81609// BE-PWR9-NEXT: [[TMP15:%.*]] = load i64, ptr [[__C_ADDR_I]], align 81610// BE-PWR9-NEXT: [[SHL_I:%.*]] = shl i64 [[TMP15]], 561611// BE-PWR9-NEXT: call void @llvm.ppc.vsx.stxvll(<4 x i32> [[TMP13]], ptr [[TMP14]], i64 [[SHL_I]])1612// BE-PWR9-NEXT: ret void1613//1614// LE-PWR9-LABEL: @test_strmb11(1615// LE-PWR9-NEXT: entry:1616// LE-PWR9-NEXT: [[__A_ADDR_I:%.*]] = alloca <16 x i8>, align 161617// LE-PWR9-NEXT: [[__B_ADDR_I:%.*]] = alloca ptr, align 81618// LE-PWR9-NEXT: [[__C_ADDR_I:%.*]] = alloca i64, align 81619// LE-PWR9-NEXT: [[__MASK_I:%.*]] = alloca <16 x i8>, align 161620// LE-PWR9-NEXT: [[__RES_I:%.*]] = alloca <16 x i8>, align 161621// LE-PWR9-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 81622// LE-PWR9-NEXT: [[DATA_ADDR:%.*]] = alloca <16 x i8>, align 161623// LE-PWR9-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 81624// LE-PWR9-NEXT: store <16 x i8> [[DATA:%.*]], ptr [[DATA_ADDR]], align 161625// LE-PWR9-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr [[DATA_ADDR]], align 161626// LE-PWR9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[PTR_ADDR]], align 81627// LE-PWR9-NEXT: store <16 x i8> [[TMP0]], ptr [[__A_ADDR_I]], align 161628// LE-PWR9-NEXT: store ptr [[TMP1]], ptr [[__B_ADDR_I]], align 81629// LE-PWR9-NEXT: store i64 11, ptr [[__C_ADDR_I]], align 81630// LE-PWR9-NEXT: [[TMP2:%.*]] = load i64, ptr [[__C_ADDR_I]], align 81631// LE-PWR9-NEXT: [[SUB_I:%.*]] = sub i64 16, [[TMP2]]1632// LE-PWR9-NEXT: [[CONV_I:%.*]] = trunc i64 [[SUB_I]] to i81633// LE-PWR9-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr null, i8 [[CONV_I]]1634// LE-PWR9-NEXT: [[TMP4:%.*]] = call <16 x i8> @llvm.ppc.altivec.lvsl(ptr [[TMP3]])1635// LE-PWR9-NEXT: store <16 x i8> [[TMP4]], ptr [[__MASK_I]], align 161636// LE-PWR9-NEXT: [[TMP5:%.*]] = load <16 x i8>, ptr [[__A_ADDR_I]], align 161637// LE-PWR9-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x i32>1638// LE-PWR9-NEXT: [[TMP7:%.*]] = load <16 x i8>, ptr [[__A_ADDR_I]], align 161639// LE-PWR9-NEXT: [[TMP8:%.*]] = bitcast <16 x i8> [[TMP7]] to <4 x i32>1640// LE-PWR9-NEXT: [[TMP9:%.*]] = load <16 x i8>, ptr [[__MASK_I]], align 161641// LE-PWR9-NEXT: [[TMP10:%.*]] = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> [[TMP6]], <4 x i32> [[TMP8]], <16 x i8> [[TMP9]])1642// LE-PWR9-NEXT: [[TMP11:%.*]] = bitcast <4 x i32> [[TMP10]] to <16 x i8>1643// LE-PWR9-NEXT: store <16 x i8> [[TMP11]], ptr [[__RES_I]], align 161644// LE-PWR9-NEXT: [[TMP12:%.*]] = load <16 x i8>, ptr [[__RES_I]], align 161645// LE-PWR9-NEXT: [[TMP13:%.*]] = bitcast <16 x i8> [[TMP12]] to <4 x i32>1646// LE-PWR9-NEXT: [[TMP14:%.*]] = load ptr, ptr [[__B_ADDR_I]], align 81647// LE-PWR9-NEXT: [[TMP15:%.*]] = load i64, ptr [[__C_ADDR_I]], align 81648// LE-PWR9-NEXT: [[SHL_I:%.*]] = shl i64 [[TMP15]], 561649// LE-PWR9-NEXT: call void @llvm.ppc.vsx.stxvll(<4 x i32> [[TMP13]], ptr [[TMP14]], i64 [[SHL_I]])1650// LE-PWR9-NEXT: ret void1651//1652// BE32-PWR9-LABEL: @test_strmb11(1653// BE32-PWR9-NEXT: entry:1654// BE32-PWR9-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 41655// BE32-PWR9-NEXT: [[DATA_ADDR:%.*]] = alloca <16 x i8>, align 161656// BE32-PWR9-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 41657// BE32-PWR9-NEXT: store <16 x i8> [[DATA:%.*]], ptr [[DATA_ADDR]], align 161658// BE32-PWR9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 41659// BE32-PWR9-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr [[DATA_ADDR]], align 161660// BE32-PWR9-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>1661// BE32-PWR9-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr [[TMP0]], i64 31662// BE32-PWR9-NEXT: [[TMP5:%.*]] = extractelement <2 x i64> [[TMP2]], i64 11663// BE32-PWR9-NEXT: store i64 [[TMP5]], ptr [[TMP3]], align 11664// BE32-PWR9-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>1665// BE32-PWR9-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr [[TMP0]], i64 11666// BE32-PWR9-NEXT: [[TMP9:%.*]] = extractelement <8 x i16> [[TMP6]], i64 31667// BE32-PWR9-NEXT: store i16 [[TMP9]], ptr [[TMP7]], align 11668// BE32-PWR9-NEXT: [[TMP10:%.*]] = getelementptr i8, ptr [[TMP0]], i64 01669// BE32-PWR9-NEXT: [[TMP11:%.*]] = extractelement <16 x i8> [[TMP1]], i64 51670// BE32-PWR9-NEXT: store i8 [[TMP11]], ptr [[TMP10]], align 11671// BE32-PWR9-NEXT: ret void1672//1673void test_strmb11(char *ptr, vector unsigned char data) {1674 __vec_strmb(ptr, 11, data);1675}1676 1677// BE-PWR8-LABEL: @test_strmb12(1678// BE-PWR8-NEXT: entry:1679// BE-PWR8-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 81680// BE-PWR8-NEXT: [[DATA_ADDR:%.*]] = alloca <16 x i8>, align 161681// BE-PWR8-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 81682// BE-PWR8-NEXT: store <16 x i8> [[DATA:%.*]], ptr [[DATA_ADDR]], align 161683// BE-PWR8-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 81684// BE-PWR8-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr [[DATA_ADDR]], align 161685// BE-PWR8-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>1686// BE-PWR8-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr [[TMP0]], i64 41687// BE-PWR8-NEXT: [[TMP5:%.*]] = extractelement <2 x i64> [[TMP2]], i64 11688// BE-PWR8-NEXT: store i64 [[TMP5]], ptr [[TMP3]], align 11689// BE-PWR8-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>1690// BE-PWR8-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr [[TMP0]], i64 01691// BE-PWR8-NEXT: [[TMP9:%.*]] = extractelement <4 x i32> [[TMP6]], i64 11692// BE-PWR8-NEXT: store i32 [[TMP9]], ptr [[TMP7]], align 11693// BE-PWR8-NEXT: ret void1694//1695// LE-PWR8-LABEL: @test_strmb12(1696// LE-PWR8-NEXT: entry:1697// LE-PWR8-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 81698// LE-PWR8-NEXT: [[DATA_ADDR:%.*]] = alloca <16 x i8>, align 161699// LE-PWR8-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 81700// LE-PWR8-NEXT: store <16 x i8> [[DATA:%.*]], ptr [[DATA_ADDR]], align 161701// LE-PWR8-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 81702// LE-PWR8-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr [[DATA_ADDR]], align 161703// LE-PWR8-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>1704// LE-PWR8-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr [[TMP0]], i64 41705// LE-PWR8-NEXT: [[TMP5:%.*]] = extractelement <2 x i64> [[TMP2]], i64 01706// LE-PWR8-NEXT: [[TMP6:%.*]] = call i64 @llvm.bswap.i64(i64 [[TMP5]])1707// LE-PWR8-NEXT: store i64 [[TMP6]], ptr [[TMP3]], align 11708// LE-PWR8-NEXT: [[TMP7:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>1709// LE-PWR8-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[TMP0]], i64 01710// LE-PWR8-NEXT: [[TMP10:%.*]] = extractelement <4 x i32> [[TMP7]], i64 21711// LE-PWR8-NEXT: [[TMP11:%.*]] = call i32 @llvm.bswap.i32(i32 [[TMP10]])1712// LE-PWR8-NEXT: store i32 [[TMP11]], ptr [[TMP8]], align 11713// LE-PWR8-NEXT: ret void1714//1715// BE-PWR9-LABEL: @test_strmb12(1716// BE-PWR9-NEXT: entry:1717// BE-PWR9-NEXT: [[__A_ADDR_I:%.*]] = alloca <16 x i8>, align 161718// BE-PWR9-NEXT: [[__B_ADDR_I:%.*]] = alloca ptr, align 81719// BE-PWR9-NEXT: [[__C_ADDR_I:%.*]] = alloca i64, align 81720// BE-PWR9-NEXT: [[__MASK_I:%.*]] = alloca <16 x i8>, align 161721// BE-PWR9-NEXT: [[__RES_I:%.*]] = alloca <16 x i8>, align 161722// BE-PWR9-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 81723// BE-PWR9-NEXT: [[DATA_ADDR:%.*]] = alloca <16 x i8>, align 161724// BE-PWR9-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 81725// BE-PWR9-NEXT: store <16 x i8> [[DATA:%.*]], ptr [[DATA_ADDR]], align 161726// BE-PWR9-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr [[DATA_ADDR]], align 161727// BE-PWR9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[PTR_ADDR]], align 81728// BE-PWR9-NEXT: store <16 x i8> [[TMP0]], ptr [[__A_ADDR_I]], align 161729// BE-PWR9-NEXT: store ptr [[TMP1]], ptr [[__B_ADDR_I]], align 81730// BE-PWR9-NEXT: store i64 12, ptr [[__C_ADDR_I]], align 81731// BE-PWR9-NEXT: [[TMP2:%.*]] = load i64, ptr [[__C_ADDR_I]], align 81732// BE-PWR9-NEXT: [[SUB_I:%.*]] = sub i64 16, [[TMP2]]1733// BE-PWR9-NEXT: [[CONV_I:%.*]] = trunc i64 [[SUB_I]] to i81734// BE-PWR9-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr null, i8 [[CONV_I]]1735// BE-PWR9-NEXT: [[TMP4:%.*]] = call <16 x i8> @llvm.ppc.altivec.lvsl(ptr [[TMP3]])1736// BE-PWR9-NEXT: store <16 x i8> [[TMP4]], ptr [[__MASK_I]], align 161737// BE-PWR9-NEXT: [[TMP5:%.*]] = load <16 x i8>, ptr [[__A_ADDR_I]], align 161738// BE-PWR9-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x i32>1739// BE-PWR9-NEXT: [[TMP7:%.*]] = load <16 x i8>, ptr [[__A_ADDR_I]], align 161740// BE-PWR9-NEXT: [[TMP8:%.*]] = bitcast <16 x i8> [[TMP7]] to <4 x i32>1741// BE-PWR9-NEXT: [[TMP9:%.*]] = load <16 x i8>, ptr [[__MASK_I]], align 161742// BE-PWR9-NEXT: [[TMP10:%.*]] = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> [[TMP6]], <4 x i32> [[TMP8]], <16 x i8> [[TMP9]])1743// BE-PWR9-NEXT: [[TMP11:%.*]] = bitcast <4 x i32> [[TMP10]] to <16 x i8>1744// BE-PWR9-NEXT: store <16 x i8> [[TMP11]], ptr [[__RES_I]], align 161745// BE-PWR9-NEXT: [[TMP12:%.*]] = load <16 x i8>, ptr [[__RES_I]], align 161746// BE-PWR9-NEXT: [[TMP13:%.*]] = bitcast <16 x i8> [[TMP12]] to <4 x i32>1747// BE-PWR9-NEXT: [[TMP14:%.*]] = load ptr, ptr [[__B_ADDR_I]], align 81748// BE-PWR9-NEXT: [[TMP15:%.*]] = load i64, ptr [[__C_ADDR_I]], align 81749// BE-PWR9-NEXT: [[SHL_I:%.*]] = shl i64 [[TMP15]], 561750// BE-PWR9-NEXT: call void @llvm.ppc.vsx.stxvll(<4 x i32> [[TMP13]], ptr [[TMP14]], i64 [[SHL_I]])1751// BE-PWR9-NEXT: ret void1752//1753// LE-PWR9-LABEL: @test_strmb12(1754// LE-PWR9-NEXT: entry:1755// LE-PWR9-NEXT: [[__A_ADDR_I:%.*]] = alloca <16 x i8>, align 161756// LE-PWR9-NEXT: [[__B_ADDR_I:%.*]] = alloca ptr, align 81757// LE-PWR9-NEXT: [[__C_ADDR_I:%.*]] = alloca i64, align 81758// LE-PWR9-NEXT: [[__MASK_I:%.*]] = alloca <16 x i8>, align 161759// LE-PWR9-NEXT: [[__RES_I:%.*]] = alloca <16 x i8>, align 161760// LE-PWR9-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 81761// LE-PWR9-NEXT: [[DATA_ADDR:%.*]] = alloca <16 x i8>, align 161762// LE-PWR9-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 81763// LE-PWR9-NEXT: store <16 x i8> [[DATA:%.*]], ptr [[DATA_ADDR]], align 161764// LE-PWR9-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr [[DATA_ADDR]], align 161765// LE-PWR9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[PTR_ADDR]], align 81766// LE-PWR9-NEXT: store <16 x i8> [[TMP0]], ptr [[__A_ADDR_I]], align 161767// LE-PWR9-NEXT: store ptr [[TMP1]], ptr [[__B_ADDR_I]], align 81768// LE-PWR9-NEXT: store i64 12, ptr [[__C_ADDR_I]], align 81769// LE-PWR9-NEXT: [[TMP2:%.*]] = load i64, ptr [[__C_ADDR_I]], align 81770// LE-PWR9-NEXT: [[SUB_I:%.*]] = sub i64 16, [[TMP2]]1771// LE-PWR9-NEXT: [[CONV_I:%.*]] = trunc i64 [[SUB_I]] to i81772// LE-PWR9-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr null, i8 [[CONV_I]]1773// LE-PWR9-NEXT: [[TMP4:%.*]] = call <16 x i8> @llvm.ppc.altivec.lvsl(ptr [[TMP3]])1774// LE-PWR9-NEXT: store <16 x i8> [[TMP4]], ptr [[__MASK_I]], align 161775// LE-PWR9-NEXT: [[TMP5:%.*]] = load <16 x i8>, ptr [[__A_ADDR_I]], align 161776// LE-PWR9-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x i32>1777// LE-PWR9-NEXT: [[TMP7:%.*]] = load <16 x i8>, ptr [[__A_ADDR_I]], align 161778// LE-PWR9-NEXT: [[TMP8:%.*]] = bitcast <16 x i8> [[TMP7]] to <4 x i32>1779// LE-PWR9-NEXT: [[TMP9:%.*]] = load <16 x i8>, ptr [[__MASK_I]], align 161780// LE-PWR9-NEXT: [[TMP10:%.*]] = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> [[TMP6]], <4 x i32> [[TMP8]], <16 x i8> [[TMP9]])1781// LE-PWR9-NEXT: [[TMP11:%.*]] = bitcast <4 x i32> [[TMP10]] to <16 x i8>1782// LE-PWR9-NEXT: store <16 x i8> [[TMP11]], ptr [[__RES_I]], align 161783// LE-PWR9-NEXT: [[TMP12:%.*]] = load <16 x i8>, ptr [[__RES_I]], align 161784// LE-PWR9-NEXT: [[TMP13:%.*]] = bitcast <16 x i8> [[TMP12]] to <4 x i32>1785// LE-PWR9-NEXT: [[TMP14:%.*]] = load ptr, ptr [[__B_ADDR_I]], align 81786// LE-PWR9-NEXT: [[TMP15:%.*]] = load i64, ptr [[__C_ADDR_I]], align 81787// LE-PWR9-NEXT: [[SHL_I:%.*]] = shl i64 [[TMP15]], 561788// LE-PWR9-NEXT: call void @llvm.ppc.vsx.stxvll(<4 x i32> [[TMP13]], ptr [[TMP14]], i64 [[SHL_I]])1789// LE-PWR9-NEXT: ret void1790//1791// BE32-PWR9-LABEL: @test_strmb12(1792// BE32-PWR9-NEXT: entry:1793// BE32-PWR9-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 41794// BE32-PWR9-NEXT: [[DATA_ADDR:%.*]] = alloca <16 x i8>, align 161795// BE32-PWR9-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 41796// BE32-PWR9-NEXT: store <16 x i8> [[DATA:%.*]], ptr [[DATA_ADDR]], align 161797// BE32-PWR9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 41798// BE32-PWR9-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr [[DATA_ADDR]], align 161799// BE32-PWR9-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>1800// BE32-PWR9-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr [[TMP0]], i64 41801// BE32-PWR9-NEXT: [[TMP5:%.*]] = extractelement <2 x i64> [[TMP2]], i64 11802// BE32-PWR9-NEXT: store i64 [[TMP5]], ptr [[TMP3]], align 11803// BE32-PWR9-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>1804// BE32-PWR9-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr [[TMP0]], i64 01805// BE32-PWR9-NEXT: [[TMP9:%.*]] = extractelement <4 x i32> [[TMP6]], i64 11806// BE32-PWR9-NEXT: store i32 [[TMP9]], ptr [[TMP7]], align 11807// BE32-PWR9-NEXT: ret void1808//1809void test_strmb12(char *ptr, vector unsigned char data) {1810 __vec_strmb(ptr, 12, data);1811}1812 1813// BE-PWR8-LABEL: @test_strmb13(1814// BE-PWR8-NEXT: entry:1815// BE-PWR8-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 81816// BE-PWR8-NEXT: [[DATA_ADDR:%.*]] = alloca <16 x i8>, align 161817// BE-PWR8-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 81818// BE-PWR8-NEXT: store <16 x i8> [[DATA:%.*]], ptr [[DATA_ADDR]], align 161819// BE-PWR8-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 81820// BE-PWR8-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr [[DATA_ADDR]], align 161821// BE-PWR8-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>1822// BE-PWR8-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr [[TMP0]], i64 51823// BE-PWR8-NEXT: [[TMP5:%.*]] = extractelement <2 x i64> [[TMP2]], i64 11824// BE-PWR8-NEXT: store i64 [[TMP5]], ptr [[TMP3]], align 11825// BE-PWR8-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>1826// BE-PWR8-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr [[TMP0]], i64 11827// BE-PWR8-NEXT: [[TMP9:%.*]] = extractelement <4 x i32> [[TMP6]], i64 11828// BE-PWR8-NEXT: store i32 [[TMP9]], ptr [[TMP7]], align 11829// BE-PWR8-NEXT: [[TMP10:%.*]] = getelementptr i8, ptr [[TMP0]], i64 01830// BE-PWR8-NEXT: [[TMP11:%.*]] = extractelement <16 x i8> [[TMP1]], i64 31831// BE-PWR8-NEXT: store i8 [[TMP11]], ptr [[TMP10]], align 11832// BE-PWR8-NEXT: ret void1833//1834// LE-PWR8-LABEL: @test_strmb13(1835// LE-PWR8-NEXT: entry:1836// LE-PWR8-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 81837// LE-PWR8-NEXT: [[DATA_ADDR:%.*]] = alloca <16 x i8>, align 161838// LE-PWR8-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 81839// LE-PWR8-NEXT: store <16 x i8> [[DATA:%.*]], ptr [[DATA_ADDR]], align 161840// LE-PWR8-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 81841// LE-PWR8-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr [[DATA_ADDR]], align 161842// LE-PWR8-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>1843// LE-PWR8-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr [[TMP0]], i64 51844// LE-PWR8-NEXT: [[TMP5:%.*]] = extractelement <2 x i64> [[TMP2]], i64 01845// LE-PWR8-NEXT: [[TMP6:%.*]] = call i64 @llvm.bswap.i64(i64 [[TMP5]])1846// LE-PWR8-NEXT: store i64 [[TMP6]], ptr [[TMP3]], align 11847// LE-PWR8-NEXT: [[TMP7:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>1848// LE-PWR8-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[TMP0]], i64 11849// LE-PWR8-NEXT: [[TMP10:%.*]] = extractelement <4 x i32> [[TMP7]], i64 21850// LE-PWR8-NEXT: [[TMP11:%.*]] = call i32 @llvm.bswap.i32(i32 [[TMP10]])1851// LE-PWR8-NEXT: store i32 [[TMP11]], ptr [[TMP8]], align 11852// LE-PWR8-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[TMP0]], i64 01853// LE-PWR8-NEXT: [[TMP13:%.*]] = extractelement <16 x i8> [[TMP1]], i64 121854// LE-PWR8-NEXT: store i8 [[TMP13]], ptr [[TMP12]], align 11855// LE-PWR8-NEXT: ret void1856//1857// BE-PWR9-LABEL: @test_strmb13(1858// BE-PWR9-NEXT: entry:1859// BE-PWR9-NEXT: [[__A_ADDR_I:%.*]] = alloca <16 x i8>, align 161860// BE-PWR9-NEXT: [[__B_ADDR_I:%.*]] = alloca ptr, align 81861// BE-PWR9-NEXT: [[__C_ADDR_I:%.*]] = alloca i64, align 81862// BE-PWR9-NEXT: [[__MASK_I:%.*]] = alloca <16 x i8>, align 161863// BE-PWR9-NEXT: [[__RES_I:%.*]] = alloca <16 x i8>, align 161864// BE-PWR9-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 81865// BE-PWR9-NEXT: [[DATA_ADDR:%.*]] = alloca <16 x i8>, align 161866// BE-PWR9-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 81867// BE-PWR9-NEXT: store <16 x i8> [[DATA:%.*]], ptr [[DATA_ADDR]], align 161868// BE-PWR9-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr [[DATA_ADDR]], align 161869// BE-PWR9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[PTR_ADDR]], align 81870// BE-PWR9-NEXT: store <16 x i8> [[TMP0]], ptr [[__A_ADDR_I]], align 161871// BE-PWR9-NEXT: store ptr [[TMP1]], ptr [[__B_ADDR_I]], align 81872// BE-PWR9-NEXT: store i64 13, ptr [[__C_ADDR_I]], align 81873// BE-PWR9-NEXT: [[TMP2:%.*]] = load i64, ptr [[__C_ADDR_I]], align 81874// BE-PWR9-NEXT: [[SUB_I:%.*]] = sub i64 16, [[TMP2]]1875// BE-PWR9-NEXT: [[CONV_I:%.*]] = trunc i64 [[SUB_I]] to i81876// BE-PWR9-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr null, i8 [[CONV_I]]1877// BE-PWR9-NEXT: [[TMP4:%.*]] = call <16 x i8> @llvm.ppc.altivec.lvsl(ptr [[TMP3]])1878// BE-PWR9-NEXT: store <16 x i8> [[TMP4]], ptr [[__MASK_I]], align 161879// BE-PWR9-NEXT: [[TMP5:%.*]] = load <16 x i8>, ptr [[__A_ADDR_I]], align 161880// BE-PWR9-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x i32>1881// BE-PWR9-NEXT: [[TMP7:%.*]] = load <16 x i8>, ptr [[__A_ADDR_I]], align 161882// BE-PWR9-NEXT: [[TMP8:%.*]] = bitcast <16 x i8> [[TMP7]] to <4 x i32>1883// BE-PWR9-NEXT: [[TMP9:%.*]] = load <16 x i8>, ptr [[__MASK_I]], align 161884// BE-PWR9-NEXT: [[TMP10:%.*]] = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> [[TMP6]], <4 x i32> [[TMP8]], <16 x i8> [[TMP9]])1885// BE-PWR9-NEXT: [[TMP11:%.*]] = bitcast <4 x i32> [[TMP10]] to <16 x i8>1886// BE-PWR9-NEXT: store <16 x i8> [[TMP11]], ptr [[__RES_I]], align 161887// BE-PWR9-NEXT: [[TMP12:%.*]] = load <16 x i8>, ptr [[__RES_I]], align 161888// BE-PWR9-NEXT: [[TMP13:%.*]] = bitcast <16 x i8> [[TMP12]] to <4 x i32>1889// BE-PWR9-NEXT: [[TMP14:%.*]] = load ptr, ptr [[__B_ADDR_I]], align 81890// BE-PWR9-NEXT: [[TMP15:%.*]] = load i64, ptr [[__C_ADDR_I]], align 81891// BE-PWR9-NEXT: [[SHL_I:%.*]] = shl i64 [[TMP15]], 561892// BE-PWR9-NEXT: call void @llvm.ppc.vsx.stxvll(<4 x i32> [[TMP13]], ptr [[TMP14]], i64 [[SHL_I]])1893// BE-PWR9-NEXT: ret void1894//1895// LE-PWR9-LABEL: @test_strmb13(1896// LE-PWR9-NEXT: entry:1897// LE-PWR9-NEXT: [[__A_ADDR_I:%.*]] = alloca <16 x i8>, align 161898// LE-PWR9-NEXT: [[__B_ADDR_I:%.*]] = alloca ptr, align 81899// LE-PWR9-NEXT: [[__C_ADDR_I:%.*]] = alloca i64, align 81900// LE-PWR9-NEXT: [[__MASK_I:%.*]] = alloca <16 x i8>, align 161901// LE-PWR9-NEXT: [[__RES_I:%.*]] = alloca <16 x i8>, align 161902// LE-PWR9-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 81903// LE-PWR9-NEXT: [[DATA_ADDR:%.*]] = alloca <16 x i8>, align 161904// LE-PWR9-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 81905// LE-PWR9-NEXT: store <16 x i8> [[DATA:%.*]], ptr [[DATA_ADDR]], align 161906// LE-PWR9-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr [[DATA_ADDR]], align 161907// LE-PWR9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[PTR_ADDR]], align 81908// LE-PWR9-NEXT: store <16 x i8> [[TMP0]], ptr [[__A_ADDR_I]], align 161909// LE-PWR9-NEXT: store ptr [[TMP1]], ptr [[__B_ADDR_I]], align 81910// LE-PWR9-NEXT: store i64 13, ptr [[__C_ADDR_I]], align 81911// LE-PWR9-NEXT: [[TMP2:%.*]] = load i64, ptr [[__C_ADDR_I]], align 81912// LE-PWR9-NEXT: [[SUB_I:%.*]] = sub i64 16, [[TMP2]]1913// LE-PWR9-NEXT: [[CONV_I:%.*]] = trunc i64 [[SUB_I]] to i81914// LE-PWR9-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr null, i8 [[CONV_I]]1915// LE-PWR9-NEXT: [[TMP4:%.*]] = call <16 x i8> @llvm.ppc.altivec.lvsl(ptr [[TMP3]])1916// LE-PWR9-NEXT: store <16 x i8> [[TMP4]], ptr [[__MASK_I]], align 161917// LE-PWR9-NEXT: [[TMP5:%.*]] = load <16 x i8>, ptr [[__A_ADDR_I]], align 161918// LE-PWR9-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x i32>1919// LE-PWR9-NEXT: [[TMP7:%.*]] = load <16 x i8>, ptr [[__A_ADDR_I]], align 161920// LE-PWR9-NEXT: [[TMP8:%.*]] = bitcast <16 x i8> [[TMP7]] to <4 x i32>1921// LE-PWR9-NEXT: [[TMP9:%.*]] = load <16 x i8>, ptr [[__MASK_I]], align 161922// LE-PWR9-NEXT: [[TMP10:%.*]] = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> [[TMP6]], <4 x i32> [[TMP8]], <16 x i8> [[TMP9]])1923// LE-PWR9-NEXT: [[TMP11:%.*]] = bitcast <4 x i32> [[TMP10]] to <16 x i8>1924// LE-PWR9-NEXT: store <16 x i8> [[TMP11]], ptr [[__RES_I]], align 161925// LE-PWR9-NEXT: [[TMP12:%.*]] = load <16 x i8>, ptr [[__RES_I]], align 161926// LE-PWR9-NEXT: [[TMP13:%.*]] = bitcast <16 x i8> [[TMP12]] to <4 x i32>1927// LE-PWR9-NEXT: [[TMP14:%.*]] = load ptr, ptr [[__B_ADDR_I]], align 81928// LE-PWR9-NEXT: [[TMP15:%.*]] = load i64, ptr [[__C_ADDR_I]], align 81929// LE-PWR9-NEXT: [[SHL_I:%.*]] = shl i64 [[TMP15]], 561930// LE-PWR9-NEXT: call void @llvm.ppc.vsx.stxvll(<4 x i32> [[TMP13]], ptr [[TMP14]], i64 [[SHL_I]])1931// LE-PWR9-NEXT: ret void1932//1933// BE32-PWR9-LABEL: @test_strmb13(1934// BE32-PWR9-NEXT: entry:1935// BE32-PWR9-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 41936// BE32-PWR9-NEXT: [[DATA_ADDR:%.*]] = alloca <16 x i8>, align 161937// BE32-PWR9-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 41938// BE32-PWR9-NEXT: store <16 x i8> [[DATA:%.*]], ptr [[DATA_ADDR]], align 161939// BE32-PWR9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 41940// BE32-PWR9-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr [[DATA_ADDR]], align 161941// BE32-PWR9-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>1942// BE32-PWR9-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr [[TMP0]], i64 51943// BE32-PWR9-NEXT: [[TMP5:%.*]] = extractelement <2 x i64> [[TMP2]], i64 11944// BE32-PWR9-NEXT: store i64 [[TMP5]], ptr [[TMP3]], align 11945// BE32-PWR9-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>1946// BE32-PWR9-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr [[TMP0]], i64 11947// BE32-PWR9-NEXT: [[TMP9:%.*]] = extractelement <4 x i32> [[TMP6]], i64 11948// BE32-PWR9-NEXT: store i32 [[TMP9]], ptr [[TMP7]], align 11949// BE32-PWR9-NEXT: [[TMP10:%.*]] = getelementptr i8, ptr [[TMP0]], i64 01950// BE32-PWR9-NEXT: [[TMP11:%.*]] = extractelement <16 x i8> [[TMP1]], i64 31951// BE32-PWR9-NEXT: store i8 [[TMP11]], ptr [[TMP10]], align 11952// BE32-PWR9-NEXT: ret void1953//1954void test_strmb13(char *ptr, vector unsigned char data) {1955 __vec_strmb(ptr, 13, data);1956}1957 1958// BE-PWR8-LABEL: @test_strmb14(1959// BE-PWR8-NEXT: entry:1960// BE-PWR8-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 81961// BE-PWR8-NEXT: [[DATA_ADDR:%.*]] = alloca <16 x i8>, align 161962// BE-PWR8-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 81963// BE-PWR8-NEXT: store <16 x i8> [[DATA:%.*]], ptr [[DATA_ADDR]], align 161964// BE-PWR8-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 81965// BE-PWR8-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr [[DATA_ADDR]], align 161966// BE-PWR8-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>1967// BE-PWR8-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr [[TMP0]], i64 61968// BE-PWR8-NEXT: [[TMP5:%.*]] = extractelement <2 x i64> [[TMP2]], i64 11969// BE-PWR8-NEXT: store i64 [[TMP5]], ptr [[TMP3]], align 11970// BE-PWR8-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>1971// BE-PWR8-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr [[TMP0]], i64 21972// BE-PWR8-NEXT: [[TMP9:%.*]] = extractelement <4 x i32> [[TMP6]], i64 11973// BE-PWR8-NEXT: store i32 [[TMP9]], ptr [[TMP7]], align 11974// BE-PWR8-NEXT: [[TMP10:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>1975// BE-PWR8-NEXT: [[TMP11:%.*]] = getelementptr i8, ptr [[TMP0]], i64 01976// BE-PWR8-NEXT: [[TMP13:%.*]] = extractelement <8 x i16> [[TMP10]], i64 11977// BE-PWR8-NEXT: store i16 [[TMP13]], ptr [[TMP11]], align 11978// BE-PWR8-NEXT: ret void1979//1980// LE-PWR8-LABEL: @test_strmb14(1981// LE-PWR8-NEXT: entry:1982// LE-PWR8-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 81983// LE-PWR8-NEXT: [[DATA_ADDR:%.*]] = alloca <16 x i8>, align 161984// LE-PWR8-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 81985// LE-PWR8-NEXT: store <16 x i8> [[DATA:%.*]], ptr [[DATA_ADDR]], align 161986// LE-PWR8-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 81987// LE-PWR8-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr [[DATA_ADDR]], align 161988// LE-PWR8-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>1989// LE-PWR8-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr [[TMP0]], i64 61990// LE-PWR8-NEXT: [[TMP5:%.*]] = extractelement <2 x i64> [[TMP2]], i64 01991// LE-PWR8-NEXT: [[TMP6:%.*]] = call i64 @llvm.bswap.i64(i64 [[TMP5]])1992// LE-PWR8-NEXT: store i64 [[TMP6]], ptr [[TMP3]], align 11993// LE-PWR8-NEXT: [[TMP7:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>1994// LE-PWR8-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[TMP0]], i64 21995// LE-PWR8-NEXT: [[TMP10:%.*]] = extractelement <4 x i32> [[TMP7]], i64 21996// LE-PWR8-NEXT: [[TMP11:%.*]] = call i32 @llvm.bswap.i32(i32 [[TMP10]])1997// LE-PWR8-NEXT: store i32 [[TMP11]], ptr [[TMP8]], align 11998// LE-PWR8-NEXT: [[TMP12:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>1999// LE-PWR8-NEXT: [[TMP13:%.*]] = getelementptr i8, ptr [[TMP0]], i64 02000// LE-PWR8-NEXT: [[TMP15:%.*]] = extractelement <8 x i16> [[TMP12]], i64 62001// LE-PWR8-NEXT: [[TMP16:%.*]] = call i16 @llvm.bswap.i16(i16 [[TMP15]])2002// LE-PWR8-NEXT: store i16 [[TMP16]], ptr [[TMP13]], align 12003// LE-PWR8-NEXT: ret void2004//2005// BE-PWR9-LABEL: @test_strmb14(2006// BE-PWR9-NEXT: entry:2007// BE-PWR9-NEXT: [[__A_ADDR_I:%.*]] = alloca <16 x i8>, align 162008// BE-PWR9-NEXT: [[__B_ADDR_I:%.*]] = alloca ptr, align 82009// BE-PWR9-NEXT: [[__C_ADDR_I:%.*]] = alloca i64, align 82010// BE-PWR9-NEXT: [[__MASK_I:%.*]] = alloca <16 x i8>, align 162011// BE-PWR9-NEXT: [[__RES_I:%.*]] = alloca <16 x i8>, align 162012// BE-PWR9-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 82013// BE-PWR9-NEXT: [[DATA_ADDR:%.*]] = alloca <16 x i8>, align 162014// BE-PWR9-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 82015// BE-PWR9-NEXT: store <16 x i8> [[DATA:%.*]], ptr [[DATA_ADDR]], align 162016// BE-PWR9-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr [[DATA_ADDR]], align 162017// BE-PWR9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[PTR_ADDR]], align 82018// BE-PWR9-NEXT: store <16 x i8> [[TMP0]], ptr [[__A_ADDR_I]], align 162019// BE-PWR9-NEXT: store ptr [[TMP1]], ptr [[__B_ADDR_I]], align 82020// BE-PWR9-NEXT: store i64 14, ptr [[__C_ADDR_I]], align 82021// BE-PWR9-NEXT: [[TMP2:%.*]] = load i64, ptr [[__C_ADDR_I]], align 82022// BE-PWR9-NEXT: [[SUB_I:%.*]] = sub i64 16, [[TMP2]]2023// BE-PWR9-NEXT: [[CONV_I:%.*]] = trunc i64 [[SUB_I]] to i82024// BE-PWR9-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr null, i8 [[CONV_I]]2025// BE-PWR9-NEXT: [[TMP4:%.*]] = call <16 x i8> @llvm.ppc.altivec.lvsl(ptr [[TMP3]])2026// BE-PWR9-NEXT: store <16 x i8> [[TMP4]], ptr [[__MASK_I]], align 162027// BE-PWR9-NEXT: [[TMP5:%.*]] = load <16 x i8>, ptr [[__A_ADDR_I]], align 162028// BE-PWR9-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x i32>2029// BE-PWR9-NEXT: [[TMP7:%.*]] = load <16 x i8>, ptr [[__A_ADDR_I]], align 162030// BE-PWR9-NEXT: [[TMP8:%.*]] = bitcast <16 x i8> [[TMP7]] to <4 x i32>2031// BE-PWR9-NEXT: [[TMP9:%.*]] = load <16 x i8>, ptr [[__MASK_I]], align 162032// BE-PWR9-NEXT: [[TMP10:%.*]] = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> [[TMP6]], <4 x i32> [[TMP8]], <16 x i8> [[TMP9]])2033// BE-PWR9-NEXT: [[TMP11:%.*]] = bitcast <4 x i32> [[TMP10]] to <16 x i8>2034// BE-PWR9-NEXT: store <16 x i8> [[TMP11]], ptr [[__RES_I]], align 162035// BE-PWR9-NEXT: [[TMP12:%.*]] = load <16 x i8>, ptr [[__RES_I]], align 162036// BE-PWR9-NEXT: [[TMP13:%.*]] = bitcast <16 x i8> [[TMP12]] to <4 x i32>2037// BE-PWR9-NEXT: [[TMP14:%.*]] = load ptr, ptr [[__B_ADDR_I]], align 82038// BE-PWR9-NEXT: [[TMP15:%.*]] = load i64, ptr [[__C_ADDR_I]], align 82039// BE-PWR9-NEXT: [[SHL_I:%.*]] = shl i64 [[TMP15]], 562040// BE-PWR9-NEXT: call void @llvm.ppc.vsx.stxvll(<4 x i32> [[TMP13]], ptr [[TMP14]], i64 [[SHL_I]])2041// BE-PWR9-NEXT: ret void2042//2043// LE-PWR9-LABEL: @test_strmb14(2044// LE-PWR9-NEXT: entry:2045// LE-PWR9-NEXT: [[__A_ADDR_I:%.*]] = alloca <16 x i8>, align 162046// LE-PWR9-NEXT: [[__B_ADDR_I:%.*]] = alloca ptr, align 82047// LE-PWR9-NEXT: [[__C_ADDR_I:%.*]] = alloca i64, align 82048// LE-PWR9-NEXT: [[__MASK_I:%.*]] = alloca <16 x i8>, align 162049// LE-PWR9-NEXT: [[__RES_I:%.*]] = alloca <16 x i8>, align 162050// LE-PWR9-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 82051// LE-PWR9-NEXT: [[DATA_ADDR:%.*]] = alloca <16 x i8>, align 162052// LE-PWR9-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 82053// LE-PWR9-NEXT: store <16 x i8> [[DATA:%.*]], ptr [[DATA_ADDR]], align 162054// LE-PWR9-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr [[DATA_ADDR]], align 162055// LE-PWR9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[PTR_ADDR]], align 82056// LE-PWR9-NEXT: store <16 x i8> [[TMP0]], ptr [[__A_ADDR_I]], align 162057// LE-PWR9-NEXT: store ptr [[TMP1]], ptr [[__B_ADDR_I]], align 82058// LE-PWR9-NEXT: store i64 14, ptr [[__C_ADDR_I]], align 82059// LE-PWR9-NEXT: [[TMP2:%.*]] = load i64, ptr [[__C_ADDR_I]], align 82060// LE-PWR9-NEXT: [[SUB_I:%.*]] = sub i64 16, [[TMP2]]2061// LE-PWR9-NEXT: [[CONV_I:%.*]] = trunc i64 [[SUB_I]] to i82062// LE-PWR9-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr null, i8 [[CONV_I]]2063// LE-PWR9-NEXT: [[TMP4:%.*]] = call <16 x i8> @llvm.ppc.altivec.lvsl(ptr [[TMP3]])2064// LE-PWR9-NEXT: store <16 x i8> [[TMP4]], ptr [[__MASK_I]], align 162065// LE-PWR9-NEXT: [[TMP5:%.*]] = load <16 x i8>, ptr [[__A_ADDR_I]], align 162066// LE-PWR9-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x i32>2067// LE-PWR9-NEXT: [[TMP7:%.*]] = load <16 x i8>, ptr [[__A_ADDR_I]], align 162068// LE-PWR9-NEXT: [[TMP8:%.*]] = bitcast <16 x i8> [[TMP7]] to <4 x i32>2069// LE-PWR9-NEXT: [[TMP9:%.*]] = load <16 x i8>, ptr [[__MASK_I]], align 162070// LE-PWR9-NEXT: [[TMP10:%.*]] = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> [[TMP6]], <4 x i32> [[TMP8]], <16 x i8> [[TMP9]])2071// LE-PWR9-NEXT: [[TMP11:%.*]] = bitcast <4 x i32> [[TMP10]] to <16 x i8>2072// LE-PWR9-NEXT: store <16 x i8> [[TMP11]], ptr [[__RES_I]], align 162073// LE-PWR9-NEXT: [[TMP12:%.*]] = load <16 x i8>, ptr [[__RES_I]], align 162074// LE-PWR9-NEXT: [[TMP13:%.*]] = bitcast <16 x i8> [[TMP12]] to <4 x i32>2075// LE-PWR9-NEXT: [[TMP14:%.*]] = load ptr, ptr [[__B_ADDR_I]], align 82076// LE-PWR9-NEXT: [[TMP15:%.*]] = load i64, ptr [[__C_ADDR_I]], align 82077// LE-PWR9-NEXT: [[SHL_I:%.*]] = shl i64 [[TMP15]], 562078// LE-PWR9-NEXT: call void @llvm.ppc.vsx.stxvll(<4 x i32> [[TMP13]], ptr [[TMP14]], i64 [[SHL_I]])2079// LE-PWR9-NEXT: ret void2080//2081// BE32-PWR9-LABEL: @test_strmb14(2082// BE32-PWR9-NEXT: entry:2083// BE32-PWR9-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 42084// BE32-PWR9-NEXT: [[DATA_ADDR:%.*]] = alloca <16 x i8>, align 162085// BE32-PWR9-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 42086// BE32-PWR9-NEXT: store <16 x i8> [[DATA:%.*]], ptr [[DATA_ADDR]], align 162087// BE32-PWR9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 42088// BE32-PWR9-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr [[DATA_ADDR]], align 162089// BE32-PWR9-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>2090// BE32-PWR9-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr [[TMP0]], i64 62091// BE32-PWR9-NEXT: [[TMP5:%.*]] = extractelement <2 x i64> [[TMP2]], i64 12092// BE32-PWR9-NEXT: store i64 [[TMP5]], ptr [[TMP3]], align 12093// BE32-PWR9-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>2094// BE32-PWR9-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr [[TMP0]], i64 22095// BE32-PWR9-NEXT: [[TMP9:%.*]] = extractelement <4 x i32> [[TMP6]], i64 12096// BE32-PWR9-NEXT: store i32 [[TMP9]], ptr [[TMP7]], align 12097// BE32-PWR9-NEXT: [[TMP10:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>2098// BE32-PWR9-NEXT: [[TMP11:%.*]] = getelementptr i8, ptr [[TMP0]], i64 02099// BE32-PWR9-NEXT: [[TMP13:%.*]] = extractelement <8 x i16> [[TMP10]], i64 12100// BE32-PWR9-NEXT: store i16 [[TMP13]], ptr [[TMP11]], align 12101// BE32-PWR9-NEXT: ret void2102//2103void test_strmb14(char *ptr, vector unsigned char data) {2104 __vec_strmb(ptr, 14, data);2105}2106 2107// BE-PWR8-LABEL: @test_strmb15(2108// BE-PWR8-NEXT: entry:2109// BE-PWR8-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 82110// BE-PWR8-NEXT: [[DATA_ADDR:%.*]] = alloca <16 x i8>, align 162111// BE-PWR8-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 82112// BE-PWR8-NEXT: store <16 x i8> [[DATA:%.*]], ptr [[DATA_ADDR]], align 162113// BE-PWR8-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 82114// BE-PWR8-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr [[DATA_ADDR]], align 162115// BE-PWR8-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>2116// BE-PWR8-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr [[TMP0]], i64 72117// BE-PWR8-NEXT: [[TMP5:%.*]] = extractelement <2 x i64> [[TMP2]], i64 12118// BE-PWR8-NEXT: store i64 [[TMP5]], ptr [[TMP3]], align 12119// BE-PWR8-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>2120// BE-PWR8-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr [[TMP0]], i64 32121// BE-PWR8-NEXT: [[TMP9:%.*]] = extractelement <4 x i32> [[TMP6]], i64 12122// BE-PWR8-NEXT: store i32 [[TMP9]], ptr [[TMP7]], align 12123// BE-PWR8-NEXT: [[TMP10:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>2124// BE-PWR8-NEXT: [[TMP11:%.*]] = getelementptr i8, ptr [[TMP0]], i64 12125// BE-PWR8-NEXT: [[TMP13:%.*]] = extractelement <8 x i16> [[TMP10]], i64 12126// BE-PWR8-NEXT: store i16 [[TMP13]], ptr [[TMP11]], align 12127// BE-PWR8-NEXT: [[TMP14:%.*]] = getelementptr i8, ptr [[TMP0]], i64 02128// BE-PWR8-NEXT: [[TMP15:%.*]] = extractelement <16 x i8> [[TMP1]], i64 12129// BE-PWR8-NEXT: store i8 [[TMP15]], ptr [[TMP14]], align 12130// BE-PWR8-NEXT: ret void2131//2132// LE-PWR8-LABEL: @test_strmb15(2133// LE-PWR8-NEXT: entry:2134// LE-PWR8-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 82135// LE-PWR8-NEXT: [[DATA_ADDR:%.*]] = alloca <16 x i8>, align 162136// LE-PWR8-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 82137// LE-PWR8-NEXT: store <16 x i8> [[DATA:%.*]], ptr [[DATA_ADDR]], align 162138// LE-PWR8-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 82139// LE-PWR8-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr [[DATA_ADDR]], align 162140// LE-PWR8-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>2141// LE-PWR8-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr [[TMP0]], i64 72142// LE-PWR8-NEXT: [[TMP5:%.*]] = extractelement <2 x i64> [[TMP2]], i64 02143// LE-PWR8-NEXT: [[TMP6:%.*]] = call i64 @llvm.bswap.i64(i64 [[TMP5]])2144// LE-PWR8-NEXT: store i64 [[TMP6]], ptr [[TMP3]], align 12145// LE-PWR8-NEXT: [[TMP7:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>2146// LE-PWR8-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[TMP0]], i64 32147// LE-PWR8-NEXT: [[TMP10:%.*]] = extractelement <4 x i32> [[TMP7]], i64 22148// LE-PWR8-NEXT: [[TMP11:%.*]] = call i32 @llvm.bswap.i32(i32 [[TMP10]])2149// LE-PWR8-NEXT: store i32 [[TMP11]], ptr [[TMP8]], align 12150// LE-PWR8-NEXT: [[TMP12:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>2151// LE-PWR8-NEXT: [[TMP13:%.*]] = getelementptr i8, ptr [[TMP0]], i64 12152// LE-PWR8-NEXT: [[TMP15:%.*]] = extractelement <8 x i16> [[TMP12]], i64 62153// LE-PWR8-NEXT: [[TMP16:%.*]] = call i16 @llvm.bswap.i16(i16 [[TMP15]])2154// LE-PWR8-NEXT: store i16 [[TMP16]], ptr [[TMP13]], align 12155// LE-PWR8-NEXT: [[TMP17:%.*]] = getelementptr i8, ptr [[TMP0]], i64 02156// LE-PWR8-NEXT: [[TMP18:%.*]] = extractelement <16 x i8> [[TMP1]], i64 142157// LE-PWR8-NEXT: store i8 [[TMP18]], ptr [[TMP17]], align 12158// LE-PWR8-NEXT: ret void2159//2160// BE-PWR9-LABEL: @test_strmb15(2161// BE-PWR9-NEXT: entry:2162// BE-PWR9-NEXT: [[__A_ADDR_I:%.*]] = alloca <16 x i8>, align 162163// BE-PWR9-NEXT: [[__B_ADDR_I:%.*]] = alloca ptr, align 82164// BE-PWR9-NEXT: [[__C_ADDR_I:%.*]] = alloca i64, align 82165// BE-PWR9-NEXT: [[__MASK_I:%.*]] = alloca <16 x i8>, align 162166// BE-PWR9-NEXT: [[__RES_I:%.*]] = alloca <16 x i8>, align 162167// BE-PWR9-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 82168// BE-PWR9-NEXT: [[DATA_ADDR:%.*]] = alloca <16 x i8>, align 162169// BE-PWR9-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 82170// BE-PWR9-NEXT: store <16 x i8> [[DATA:%.*]], ptr [[DATA_ADDR]], align 162171// BE-PWR9-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr [[DATA_ADDR]], align 162172// BE-PWR9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[PTR_ADDR]], align 82173// BE-PWR9-NEXT: store <16 x i8> [[TMP0]], ptr [[__A_ADDR_I]], align 162174// BE-PWR9-NEXT: store ptr [[TMP1]], ptr [[__B_ADDR_I]], align 82175// BE-PWR9-NEXT: store i64 15, ptr [[__C_ADDR_I]], align 82176// BE-PWR9-NEXT: [[TMP2:%.*]] = load i64, ptr [[__C_ADDR_I]], align 82177// BE-PWR9-NEXT: [[SUB_I:%.*]] = sub i64 16, [[TMP2]]2178// BE-PWR9-NEXT: [[CONV_I:%.*]] = trunc i64 [[SUB_I]] to i82179// BE-PWR9-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr null, i8 [[CONV_I]]2180// BE-PWR9-NEXT: [[TMP4:%.*]] = call <16 x i8> @llvm.ppc.altivec.lvsl(ptr [[TMP3]])2181// BE-PWR9-NEXT: store <16 x i8> [[TMP4]], ptr [[__MASK_I]], align 162182// BE-PWR9-NEXT: [[TMP5:%.*]] = load <16 x i8>, ptr [[__A_ADDR_I]], align 162183// BE-PWR9-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x i32>2184// BE-PWR9-NEXT: [[TMP7:%.*]] = load <16 x i8>, ptr [[__A_ADDR_I]], align 162185// BE-PWR9-NEXT: [[TMP8:%.*]] = bitcast <16 x i8> [[TMP7]] to <4 x i32>2186// BE-PWR9-NEXT: [[TMP9:%.*]] = load <16 x i8>, ptr [[__MASK_I]], align 162187// BE-PWR9-NEXT: [[TMP10:%.*]] = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> [[TMP6]], <4 x i32> [[TMP8]], <16 x i8> [[TMP9]])2188// BE-PWR9-NEXT: [[TMP11:%.*]] = bitcast <4 x i32> [[TMP10]] to <16 x i8>2189// BE-PWR9-NEXT: store <16 x i8> [[TMP11]], ptr [[__RES_I]], align 162190// BE-PWR9-NEXT: [[TMP12:%.*]] = load <16 x i8>, ptr [[__RES_I]], align 162191// BE-PWR9-NEXT: [[TMP13:%.*]] = bitcast <16 x i8> [[TMP12]] to <4 x i32>2192// BE-PWR9-NEXT: [[TMP14:%.*]] = load ptr, ptr [[__B_ADDR_I]], align 82193// BE-PWR9-NEXT: [[TMP15:%.*]] = load i64, ptr [[__C_ADDR_I]], align 82194// BE-PWR9-NEXT: [[SHL_I:%.*]] = shl i64 [[TMP15]], 562195// BE-PWR9-NEXT: call void @llvm.ppc.vsx.stxvll(<4 x i32> [[TMP13]], ptr [[TMP14]], i64 [[SHL_I]])2196// BE-PWR9-NEXT: ret void2197//2198// LE-PWR9-LABEL: @test_strmb15(2199// LE-PWR9-NEXT: entry:2200// LE-PWR9-NEXT: [[__A_ADDR_I:%.*]] = alloca <16 x i8>, align 162201// LE-PWR9-NEXT: [[__B_ADDR_I:%.*]] = alloca ptr, align 82202// LE-PWR9-NEXT: [[__C_ADDR_I:%.*]] = alloca i64, align 82203// LE-PWR9-NEXT: [[__MASK_I:%.*]] = alloca <16 x i8>, align 162204// LE-PWR9-NEXT: [[__RES_I:%.*]] = alloca <16 x i8>, align 162205// LE-PWR9-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 82206// LE-PWR9-NEXT: [[DATA_ADDR:%.*]] = alloca <16 x i8>, align 162207// LE-PWR9-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 82208// LE-PWR9-NEXT: store <16 x i8> [[DATA:%.*]], ptr [[DATA_ADDR]], align 162209// LE-PWR9-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr [[DATA_ADDR]], align 162210// LE-PWR9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[PTR_ADDR]], align 82211// LE-PWR9-NEXT: store <16 x i8> [[TMP0]], ptr [[__A_ADDR_I]], align 162212// LE-PWR9-NEXT: store ptr [[TMP1]], ptr [[__B_ADDR_I]], align 82213// LE-PWR9-NEXT: store i64 15, ptr [[__C_ADDR_I]], align 82214// LE-PWR9-NEXT: [[TMP2:%.*]] = load i64, ptr [[__C_ADDR_I]], align 82215// LE-PWR9-NEXT: [[SUB_I:%.*]] = sub i64 16, [[TMP2]]2216// LE-PWR9-NEXT: [[CONV_I:%.*]] = trunc i64 [[SUB_I]] to i82217// LE-PWR9-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr null, i8 [[CONV_I]]2218// LE-PWR9-NEXT: [[TMP4:%.*]] = call <16 x i8> @llvm.ppc.altivec.lvsl(ptr [[TMP3]])2219// LE-PWR9-NEXT: store <16 x i8> [[TMP4]], ptr [[__MASK_I]], align 162220// LE-PWR9-NEXT: [[TMP5:%.*]] = load <16 x i8>, ptr [[__A_ADDR_I]], align 162221// LE-PWR9-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x i32>2222// LE-PWR9-NEXT: [[TMP7:%.*]] = load <16 x i8>, ptr [[__A_ADDR_I]], align 162223// LE-PWR9-NEXT: [[TMP8:%.*]] = bitcast <16 x i8> [[TMP7]] to <4 x i32>2224// LE-PWR9-NEXT: [[TMP9:%.*]] = load <16 x i8>, ptr [[__MASK_I]], align 162225// LE-PWR9-NEXT: [[TMP10:%.*]] = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> [[TMP6]], <4 x i32> [[TMP8]], <16 x i8> [[TMP9]])2226// LE-PWR9-NEXT: [[TMP11:%.*]] = bitcast <4 x i32> [[TMP10]] to <16 x i8>2227// LE-PWR9-NEXT: store <16 x i8> [[TMP11]], ptr [[__RES_I]], align 162228// LE-PWR9-NEXT: [[TMP12:%.*]] = load <16 x i8>, ptr [[__RES_I]], align 162229// LE-PWR9-NEXT: [[TMP13:%.*]] = bitcast <16 x i8> [[TMP12]] to <4 x i32>2230// LE-PWR9-NEXT: [[TMP14:%.*]] = load ptr, ptr [[__B_ADDR_I]], align 82231// LE-PWR9-NEXT: [[TMP15:%.*]] = load i64, ptr [[__C_ADDR_I]], align 82232// LE-PWR9-NEXT: [[SHL_I:%.*]] = shl i64 [[TMP15]], 562233// LE-PWR9-NEXT: call void @llvm.ppc.vsx.stxvll(<4 x i32> [[TMP13]], ptr [[TMP14]], i64 [[SHL_I]])2234// LE-PWR9-NEXT: ret void2235//2236// BE32-PWR9-LABEL: @test_strmb15(2237// BE32-PWR9-NEXT: entry:2238// BE32-PWR9-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 42239// BE32-PWR9-NEXT: [[DATA_ADDR:%.*]] = alloca <16 x i8>, align 162240// BE32-PWR9-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 42241// BE32-PWR9-NEXT: store <16 x i8> [[DATA:%.*]], ptr [[DATA_ADDR]], align 162242// BE32-PWR9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 42243// BE32-PWR9-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr [[DATA_ADDR]], align 162244// BE32-PWR9-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>2245// BE32-PWR9-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr [[TMP0]], i64 72246// BE32-PWR9-NEXT: [[TMP5:%.*]] = extractelement <2 x i64> [[TMP2]], i64 12247// BE32-PWR9-NEXT: store i64 [[TMP5]], ptr [[TMP3]], align 12248// BE32-PWR9-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>2249// BE32-PWR9-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr [[TMP0]], i64 32250// BE32-PWR9-NEXT: [[TMP9:%.*]] = extractelement <4 x i32> [[TMP6]], i64 12251// BE32-PWR9-NEXT: store i32 [[TMP9]], ptr [[TMP7]], align 12252// BE32-PWR9-NEXT: [[TMP10:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>2253// BE32-PWR9-NEXT: [[TMP11:%.*]] = getelementptr i8, ptr [[TMP0]], i64 12254// BE32-PWR9-NEXT: [[TMP13:%.*]] = extractelement <8 x i16> [[TMP10]], i64 12255// BE32-PWR9-NEXT: store i16 [[TMP13]], ptr [[TMP11]], align 12256// BE32-PWR9-NEXT: [[TMP14:%.*]] = getelementptr i8, ptr [[TMP0]], i64 02257// BE32-PWR9-NEXT: [[TMP15:%.*]] = extractelement <16 x i8> [[TMP1]], i64 12258// BE32-PWR9-NEXT: store i8 [[TMP15]], ptr [[TMP14]], align 12259// BE32-PWR9-NEXT: ret void2260//2261void test_strmb15(char *ptr, vector unsigned char data) {2262 __vec_strmb(ptr, 15, data);2263}2264// BE-PWR8-LABEL: @test_ldrmb16(2265// BE-PWR8-NEXT: entry:2266// BE-PWR8-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 82267// BE-PWR8-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 82268// BE-PWR8-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 82269// BE-PWR8-NEXT: [[TMP2:%.*]] = load <16 x i8>, ptr [[TMP0]], align 12270// BE-PWR8-NEXT: ret <16 x i8> [[TMP2]]2271//2272// LE-PWR8-LABEL: @test_ldrmb16(2273// LE-PWR8-NEXT: entry:2274// LE-PWR8-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 82275// LE-PWR8-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 82276// LE-PWR8-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 82277// LE-PWR8-NEXT: [[TMP2:%.*]] = load <16 x i8>, ptr [[TMP0]], align 12278// LE-PWR8-NEXT: [[TMP3:%.*]] = shufflevector <16 x i8> [[TMP2]], <16 x i8> [[TMP2]], <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>2279// LE-PWR8-NEXT: ret <16 x i8> [[TMP3]]2280//2281// BE-PWR9-LABEL: @test_ldrmb16(2282// BE-PWR9-NEXT: entry:2283// BE-PWR9-NEXT: [[__A_ADDR_I:%.*]] = alloca ptr, align 82284// BE-PWR9-NEXT: [[__B_ADDR_I:%.*]] = alloca i64, align 82285// BE-PWR9-NEXT: [[__RES_I:%.*]] = alloca <16 x i8>, align 162286// BE-PWR9-NEXT: [[__MASK_I:%.*]] = alloca <16 x i8>, align 162287// BE-PWR9-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 82288// BE-PWR9-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 82289// BE-PWR9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 82290// BE-PWR9-NEXT: store ptr [[TMP0]], ptr [[__A_ADDR_I]], align 82291// BE-PWR9-NEXT: store i64 16, ptr [[__B_ADDR_I]], align 82292// BE-PWR9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__A_ADDR_I]], align 82293// BE-PWR9-NEXT: [[TMP2:%.*]] = load i64, ptr [[__B_ADDR_I]], align 82294// BE-PWR9-NEXT: [[SHL_I:%.*]] = shl i64 [[TMP2]], 562295// BE-PWR9-NEXT: [[TMP3:%.*]] = call <4 x i32> @llvm.ppc.vsx.lxvll(ptr [[TMP1]], i64 [[SHL_I]])2296// BE-PWR9-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP3]] to <16 x i8>2297// BE-PWR9-NEXT: store <16 x i8> [[TMP4]], ptr [[__RES_I]], align 162298// BE-PWR9-NEXT: [[TMP5:%.*]] = load i64, ptr [[__B_ADDR_I]], align 82299// BE-PWR9-NEXT: [[SUB_I:%.*]] = sub i64 16, [[TMP5]]2300// BE-PWR9-NEXT: [[CONV_I:%.*]] = trunc i64 [[SUB_I]] to i82301// BE-PWR9-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr null, i8 [[CONV_I]]2302// BE-PWR9-NEXT: [[TMP7:%.*]] = call <16 x i8> @llvm.ppc.altivec.lvsr(ptr [[TMP6]])2303// BE-PWR9-NEXT: store <16 x i8> [[TMP7]], ptr [[__MASK_I]], align 162304// BE-PWR9-NEXT: [[TMP8:%.*]] = load <16 x i8>, ptr [[__RES_I]], align 162305// BE-PWR9-NEXT: [[TMP9:%.*]] = bitcast <16 x i8> [[TMP8]] to <4 x i32>2306// BE-PWR9-NEXT: [[TMP10:%.*]] = load <16 x i8>, ptr [[__RES_I]], align 162307// BE-PWR9-NEXT: [[TMP11:%.*]] = bitcast <16 x i8> [[TMP10]] to <4 x i32>2308// BE-PWR9-NEXT: [[TMP12:%.*]] = load <16 x i8>, ptr [[__MASK_I]], align 162309// BE-PWR9-NEXT: [[TMP13:%.*]] = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> [[TMP9]], <4 x i32> [[TMP11]], <16 x i8> [[TMP12]])2310// BE-PWR9-NEXT: [[TMP14:%.*]] = bitcast <4 x i32> [[TMP13]] to <16 x i8>2311// BE-PWR9-NEXT: ret <16 x i8> [[TMP14]]2312//2313// LE-PWR9-LABEL: @test_ldrmb16(2314// LE-PWR9-NEXT: entry:2315// LE-PWR9-NEXT: [[__A_ADDR_I:%.*]] = alloca ptr, align 82316// LE-PWR9-NEXT: [[__B_ADDR_I:%.*]] = alloca i64, align 82317// LE-PWR9-NEXT: [[__RES_I:%.*]] = alloca <16 x i8>, align 162318// LE-PWR9-NEXT: [[__MASK_I:%.*]] = alloca <16 x i8>, align 162319// LE-PWR9-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 82320// LE-PWR9-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 82321// LE-PWR9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 82322// LE-PWR9-NEXT: store ptr [[TMP0]], ptr [[__A_ADDR_I]], align 82323// LE-PWR9-NEXT: store i64 16, ptr [[__B_ADDR_I]], align 82324// LE-PWR9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__A_ADDR_I]], align 82325// LE-PWR9-NEXT: [[TMP2:%.*]] = load i64, ptr [[__B_ADDR_I]], align 82326// LE-PWR9-NEXT: [[SHL_I:%.*]] = shl i64 [[TMP2]], 562327// LE-PWR9-NEXT: [[TMP3:%.*]] = call <4 x i32> @llvm.ppc.vsx.lxvll(ptr [[TMP1]], i64 [[SHL_I]])2328// LE-PWR9-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP3]] to <16 x i8>2329// LE-PWR9-NEXT: store <16 x i8> [[TMP4]], ptr [[__RES_I]], align 162330// LE-PWR9-NEXT: [[TMP5:%.*]] = load i64, ptr [[__B_ADDR_I]], align 82331// LE-PWR9-NEXT: [[SUB_I:%.*]] = sub i64 16, [[TMP5]]2332// LE-PWR9-NEXT: [[CONV_I:%.*]] = trunc i64 [[SUB_I]] to i82333// LE-PWR9-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr null, i8 [[CONV_I]]2334// LE-PWR9-NEXT: [[TMP7:%.*]] = call <16 x i8> @llvm.ppc.altivec.lvsr(ptr [[TMP6]])2335// LE-PWR9-NEXT: store <16 x i8> [[TMP7]], ptr [[__MASK_I]], align 162336// LE-PWR9-NEXT: [[TMP8:%.*]] = load <16 x i8>, ptr [[__RES_I]], align 162337// LE-PWR9-NEXT: [[TMP9:%.*]] = bitcast <16 x i8> [[TMP8]] to <4 x i32>2338// LE-PWR9-NEXT: [[TMP10:%.*]] = load <16 x i8>, ptr [[__RES_I]], align 162339// LE-PWR9-NEXT: [[TMP11:%.*]] = bitcast <16 x i8> [[TMP10]] to <4 x i32>2340// LE-PWR9-NEXT: [[TMP12:%.*]] = load <16 x i8>, ptr [[__MASK_I]], align 162341// LE-PWR9-NEXT: [[TMP13:%.*]] = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> [[TMP9]], <4 x i32> [[TMP11]], <16 x i8> [[TMP12]])2342// LE-PWR9-NEXT: [[TMP14:%.*]] = bitcast <4 x i32> [[TMP13]] to <16 x i8>2343// LE-PWR9-NEXT: ret <16 x i8> [[TMP14]]2344//2345// BE32-PWR9-LABEL: @test_ldrmb16(2346// BE32-PWR9-NEXT: entry:2347// BE32-PWR9-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 42348// BE32-PWR9-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 42349// BE32-PWR9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 42350// BE32-PWR9-NEXT: [[TMP2:%.*]] = load <16 x i8>, ptr [[TMP0]], align 12351// BE32-PWR9-NEXT: ret <16 x i8> [[TMP2]]2352//2353vector unsigned char test_ldrmb16(char *ptr) { return __vec_ldrmb(ptr, 16); }2354 2355// BE-PWR8-LABEL: @test_strmb16(2356// BE-PWR8-NEXT: entry:2357// BE-PWR8-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 82358// BE-PWR8-NEXT: [[DATA_ADDR:%.*]] = alloca <16 x i8>, align 162359// BE-PWR8-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 82360// BE-PWR8-NEXT: store <16 x i8> [[DATA:%.*]], ptr [[DATA_ADDR]], align 162361// BE-PWR8-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 82362// BE-PWR8-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr [[DATA_ADDR]], align 162363// BE-PWR8-NEXT: store <16 x i8> [[TMP1]], ptr [[TMP0]], align 12364// BE-PWR8-NEXT: ret void2365//2366// LE-PWR8-LABEL: @test_strmb16(2367// LE-PWR8-NEXT: entry:2368// LE-PWR8-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 82369// LE-PWR8-NEXT: [[DATA_ADDR:%.*]] = alloca <16 x i8>, align 162370// LE-PWR8-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 82371// LE-PWR8-NEXT: store <16 x i8> [[DATA:%.*]], ptr [[DATA_ADDR]], align 162372// LE-PWR8-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 82373// LE-PWR8-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr [[DATA_ADDR]], align 162374// LE-PWR8-NEXT: [[TMP3:%.*]] = shufflevector <16 x i8> [[TMP1]], <16 x i8> [[TMP1]], <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>2375// LE-PWR8-NEXT: store <16 x i8> [[TMP3]], ptr [[TMP0]], align 12376// LE-PWR8-NEXT: ret void2377//2378// BE-PWR9-LABEL: @test_strmb16(2379// BE-PWR9-NEXT: entry:2380// BE-PWR9-NEXT: [[__A_ADDR_I:%.*]] = alloca <16 x i8>, align 162381// BE-PWR9-NEXT: [[__B_ADDR_I:%.*]] = alloca ptr, align 82382// BE-PWR9-NEXT: [[__C_ADDR_I:%.*]] = alloca i64, align 82383// BE-PWR9-NEXT: [[__MASK_I:%.*]] = alloca <16 x i8>, align 162384// BE-PWR9-NEXT: [[__RES_I:%.*]] = alloca <16 x i8>, align 162385// BE-PWR9-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 82386// BE-PWR9-NEXT: [[DATA_ADDR:%.*]] = alloca <16 x i8>, align 162387// BE-PWR9-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 82388// BE-PWR9-NEXT: store <16 x i8> [[DATA:%.*]], ptr [[DATA_ADDR]], align 162389// BE-PWR9-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr [[DATA_ADDR]], align 162390// BE-PWR9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[PTR_ADDR]], align 82391// BE-PWR9-NEXT: store <16 x i8> [[TMP0]], ptr [[__A_ADDR_I]], align 162392// BE-PWR9-NEXT: store ptr [[TMP1]], ptr [[__B_ADDR_I]], align 82393// BE-PWR9-NEXT: store i64 16, ptr [[__C_ADDR_I]], align 82394// BE-PWR9-NEXT: [[TMP2:%.*]] = load i64, ptr [[__C_ADDR_I]], align 82395// BE-PWR9-NEXT: [[SUB_I:%.*]] = sub i64 16, [[TMP2]]2396// BE-PWR9-NEXT: [[CONV_I:%.*]] = trunc i64 [[SUB_I]] to i82397// BE-PWR9-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr null, i8 [[CONV_I]]2398// BE-PWR9-NEXT: [[TMP4:%.*]] = call <16 x i8> @llvm.ppc.altivec.lvsl(ptr [[TMP3]])2399// BE-PWR9-NEXT: store <16 x i8> [[TMP4]], ptr [[__MASK_I]], align 162400// BE-PWR9-NEXT: [[TMP5:%.*]] = load <16 x i8>, ptr [[__A_ADDR_I]], align 162401// BE-PWR9-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x i32>2402// BE-PWR9-NEXT: [[TMP7:%.*]] = load <16 x i8>, ptr [[__A_ADDR_I]], align 162403// BE-PWR9-NEXT: [[TMP8:%.*]] = bitcast <16 x i8> [[TMP7]] to <4 x i32>2404// BE-PWR9-NEXT: [[TMP9:%.*]] = load <16 x i8>, ptr [[__MASK_I]], align 162405// BE-PWR9-NEXT: [[TMP10:%.*]] = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> [[TMP6]], <4 x i32> [[TMP8]], <16 x i8> [[TMP9]])2406// BE-PWR9-NEXT: [[TMP11:%.*]] = bitcast <4 x i32> [[TMP10]] to <16 x i8>2407// BE-PWR9-NEXT: store <16 x i8> [[TMP11]], ptr [[__RES_I]], align 162408// BE-PWR9-NEXT: [[TMP12:%.*]] = load <16 x i8>, ptr [[__RES_I]], align 162409// BE-PWR9-NEXT: [[TMP13:%.*]] = bitcast <16 x i8> [[TMP12]] to <4 x i32>2410// BE-PWR9-NEXT: [[TMP14:%.*]] = load ptr, ptr [[__B_ADDR_I]], align 82411// BE-PWR9-NEXT: [[TMP15:%.*]] = load i64, ptr [[__C_ADDR_I]], align 82412// BE-PWR9-NEXT: [[SHL_I:%.*]] = shl i64 [[TMP15]], 562413// BE-PWR9-NEXT: call void @llvm.ppc.vsx.stxvll(<4 x i32> [[TMP13]], ptr [[TMP14]], i64 [[SHL_I]])2414// BE-PWR9-NEXT: ret void2415//2416// LE-PWR9-LABEL: @test_strmb16(2417// LE-PWR9-NEXT: entry:2418// LE-PWR9-NEXT: [[__A_ADDR_I:%.*]] = alloca <16 x i8>, align 162419// LE-PWR9-NEXT: [[__B_ADDR_I:%.*]] = alloca ptr, align 82420// LE-PWR9-NEXT: [[__C_ADDR_I:%.*]] = alloca i64, align 82421// LE-PWR9-NEXT: [[__MASK_I:%.*]] = alloca <16 x i8>, align 162422// LE-PWR9-NEXT: [[__RES_I:%.*]] = alloca <16 x i8>, align 162423// LE-PWR9-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 82424// LE-PWR9-NEXT: [[DATA_ADDR:%.*]] = alloca <16 x i8>, align 162425// LE-PWR9-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 82426// LE-PWR9-NEXT: store <16 x i8> [[DATA:%.*]], ptr [[DATA_ADDR]], align 162427// LE-PWR9-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr [[DATA_ADDR]], align 162428// LE-PWR9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[PTR_ADDR]], align 82429// LE-PWR9-NEXT: store <16 x i8> [[TMP0]], ptr [[__A_ADDR_I]], align 162430// LE-PWR9-NEXT: store ptr [[TMP1]], ptr [[__B_ADDR_I]], align 82431// LE-PWR9-NEXT: store i64 16, ptr [[__C_ADDR_I]], align 82432// LE-PWR9-NEXT: [[TMP2:%.*]] = load i64, ptr [[__C_ADDR_I]], align 82433// LE-PWR9-NEXT: [[SUB_I:%.*]] = sub i64 16, [[TMP2]]2434// LE-PWR9-NEXT: [[CONV_I:%.*]] = trunc i64 [[SUB_I]] to i82435// LE-PWR9-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr null, i8 [[CONV_I]]2436// LE-PWR9-NEXT: [[TMP4:%.*]] = call <16 x i8> @llvm.ppc.altivec.lvsl(ptr [[TMP3]])2437// LE-PWR9-NEXT: store <16 x i8> [[TMP4]], ptr [[__MASK_I]], align 162438// LE-PWR9-NEXT: [[TMP5:%.*]] = load <16 x i8>, ptr [[__A_ADDR_I]], align 162439// LE-PWR9-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x i32>2440// LE-PWR9-NEXT: [[TMP7:%.*]] = load <16 x i8>, ptr [[__A_ADDR_I]], align 162441// LE-PWR9-NEXT: [[TMP8:%.*]] = bitcast <16 x i8> [[TMP7]] to <4 x i32>2442// LE-PWR9-NEXT: [[TMP9:%.*]] = load <16 x i8>, ptr [[__MASK_I]], align 162443// LE-PWR9-NEXT: [[TMP10:%.*]] = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> [[TMP6]], <4 x i32> [[TMP8]], <16 x i8> [[TMP9]])2444// LE-PWR9-NEXT: [[TMP11:%.*]] = bitcast <4 x i32> [[TMP10]] to <16 x i8>2445// LE-PWR9-NEXT: store <16 x i8> [[TMP11]], ptr [[__RES_I]], align 162446// LE-PWR9-NEXT: [[TMP12:%.*]] = load <16 x i8>, ptr [[__RES_I]], align 162447// LE-PWR9-NEXT: [[TMP13:%.*]] = bitcast <16 x i8> [[TMP12]] to <4 x i32>2448// LE-PWR9-NEXT: [[TMP14:%.*]] = load ptr, ptr [[__B_ADDR_I]], align 82449// LE-PWR9-NEXT: [[TMP15:%.*]] = load i64, ptr [[__C_ADDR_I]], align 82450// LE-PWR9-NEXT: [[SHL_I:%.*]] = shl i64 [[TMP15]], 562451// LE-PWR9-NEXT: call void @llvm.ppc.vsx.stxvll(<4 x i32> [[TMP13]], ptr [[TMP14]], i64 [[SHL_I]])2452// LE-PWR9-NEXT: ret void2453//2454// BE32-PWR9-LABEL: @test_strmb16(2455// BE32-PWR9-NEXT: entry:2456// BE32-PWR9-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 42457// BE32-PWR9-NEXT: [[DATA_ADDR:%.*]] = alloca <16 x i8>, align 162458// BE32-PWR9-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 42459// BE32-PWR9-NEXT: store <16 x i8> [[DATA:%.*]], ptr [[DATA_ADDR]], align 162460// BE32-PWR9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 42461// BE32-PWR9-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr [[DATA_ADDR]], align 162462// BE32-PWR9-NEXT: store <16 x i8> [[TMP1]], ptr [[TMP0]], align 12463// BE32-PWR9-NEXT: ret void2464//2465void test_strmb16(char *ptr, vector unsigned char data) {2466 __vec_strmb(ptr, 16, data);2467}2468