1271 lines · c
1// REQUIRES: powerpc-registered-target2// RUN: %clang_cc1 -target-feature +altivec -target-feature +power9-vector \3// RUN: -triple powerpc64-unknown-unknown -emit-llvm %s \4// RUN: -flax-vector-conversions=integer \5// RUN: -o - | FileCheck %s -check-prefix=CHECK-BE6 7// RUN: %clang_cc1 -target-feature +altivec -target-feature +power9-vector \8// RUN: -triple powerpc64le-unknown-unknown -emit-llvm %s \9// RUN: -flax-vector-conversions=integer \10// RUN: -o - | FileCheck %s11 12// RUN: %clang_cc1 -flax-vector-conversions=none -target-feature +altivec -target-feature +power9-vector \13// RUN: -triple powerpc64-unknown-unknown -emit-llvm %s \14// RUN: -o - | FileCheck %s -check-prefix=CHECK-BE15 16#include <altivec.h>17 18vector signed char vsca, vscb;19vector unsigned char vuca, vucb;20vector bool char vbca, vbcb;21vector signed short vssa, vssb;22vector unsigned short vusa, vusb;23vector bool short vbsa, vbsb;24vector signed int vsia, vsib;25vector unsigned int vuia, vuib;26vector bool int vbia, vbib;27vector signed long long vsla, vslb;28vector unsigned long long vula, vulb;29vector bool long long vbla, vblb;30vector float vfa, vfb;31vector double vda, vdb;32vector unsigned __int128 vui128a, vui128b;33vector signed __int128 vsi128a, vsi128b;34 35float f[4] = { 23.4f, 56.7f, 89.0f, 12.3f };36double d[2] = { 23.4, 56.7 };37signed char sc[16] = { -8, 9, -10, 11, -12, 13, -14, 15,38 -0, 1, -2, 3, -4, 5, -6, 7 };39unsigned char uc[16] = { 8, 9, 10, 11, 12, 13, 14, 15,40 0, 1, 2, 3, 4, 5, 6, 7 };41signed short ss[8] = { -1, 2, -3, 4, -5, 6, -7, 8 };42unsigned short us[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };43signed int si[4] = { -1, 2, -3, 4 };44unsigned int ui[4] = { 0, 1, 2, 3 };45signed long sl[2] = { -1L, 2L };46unsigned long ul[2] = { 1L, 2L };47signed long long sll[2] = { 1LL, 1LL };48unsigned long long ull[2] = { -1LL, 1LL };49signed __int128 sint128[1] = { -1 };50unsigned __int128 uint128[1] = { 1 };51 52unsigned test1(void) {53// CHECK-BE: @llvm.ppc.altivec.vcmpequb(<16 x i8>54// CHECK-BE: @llvm.ctlz.v2i64(<2 x i64>55// CHECK-BE: extractelement <2 x i64>56// CHECK-BE: icmp eq i64 {{.*}}, 6457// CHECK-BE: extractelement <2 x i64>58// CHECK-BE: add i64 {{.*}}, 6459// CHECK-BE: lshr i64 {{.*}}, 360// CHECK: @llvm.ppc.altivec.vcmpequb(<16 x i8>61// CHECK: @llvm.cttz.v2i64(<2 x i64>62// CHECK: extractelement <2 x i64>63// CHECK: icmp eq i64 {{.*}}, 6464// CHECK: extractelement <2 x i64>65// CHECK: add i64 {{.*}}, 6466// CHECK: lshr i64 {{.*}}, 367 return vec_first_match_index (vsca, vscb);68}69unsigned test2(void) {70// CHECK-BE: @llvm.ppc.altivec.vcmpequb(<16 x i8>71// CHECK-BE: @llvm.ctlz.v2i64(<2 x i64>72// CHECK-BE: extractelement <2 x i64>73// CHECK-BE: icmp eq i64 {{.*}}, 6474// CHECK-BE: extractelement <2 x i64>75// CHECK-BE: add i64 {{.*}}, 6476// CHECK-BE: lshr i64 {{.*}}, 377// CHECK: @llvm.ppc.altivec.vcmpequb(<16 x i8>78// CHECK: @llvm.cttz.v2i64(<2 x i64>79// CHECK: extractelement <2 x i64>80// CHECK: icmp eq i64 {{.*}}, 6481// CHECK: extractelement <2 x i64>82// CHECK: add i64 {{.*}}, 6483// CHECK: lshr i64 {{.*}}, 384 return vec_first_match_index (vuca, vucb);85}86unsigned test3(void) {87// CHECK-BE: @llvm.ppc.altivec.vcmpequw(<4 x i32>88// CHECK-BE: @llvm.ctlz.v2i64(<2 x i64>89// CHECK-BE: extractelement <2 x i64>90// CHECK-BE: icmp eq i64 {{.*}}, 6491// CHECK-BE: extractelement <2 x i64>92// CHECK-BE: add i64 {{.*}}, 6493// CHECK-BE: lshr i64 {{.*}}, 594// CHECK: @llvm.ppc.altivec.vcmpequw(<4 x i32>95// CHECK: @llvm.cttz.v2i64(<2 x i64>96// CHECK: extractelement <2 x i64>97// CHECK: icmp eq i64 {{.*}}, 6498// CHECK: extractelement <2 x i64>99// CHECK: add i64 {{.*}}, 64100// CHECK: lshr i64 {{.*}}, 5101 return vec_first_match_index (vsia, vsib);102}103unsigned test4(void) {104// CHECK-BE: @llvm.ppc.altivec.vcmpequw(<4 x i32>105// CHECK-BE: @llvm.ctlz.v2i64(<2 x i64>106// CHECK-BE: extractelement <2 x i64>107// CHECK-BE: icmp eq i64 {{.*}}, 64108// CHECK-BE: extractelement <2 x i64>109// CHECK-BE: add i64 {{.*}}, 64110// CHECK-BE: lshr i64 {{.*}}, 5111// CHECK: @llvm.ppc.altivec.vcmpequw(<4 x i32>112// CHECK: @llvm.cttz.v2i64(<2 x i64>113// CHECK: extractelement <2 x i64>114// CHECK: icmp eq i64 {{.*}}, 64115// CHECK: extractelement <2 x i64>116// CHECK: add i64 {{.*}}, 64117// CHECK: lshr i64 {{.*}}, 5118 return vec_first_match_index (vuia, vuib);119}120unsigned test5(void) {121// CHECK-BE: @llvm.ppc.altivec.vcmpequh(<8 x i16>122// CHECK-BE: @llvm.ctlz.v2i64(<2 x i64>123// CHECK-BE: extractelement <2 x i64>124// CHECK-BE: icmp eq i64 {{.*}}, 64125// CHECK-BE: extractelement <2 x i64>126// CHECK-BE: add i64 {{.*}}, 64127// CHECK-BE: lshr i64 {{.*}}, 4128// CHECK: @llvm.ppc.altivec.vcmpequh(<8 x i16>129// CHECK: @llvm.cttz.v2i64(<2 x i64>130// CHECK: extractelement <2 x i64>131// CHECK: icmp eq i64 {{.*}}, 64132// CHECK: extractelement <2 x i64>133// CHECK: add i64 {{.*}}, 64134// CHECK: lshr i64 {{.*}}, 4135 return vec_first_match_index (vssa, vssb);136}137unsigned test6(void) {138// CHECK-BE: @llvm.ppc.altivec.vcmpequh(<8 x i16>139// CHECK-BE: @llvm.ctlz.v2i64(<2 x i64>140// CHECK-BE: extractelement <2 x i64>141// CHECK-BE: icmp eq i64 {{.*}}, 64142// CHECK-BE: extractelement <2 x i64>143// CHECK-BE: add i64 {{.*}}, 64144// CHECK-BE: lshr i64 {{.*}}, 4145// CHECK: @llvm.ppc.altivec.vcmpequh(<8 x i16>146// CHECK: @llvm.cttz.v2i64(<2 x i64>147// CHECK: extractelement <2 x i64>148// CHECK: icmp eq i64 {{.*}}, 64149// CHECK: extractelement <2 x i64>150// CHECK: add i64 {{.*}}, 64151// CHECK: lshr i64 {{.*}}, 4152 return vec_first_match_index (vusa, vusb);153}154unsigned test7(void) {155// CHECK-BE: @llvm.ppc.altivec.vcmpequb(<16 x i8>156// CHECK-BE: @llvm.ppc.altivec.vcmpequb(<16 x i8>157// CHECK-BE: or <16 x i8>158// CHECK-BE: @llvm.ppc.altivec.vcmpequb(<16 x i8>159// CHECK-BE: or <16 x i8>160// CHECK-BE: @llvm.ctlz.v2i64(<2 x i64>161// CHECK-BE: extractelement <2 x i64>162// CHECK-BE: icmp eq i64 {{.*}}, 64163// CHECK-BE: extractelement <2 x i64>164// CHECK-BE: add i64 {{.*}}, 64165// CHECK-BE: lshr i64 {{.*}}, 3166// CHECK: @llvm.ppc.altivec.vcmpequb(<16 x i8>167// CHECK: @llvm.ppc.altivec.vcmpequb(<16 x i8>168// CHECK: or <16 x i8>169// CHECK: @llvm.ppc.altivec.vcmpequb(<16 x i8>170// CHECK: or <16 x i8>171// CHECK: @llvm.cttz.v2i64(<2 x i64>172// CHECK: extractelement <2 x i64>173// CHECK: icmp eq i64 {{.*}}, 64174// CHECK: extractelement <2 x i64>175// CHECK: add i64 {{.*}}, 64176// CHECK: lshr i64 {{.*}}, 3177 return vec_first_match_or_eos_index (vsca, vscb);178}179unsigned test8(void) {180// CHECK-BE: @llvm.ppc.altivec.vcmpequb(<16 x i8>181// CHECK-BE: @llvm.ppc.altivec.vcmpequb(<16 x i8>182// CHECK-BE: or <16 x i8>183// CHECK-BE: @llvm.ppc.altivec.vcmpequb(<16 x i8>184// CHECK-BE: or <16 x i8>185// CHECK-BE: @llvm.ctlz.v2i64(<2 x i64>186// CHECK-BE: extractelement <2 x i64>187// CHECK-BE: icmp eq i64 {{.*}}, 64188// CHECK-BE: extractelement <2 x i64>189// CHECK-BE: add i64 {{.*}}, 64190// CHECK-BE: lshr i64 {{.*}}, 3191// CHECK: @llvm.ppc.altivec.vcmpequb(<16 x i8>192// CHECK: @llvm.ppc.altivec.vcmpequb(<16 x i8>193// CHECK: or <16 x i8>194// CHECK: @llvm.ppc.altivec.vcmpequb(<16 x i8>195// CHECK: or <16 x i8>196// CHECK: @llvm.cttz.v2i64(<2 x i64>197// CHECK: extractelement <2 x i64>198// CHECK: icmp eq i64 {{.*}}, 64199// CHECK: extractelement <2 x i64>200// CHECK: add i64 {{.*}}, 64201// CHECK: lshr i64 {{.*}}, 3202 return vec_first_match_or_eos_index (vuca, vucb);203}204unsigned test9(void) {205// CHECK-BE: @llvm.ppc.altivec.vcmpequw(<4 x i32>206// CHECK-BE: @llvm.ppc.altivec.vcmpequw(<4 x i32>207// CHECK-BE: or <4 x i32>208// CHECK-BE: @llvm.ppc.altivec.vcmpequw(<4 x i32>209// CHECK-BE: or <4 x i32>210// CHECK-BE: @llvm.ctlz.v2i64(<2 x i64>211// CHECK-BE: extractelement <2 x i64>212// CHECK-BE: icmp eq i64 {{.*}}, 64213// CHECK-BE: extractelement <2 x i64>214// CHECK-BE: add i64 {{.*}}, 64215// CHECK-BE: lshr i64 {{.*}}, 5216// CHECK: @llvm.ppc.altivec.vcmpequw(<4 x i32>217// CHECK: @llvm.ppc.altivec.vcmpequw(<4 x i32>218// CHECK: or <4 x i32>219// CHECK: @llvm.ppc.altivec.vcmpequw(<4 x i32>220// CHECK: or <4 x i32>221// CHECK: @llvm.cttz.v2i64(<2 x i64>222// CHECK: extractelement <2 x i64>223// CHECK: icmp eq i64 {{.*}}, 64224// CHECK: extractelement <2 x i64>225// CHECK: add i64 {{.*}}, 64226// CHECK: lshr i64 {{.*}}, 5227 return vec_first_match_or_eos_index (vsia, vsib);228}229unsigned test10(void) {230// CHECK-BE: @llvm.ppc.altivec.vcmpequw(<4 x i32>231// CHECK-BE: @llvm.ppc.altivec.vcmpequw(<4 x i32>232// CHECK-BE: or <4 x i32>233// CHECK-BE: @llvm.ppc.altivec.vcmpequw(<4 x i32>234// CHECK-BE: or <4 x i32>235// CHECK-BE: @llvm.ctlz.v2i64(<2 x i64>236// CHECK-BE: extractelement <2 x i64>237// CHECK-BE: icmp eq i64 {{.*}}, 64238// CHECK-BE: extractelement <2 x i64>239// CHECK-BE: add i64 {{.*}}, 64240// CHECK-BE: lshr i64 {{.*}}, 5241// CHECK: @llvm.ppc.altivec.vcmpequw(<4 x i32>242// CHECK: @llvm.ppc.altivec.vcmpequw(<4 x i32>243// CHECK: or <4 x i32>244// CHECK: @llvm.ppc.altivec.vcmpequw(<4 x i32>245// CHECK: or <4 x i32>246// CHECK: @llvm.cttz.v2i64(<2 x i64>247// CHECK: extractelement <2 x i64>248// CHECK: icmp eq i64 {{.*}}, 64249// CHECK: extractelement <2 x i64>250// CHECK: add i64 {{.*}}, 64251// CHECK: lshr i64 {{.*}}, 5252 return vec_first_match_or_eos_index (vuia, vuib);253}254unsigned test11(void) {255// CHECK-BE: @llvm.ppc.altivec.vcmpequh(<8 x i16>256// CHECK-BE: @llvm.ppc.altivec.vcmpequh(<8 x i16>257// CHECK-BE: or <8 x i16>258// CHECK-BE: @llvm.ppc.altivec.vcmpequh(<8 x i16>259// CHECK-BE: or <8 x i16>260// CHECK-BE: @llvm.ctlz.v2i64(<2 x i64>261// CHECK-BE: extractelement <2 x i64>262// CHECK-BE: icmp eq i64 {{.*}}, 64263// CHECK-BE: extractelement <2 x i64>264// CHECK-BE: add i64 {{.*}}, 64265// CHECK-BE: lshr i64 {{.*}}, 4266// CHECK: @llvm.ppc.altivec.vcmpequh(<8 x i16>267// CHECK: @llvm.ppc.altivec.vcmpequh(<8 x i16>268// CHECK: or <8 x i16>269// CHECK: @llvm.ppc.altivec.vcmpequh(<8 x i16>270// CHECK: or <8 x i16>271// CHECK: @llvm.cttz.v2i64(<2 x i64>272// CHECK: extractelement <2 x i64>273// CHECK: icmp eq i64 {{.*}}, 64274// CHECK: extractelement <2 x i64>275// CHECK: add i64 {{.*}}, 64276// CHECK: lshr i64 {{.*}}, 4277 return vec_first_match_or_eos_index (vssa, vssb);278}279unsigned test12(void) {280// CHECK-BE: @llvm.ppc.altivec.vcmpequh(<8 x i16>281// CHECK-BE: @llvm.ppc.altivec.vcmpequh(<8 x i16>282// CHECK-BE: or <8 x i16>283// CHECK-BE: @llvm.ppc.altivec.vcmpequh(<8 x i16>284// CHECK-BE: or <8 x i16>285// CHECK-BE: @llvm.ctlz.v2i64(<2 x i64>286// CHECK-BE: extractelement <2 x i64>287// CHECK-BE: icmp eq i64 {{.*}}, 64288// CHECK-BE: extractelement <2 x i64>289// CHECK-BE: add i64 {{.*}}, 64290// CHECK-BE: lshr i64 {{.*}}, 4291// CHECK: @llvm.ppc.altivec.vcmpequh(<8 x i16>292// CHECK: @llvm.ppc.altivec.vcmpequh(<8 x i16>293// CHECK: or <8 x i16>294// CHECK: @llvm.ppc.altivec.vcmpequh(<8 x i16>295// CHECK: or <8 x i16>296// CHECK: @llvm.cttz.v2i64(<2 x i64>297// CHECK: extractelement <2 x i64>298// CHECK: icmp eq i64 {{.*}}, 64299// CHECK: extractelement <2 x i64>300// CHECK: add i64 {{.*}}, 64301// CHECK: lshr i64 {{.*}}, 4302 return vec_first_match_or_eos_index (vusa, vusb);303}304unsigned test13(void) {305// CHECK-BE: @llvm.ppc.altivec.vcmpneb(<16 x i8>306// CHECK-BE: @llvm.ctlz.v2i64(<2 x i64>307// CHECK-BE: extractelement <2 x i64>308// CHECK-BE: icmp eq i64 {{.*}}, 64309// CHECK-BE: extractelement <2 x i64>310// CHECK-BE: add i64 {{.*}}, 64311// CHECK-BE: lshr i64 {{.*}}, 3312// CHECK: @llvm.ppc.altivec.vcmpneb(<16 x i8>313// CHECK: @llvm.cttz.v2i64(<2 x i64>314// CHECK: extractelement <2 x i64>315// CHECK: icmp eq i64 {{.*}}, 64316// CHECK: extractelement <2 x i64>317// CHECK: add i64 {{.*}}, 64318// CHECK: lshr i64 {{.*}}, 3319 return vec_first_mismatch_index (vsca, vscb);320}321unsigned test14(void) {322// CHECK-BE: @llvm.ppc.altivec.vcmpneb(<16 x i8>323// CHECK-BE: @llvm.ctlz.v2i64(<2 x i64>324// CHECK-BE: extractelement <2 x i64>325// CHECK-BE: icmp eq i64 {{.*}}, 64326// CHECK-BE: extractelement <2 x i64>327// CHECK-BE: add i64 {{.*}}, 64328// CHECK-BE: lshr i64 {{.*}}, 3329// CHECK: @llvm.ppc.altivec.vcmpneb(<16 x i8>330// CHECK: @llvm.cttz.v2i64(<2 x i64>331// CHECK: extractelement <2 x i64>332// CHECK: icmp eq i64 {{.*}}, 64333// CHECK: extractelement <2 x i64>334// CHECK: add i64 {{.*}}, 64335// CHECK: lshr i64 {{.*}}, 3336 return vec_first_mismatch_index (vuca, vucb);337}338unsigned test15(void) {339// CHECK-BE: @llvm.ppc.altivec.vcmpnew(<4 x i32>340// CHECK-BE: @llvm.ctlz.v2i64(<2 x i64>341// CHECK-BE: extractelement <2 x i64>342// CHECK-BE: icmp eq i64 {{.*}}, 64343// CHECK-BE: extractelement <2 x i64>344// CHECK-BE: add i64 {{.*}}, 64345// CHECK-BE: lshr i64 {{.*}}, 5346// CHECK: @llvm.ppc.altivec.vcmpnew(<4 x i32>347// CHECK: @llvm.cttz.v2i64(<2 x i64>348// CHECK: extractelement <2 x i64>349// CHECK: icmp eq i64 {{.*}}, 64350// CHECK: extractelement <2 x i64>351// CHECK: add i64 {{.*}}, 64352// CHECK: lshr i64 {{.*}}, 5353 return vec_first_mismatch_index (vsia, vsib);354}355unsigned test16(void) {356// CHECK-BE: @llvm.ppc.altivec.vcmpnew(<4 x i32>357// CHECK-BE: @llvm.ctlz.v2i64(<2 x i64>358// CHECK-BE: extractelement <2 x i64>359// CHECK-BE: icmp eq i64 {{.*}}, 64360// CHECK-BE: extractelement <2 x i64>361// CHECK-BE: add i64 {{.*}}, 64362// CHECK-BE: lshr i64 {{.*}}, 5363// CHECK: @llvm.ppc.altivec.vcmpnew(<4 x i32>364// CHECK: @llvm.cttz.v2i64(<2 x i64>365// CHECK: extractelement <2 x i64>366// CHECK: icmp eq i64 {{.*}}, 64367// CHECK: extractelement <2 x i64>368// CHECK: add i64 {{.*}}, 64369// CHECK: lshr i64 {{.*}}, 5370 return vec_first_mismatch_index (vuia, vuib);371}372unsigned test17(void) {373// CHECK-BE: @llvm.ppc.altivec.vcmpneh(<8 x i16>374// CHECK-BE: @llvm.ctlz.v2i64(<2 x i64>375// CHECK-BE: extractelement <2 x i64>376// CHECK-BE: icmp eq i64 {{.*}}, 64377// CHECK-BE: extractelement <2 x i64>378// CHECK-BE: add i64 {{.*}}, 64379// CHECK-BE: lshr i64 {{.*}}, 4380// CHECK: @llvm.ppc.altivec.vcmpneh(<8 x i16>381// CHECK: @llvm.cttz.v2i64(<2 x i64>382// CHECK: extractelement <2 x i64>383// CHECK: icmp eq i64 {{.*}}, 64384// CHECK: extractelement <2 x i64>385// CHECK: add i64 {{.*}}, 64386// CHECK: lshr i64 {{.*}}, 4387 return vec_first_mismatch_index (vssa, vssb);388}389unsigned test18(void) {390// CHECK-BE: @llvm.ppc.altivec.vcmpneh(<8 x i16>391// CHECK-BE: @llvm.ctlz.v2i64(<2 x i64>392// CHECK-BE: extractelement <2 x i64>393// CHECK-BE: icmp eq i64 {{.*}}, 64394// CHECK-BE: extractelement <2 x i64>395// CHECK-BE: add i64 {{.*}}, 64396// CHECK-BE: lshr i64 {{.*}}, 4397// CHECK: @llvm.ppc.altivec.vcmpneh(<8 x i16>398// CHECK: @llvm.cttz.v2i64(<2 x i64>399// CHECK: extractelement <2 x i64>400// CHECK: icmp eq i64 {{.*}}, 64401// CHECK: extractelement <2 x i64>402// CHECK: add i64 {{.*}}, 64403// CHECK: lshr i64 {{.*}}, 4404 return vec_first_mismatch_index (vusa, vusb);405}406unsigned test19(void) {407// CHECK-BE: @llvm.ppc.altivec.vcmpnezb(<16 x i8>408// CHECK-BE: @llvm.ctlz.v2i64(<2 x i64>409// CHECK-BE: extractelement <2 x i64>410// CHECK-BE: icmp eq i64 {{.*}}, 64411// CHECK-BE: extractelement <2 x i64>412// CHECK-BE: add i64 {{.*}}, 64413// CHECK-BE: lshr i64 {{.*}}, 3414// CHECK: @llvm.ppc.altivec.vcmpnezb(<16 x i8>415// CHECK: @llvm.cttz.v2i64(<2 x i64>416// CHECK: extractelement <2 x i64>417// CHECK: icmp eq i64 {{.*}}, 64418// CHECK: extractelement <2 x i64>419// CHECK: add i64 {{.*}}, 64420// CHECK: lshr i64 {{.*}}, 3421 return vec_first_mismatch_or_eos_index (vsca, vscb);422}423unsigned test20(void) {424// CHECK-BE: @llvm.ppc.altivec.vcmpnezb(<16 x i8>425// CHECK-BE: @llvm.ctlz.v2i64(<2 x i64>426// CHECK-BE: extractelement <2 x i64>427// CHECK-BE: icmp eq i64 {{.*}}, 64428// CHECK-BE: extractelement <2 x i64>429// CHECK-BE: add i64 {{.*}}, 64430// CHECK-BE: lshr i64 {{.*}}, 3431// CHECK: @llvm.ppc.altivec.vcmpnezb(<16 x i8>432// CHECK: @llvm.cttz.v2i64(<2 x i64>433// CHECK: extractelement <2 x i64>434// CHECK: icmp eq i64 {{.*}}, 64435// CHECK: extractelement <2 x i64>436// CHECK: add i64 {{.*}}, 64437// CHECK: lshr i64 {{.*}}, 3438 return vec_first_mismatch_or_eos_index (vuca, vucb);439}440unsigned test21(void) {441// CHECK-BE: @llvm.ppc.altivec.vcmpnezw(<4 x i32>442// CHECK-BE: @llvm.ctlz.v2i64(<2 x i64>443// CHECK-BE: extractelement <2 x i64>444// CHECK-BE: icmp eq i64 {{.*}}, 64445// CHECK-BE: extractelement <2 x i64>446// CHECK-BE: add i64 {{.*}}, 64447// CHECK-BE: lshr i64 {{.*}}, 5448// CHECK: @llvm.ppc.altivec.vcmpnezw(<4 x i32>449// CHECK: @llvm.cttz.v2i64(<2 x i64>450// CHECK: extractelement <2 x i64>451// CHECK: icmp eq i64 {{.*}}, 64452// CHECK: extractelement <2 x i64>453// CHECK: add i64 {{.*}}, 64454// CHECK: lshr i64 {{.*}}, 5455 return vec_first_mismatch_or_eos_index (vsia, vsib);456}457unsigned test22(void) {458// CHECK-BE: @llvm.ppc.altivec.vcmpnezw(<4 x i32>459// CHECK-BE: @llvm.ctlz.v2i64(<2 x i64>460// CHECK-BE: extractelement <2 x i64>461// CHECK-BE: icmp eq i64 {{.*}}, 64462// CHECK-BE: extractelement <2 x i64>463// CHECK-BE: add i64 {{.*}}, 64464// CHECK-BE: lshr i64 {{.*}}, 5465// CHECK: @llvm.ppc.altivec.vcmpnezw(<4 x i32>466// CHECK: @llvm.cttz.v2i64(<2 x i64>467// CHECK: extractelement <2 x i64>468// CHECK: icmp eq i64 {{.*}}, 64469// CHECK: extractelement <2 x i64>470// CHECK: add i64 {{.*}}, 64471// CHECK: lshr i64 {{.*}}, 5472 return vec_first_mismatch_or_eos_index (vuia, vuib);473}474unsigned test23(void) {475// CHECK-BE: @llvm.ppc.altivec.vcmpnezh(<8 x i16>476// CHECK-BE: @llvm.ctlz.v2i64(<2 x i64>477// CHECK-BE: extractelement <2 x i64>478// CHECK-BE: icmp eq i64 {{.*}}, 64479// CHECK-BE: extractelement <2 x i64>480// CHECK-BE: add i64 {{.*}}, 64481// CHECK-BE: lshr i64 {{.*}}, 4482// CHECK: @llvm.ppc.altivec.vcmpnezh(<8 x i16>483// CHECK: @llvm.cttz.v2i64(<2 x i64>484// CHECK: extractelement <2 x i64>485// CHECK: icmp eq i64 {{.*}}, 64486// CHECK: extractelement <2 x i64>487// CHECK: add i64 {{.*}}, 64488// CHECK: lshr i64 {{.*}}, 4489 return vec_first_mismatch_or_eos_index (vssa, vssb);490}491unsigned test24(void) {492// CHECK-BE: @llvm.ppc.altivec.vcmpnezh(<8 x i16>493// CHECK-BE: @llvm.ctlz.v2i64(<2 x i64>494// CHECK-BE: extractelement <2 x i64>495// CHECK-BE: icmp eq i64 {{.*}}, 64496// CHECK-BE: extractelement <2 x i64>497// CHECK-BE: add i64 {{.*}}, 64498// CHECK-BE: lshr i64 {{.*}}, 4499// CHECK: @llvm.ppc.altivec.vcmpnezh(<8 x i16>500// CHECK: @llvm.cttz.v2i64(<2 x i64>501// CHECK: extractelement <2 x i64>502// CHECK: icmp eq i64 {{.*}}, 64503// CHECK: extractelement <2 x i64>504// CHECK: add i64 {{.*}}, 64505// CHECK: lshr i64 {{.*}}, 4506 return vec_first_mismatch_or_eos_index (vusa, vusb);507}508vector bool char test25(void) {509// CHECK-BE: @llvm.ppc.altivec.vcmpneb(<16 x i8>510// CHECK-BE-NEXT: ret <16 x i8>511// CHECK: @llvm.ppc.altivec.vcmpneb(<16 x i8>512// CHECK-NEXT: ret <16 x i8>513 return vec_cmpne (vbca, vbcb);514}515vector bool char test26(void) {516// CHECK-BE: @llvm.ppc.altivec.vcmpneb(<16 x i8>517// CHECK-BE-NEXT: ret <16 x i8>518// CHECK: @llvm.ppc.altivec.vcmpneb(<16 x i8>519// CHECK-NEXT: ret <16 x i8>520 return vec_cmpne (vsca, vscb);521}522vector bool char test27(void) {523// CHECK-BE: @llvm.ppc.altivec.vcmpneb(<16 x i8>524// CHECK-BE-NEXT: ret <16 x i8>525// CHECK: @llvm.ppc.altivec.vcmpneb(<16 x i8>526// CHECK-NEXT: ret <16 x i8>527 return vec_cmpne (vuca, vucb);528}529vector bool int test28(void) {530// CHECK-BE: @llvm.ppc.altivec.vcmpnew(<4 x i32>531// CHECK-BE-NEXT: ret <4 x i32>532// CHECK: @llvm.ppc.altivec.vcmpnew(<4 x i32>533// CHECK-NEXT: ret <4 x i32>534 return vec_cmpne (vbia, vbib);535}536vector bool int test29(void) {537// CHECK-BE: @llvm.ppc.altivec.vcmpnew(<4 x i32>538// CHECK-BE-NEXT: ret <4 x i32>539// CHECK: @llvm.ppc.altivec.vcmpnew(<4 x i32>540// CHECK-NEXT: ret <4 x i32>541 return vec_cmpne (vsia, vsib);542}543vector bool int test30(void) {544// CHECK-BE: @llvm.ppc.altivec.vcmpnew(<4 x i32>545// CHECK-BE-NEXT: ret <4 x i32>546// CHECK: @llvm.ppc.altivec.vcmpnew(<4 x i32>547// CHECK-NEXT: ret <4 x i32>548 return vec_cmpne (vuia, vuib);549}550vector bool long long test31(void) {551// CHECK-BE: @llvm.ppc.altivec.vcmpequd(<2 x i64>552// CHECK-BE: xor <2 x i64>553// CHECK-BE-NEXT: ret <2 x i64>554// CHECK: @llvm.ppc.altivec.vcmpequd(<2 x i64>555// CHECK: xor <2 x i64>556// CHECK-NEXT: ret <2 x i64>557 return vec_cmpne (vbla, vblb);558}559vector bool long long test32(void) {560// CHECK-BE: @llvm.ppc.altivec.vcmpequd(<2 x i64>561// CHECK-BE: xor <2 x i64>562// CHECK-BE-NEXT: ret <2 x i64>563// CHECK: @llvm.ppc.altivec.vcmpequd(<2 x i64>564// CHECK: xor <2 x i64>565// CHECK-NEXT: ret <2 x i64>566 return vec_cmpne (vsla, vslb);567}568vector bool long long test33(void) {569// CHECK-BE: @llvm.ppc.altivec.vcmpequd(<2 x i64>570// CHECK-BE: xor <2 x i64>571// CHECK-BE-NEXT: ret <2 x i64>572// CHECK: @llvm.ppc.altivec.vcmpequd(<2 x i64>573// CHECK: xor <2 x i64>574// CHECK-NEXT: ret <2 x i64>575 return vec_cmpne (vula, vulb);576}577vector bool short test34(void) {578// CHECK-BE: @llvm.ppc.altivec.vcmpneh(<8 x i16>579// CHECK-BE-NEXT: ret <8 x i16>580// CHECK: @llvm.ppc.altivec.vcmpneh(<8 x i16>581// CHECK-NEXT: ret <8 x i16>582 return vec_cmpne (vbsa, vbsb);583}584vector bool short test35(void) {585// CHECK-BE: @llvm.ppc.altivec.vcmpneh(<8 x i16>586// CHECK-BE-NEXT: ret <8 x i16>587// CHECK: @llvm.ppc.altivec.vcmpneh(<8 x i16>588// CHECK-NEXT: ret <8 x i16>589 return vec_cmpne (vssa, vssb);590}591vector bool short test36(void) {592// CHECK-BE: @llvm.ppc.altivec.vcmpneh(<8 x i16>593// CHECK-BE-NEXT: ret <8 x i16>594// CHECK: @llvm.ppc.altivec.vcmpneh(<8 x i16>595// CHECK-NEXT: ret <8 x i16>596 return vec_cmpne (vusa, vusb);597}598vector bool long long test37(void) {599// CHECK-BE: @llvm.ppc.altivec.vcmpequd(<2 x i64>600// CHECK-BE: xor <2 x i64>601// CHECK-BE-NEXT: ret <2 x i64>602// CHECK: @llvm.ppc.altivec.vcmpequd(<2 x i64>603// CHECK: xor <2 x i64>604// CHECK-NEXT: ret <2 x i64>605 return vec_cmpne (vda, vdb);606}607vector bool int test38(void) {608// CHECK-BE: @llvm.ppc.altivec.vcmpnew(<4 x i32>609// CHECK-BE-NEXT: ret <4 x i32>610// CHECK: @llvm.ppc.altivec.vcmpnew(<4 x i32>611// CHECK-NEXT: ret <4 x i32>612 return vec_cmpne (vfa, vfb);613}614vector signed char test39(void) {615// CHECK-BE: @llvm.cttz.v16i8(<16 x i8>616// CHECK-BE-NEXT: ret <16 x i8>617// CHECK: @llvm.cttz.v16i8(<16 x i8>618// CHECK-NEXT: ret <16 x i8>619 return vec_cnttz (vsca);620}621vector unsigned char test40(void) {622// CHECK-BE: @llvm.cttz.v16i8(<16 x i8>623// CHECK-BE-NEXT: ret <16 x i8>624// CHECK: @llvm.cttz.v16i8(<16 x i8>625// CHECK-NEXT: ret <16 x i8>626 return vec_cnttz (vuca);627}628vector signed int test41(void) {629// CHECK-BE: @llvm.cttz.v4i32(<4 x i32>630// CHECK-BE-NEXT: ret <4 x i32>631// CHECK: @llvm.cttz.v4i32(<4 x i32>632// CHECK-NEXT: ret <4 x i32>633 return vec_cnttz (vsia);634}635vector unsigned int test42(void) {636// CHECK-BE: @llvm.cttz.v4i32(<4 x i32>637// CHECK-BE-NEXT: ret <4 x i32>638// CHECK: @llvm.cttz.v4i32(<4 x i32>639// CHECK-NEXT: ret <4 x i32>640 return vec_cnttz (vuia);641}642vector signed long long test43(void) {643// CHECK-BE: @llvm.cttz.v2i64(<2 x i64>644// CHECK-BE-NEXT: ret <2 x i64>645// CHECK: @llvm.cttz.v2i64(<2 x i64>646// CHECK-NEXT: ret <2 x i64>647 return vec_cnttz (vsla);648}649vector unsigned long long test44(void) {650// CHECK-BE: @llvm.cttz.v2i64(<2 x i64>651// CHECK-BE-NEXT: ret <2 x i64>652// CHECK: @llvm.cttz.v2i64(<2 x i64>653// CHECK-NEXT: ret <2 x i64>654 return vec_cnttz (vula);655}656vector signed short test45(void) {657// CHECK-BE: @llvm.cttz.v8i16(<8 x i16>658// CHECK-BE-NEXT: ret <8 x i16>659// CHECK: @llvm.cttz.v8i16(<8 x i16>660// CHECK-NEXT: ret <8 x i16>661 return vec_cnttz (vssa);662}663vector unsigned short test46(void) {664// CHECK-BE: @llvm.cttz.v8i16(<8 x i16>665// CHECK-BE-NEXT: ret <8 x i16>666// CHECK: @llvm.cttz.v8i16(<8 x i16>667// CHECK-NEXT: ret <8 x i16>668 return vec_cnttz (vusa);669}670vector unsigned char test47(void) {671// CHECK-BE: @llvm.ctpop.v16i8(<16 x i8>672// CHECK-BE-NEXT: ret <16 x i8>673// CHECK: @llvm.ctpop.v16i8(<16 x i8>674// CHECK-NEXT: ret <16 x i8>675 return vec_popcnt (vsca);676}677vector unsigned char test48(void) {678// CHECK-BE: @llvm.ctpop.v16i8(<16 x i8>679// CHECK-BE-NEXT: ret <16 x i8>680// CHECK: @llvm.ctpop.v16i8(<16 x i8>681// CHECK-NEXT: ret <16 x i8>682 return vec_popcnt (vuca);683}684vector unsigned int test49(void) {685// CHECK-BE: @llvm.ctpop.v4i32(<4 x i32>686// CHECK-BE-NEXT: ret <4 x i32>687// CHECK: @llvm.ctpop.v4i32(<4 x i32>688// CHECK-NEXT: ret <4 x i32>689 return vec_popcnt (vsia);690}691vector unsigned int test50(void) {692// CHECK-BE: @llvm.ctpop.v4i32(<4 x i32>693// CHECK-BE-NEXT: ret <4 x i32>694// CHECK: @llvm.ctpop.v4i32(<4 x i32>695// CHECK-NEXT: ret <4 x i32>696 return vec_popcnt (vuia);697}698vector unsigned long long test51(void) {699// CHECK-BE: @llvm.ctpop.v2i64(<2 x i64>700// CHECK-BE-NEXT: ret <2 x i64>701// CHECK: @llvm.ctpop.v2i64(<2 x i64>702// CHECK-NEXT: ret <2 x i64>703 return vec_popcnt (vsla);704}705vector unsigned long long test52(void) {706// CHECK-BE: @llvm.ctpop.v2i64(<2 x i64>707// CHECK-BE-NEXT: ret <2 x i64>708// CHECK: @llvm.ctpop.v2i64(<2 x i64>709// CHECK-NEXT: ret <2 x i64>710 return vec_popcnt (vula);711}712vector unsigned short test53(void) {713// CHECK-BE: @llvm.ctpop.v8i16(<8 x i16>714// CHECK-BE-NEXT: ret <8 x i16>715// CHECK: @llvm.ctpop.v8i16(<8 x i16>716// CHECK-NEXT: ret <8 x i16>717 return vec_popcnt (vssa);718}719vector unsigned short test54(void) {720// CHECK-BE: @llvm.ctpop.v8i16(<8 x i16>721// CHECK-BE-NEXT: ret <8 x i16>722// CHECK: @llvm.ctpop.v8i16(<8 x i16>723// CHECK-NEXT: ret <8 x i16>724 return vec_popcnt (vusa);725}726vector double test55(void) {727// CHECK-BE: @llvm.ppc.vsx.xviexpdp(<2 x i64> %{{.+}}, <2 x i64>728// CHECK-BE-NEXT: ret <2 x double>729// CHECK: @llvm.ppc.vsx.xviexpdp(<2 x i64> %{{.+}}, <2 x i64>730// CHECK-NEXT: ret <2 x double>731 return vec_insert_exp (vda,vulb);732}733vector double test56(void) {734// CHECK-BE: @llvm.ppc.vsx.xviexpdp(<2 x i64> %{{.+}}, <2 x i64>735// CHECK-BE-NEXT: ret <2 x double>736// CHECK: @llvm.ppc.vsx.xviexpdp(<2 x i64> %{{.+}}, <2 x i64>737// CHECK-NEXT: ret <2 x double>738 return vec_insert_exp (vula, vulb);739}740vector float test57(void) {741// CHECK-BE: @llvm.ppc.vsx.xviexpsp(<4 x i32> %{{.+}}, <4 x i32>742// CHECK-BE-NEXT: ret <4 x float>743// CHECK: @llvm.ppc.vsx.xviexpsp(<4 x i32> %{{.+}}, <4 x i32>744// CHECK-NEXT: ret <4 x float>745 return vec_insert_exp (vfa,vuib);746}747vector float test58(void) {748// CHECK-BE: @llvm.ppc.vsx.xviexpsp(<4 x i32> %{{.+}}, <4 x i32>749// CHECK-BE-NEXT: ret <4 x float>750// CHECK: @llvm.ppc.vsx.xviexpsp(<4 x i32> %{{.+}}, <4 x i32>751// CHECK-NEXT: ret <4 x float>752 return vec_insert_exp (vuia,vuib);753}754signed int test59(void) {755// CHECK-BE: @llvm.ppc.altivec.vclzlsbb(<16 x i8>756// CHECK-BE-NEXT: ret i32757// CHECK-LE: @llvm.ppc.altivec.vctzlsbb(<16 x i8>758// CHECK-LE-NEXT: ret i32759 return vec_cntlz_lsbb (vuca);760}761signed int test60(void) {762// CHECK-BE: @llvm.ppc.altivec.vclzlsbb(<16 x i8>763// CHECK-BE-NEXT: ret i32764// CHECK-LE: @llvm.ppc.altivec.vctzlsbb(<16 x i8>765// CHECK-LE-NEXT: ret i32766 return vec_cntlz_lsbb (vsca);767}768signed int test61(void) {769// CHECK-BE: @llvm.ppc.altivec.vctzlsbb(<16 x i8>770// CHECK-BE-NEXT: ret i32771// CHECK-LE: @llvm.ppc.altivec.vclzlsbb(<16 x i8>772// CHECK-LE-NEXT: ret i32773 return vec_cnttz_lsbb (vsca);774}775signed int test62(void) {776// CHECK-BE: @llvm.ppc.altivec.vctzlsbb(<16 x i8>777// CHECK-BE-NEXT: ret i32778// CHECK-LE: @llvm.ppc.altivec.vclzlsbb(<16 x i8>779// CHECK-LE-NEXT: ret i32780 return vec_cnttz_lsbb (vuca);781}782vector unsigned int test63(void) {783// CHECK-BE: @llvm.ppc.altivec.vprtybw(<4 x i32>784// CHECK-BE-NEXT: ret <4 x i32>785// CHECK: @llvm.ppc.altivec.vprtybw(<4 x i32>786// CHECK-NEXT: ret <4 x i32>787 return vec_parity_lsbb (vuia);788}789vector unsigned int test64(void) {790// CHECK-BE: @llvm.ppc.altivec.vprtybw(<4 x i32>791// CHECK-BE-NEXT: ret <4 x i32>792// CHECK: @llvm.ppc.altivec.vprtybw(<4 x i32>793// CHECK-NEXT: ret <4 x i32>794 return vec_parity_lsbb (vsia);795}796vector unsigned long long test65(void) {797// CHECK-BE: @llvm.ppc.altivec.vprtybd(<2 x i64>798// CHECK-BE-NEXT: ret <2 x i64>799// CHECK: @llvm.ppc.altivec.vprtybd(<2 x i64>800// CHECK-NEXT: ret <2 x i64>801 return vec_parity_lsbb (vula);802}803vector unsigned long long test66(void) {804// CHECK-BE: @llvm.ppc.altivec.vprtybd(<2 x i64>805// CHECK-BE-NEXT: ret <2 x i64>806// CHECK: @llvm.ppc.altivec.vprtybd(<2 x i64>807// CHECK-NEXT: ret <2 x i64>808 return vec_parity_lsbb (vsla);809}810vector unsigned __int128 test67(void) {811// CHECK-BE: @llvm.ppc.altivec.vprtybq(<1 x i128>812// CHECK-BE-NEXT: ret <1 x i128>813// CHECK: @llvm.ppc.altivec.vprtybq(<1 x i128>814// CHECK-NEXT: ret <1 x i128>815 return vec_parity_lsbb (vui128a);816}817vector unsigned __int128 test68(void) {818// CHECK-BE: @llvm.ppc.altivec.vprtybq(<1 x i128>819// CHECK-BE-NEXT: ret <1 x i128>820// CHECK: @llvm.ppc.altivec.vprtybq(<1 x i128>821// CHECK-NEXT: ret <1 x i128>822 return vec_parity_lsbb (vsi128a);823}824vector unsigned char test69(void) {825// CHECK-BE: call <16 x i8> @llvm.ppc.altivec.vabsdub(<16 x i8> {{.+}}, <16 x i8> {{.+}})826// CHECK: call <16 x i8> @llvm.ppc.altivec.vabsdub(<16 x i8> {{.+}}, <16 x i8> {{.+}})827 return vec_absd(vuca, vucb);828}829vector unsigned short test70(void) {830// CHECK-BE: call <8 x i16> @llvm.ppc.altivec.vabsduh(<8 x i16> {{.+}}, <8 x i16> {{.+}})831// CHECK: call <8 x i16> @llvm.ppc.altivec.vabsduh(<8 x i16> {{.+}}, <8 x i16> {{.+}})832 return vec_absd(vusa, vusb);833}834vector unsigned int test71(void) {835// CHECK-BE: call <4 x i32> @llvm.ppc.altivec.vabsduw(<4 x i32> {{.+}}, <4 x i32> {{.+}})836// CHECK: call <4 x i32> @llvm.ppc.altivec.vabsduw(<4 x i32> {{.+}}, <4 x i32> {{.+}})837 return vec_absd(vuia, vuib);838}839vector unsigned char test72(void) {840// CHECK-BE: @llvm.ppc.altivec.vslv(<16 x i8>841// CHECK-BE-NEXT: ret <16 x i8>842// CHECK: @llvm.ppc.altivec.vslv(<16 x i8>843// CHECK-NEXT: ret <16 x i8>844 return vec_slv (vuca, vucb);845}846vector unsigned char test73(void) {847// CHECK-BE: @llvm.ppc.altivec.vsrv(<16 x i8>848// CHECK-BE-NEXT: ret <16 x i8>849// CHECK: @llvm.ppc.altivec.vsrv(<16 x i8>850// CHECK-NEXT: ret <16 x i8>851 return vec_srv (vuca, vucb);852}853vector unsigned short test74(void) {854// CHECK-BE: @llvm.ppc.vsx.xvcvsphp(<4 x float>855// CHECK-BE: @llvm.ppc.vsx.xvcvsphp(<4 x float>856// CHECK-BE: [[REG0:%[0-9]+]] = call <4 x i32> @llvm.ppc.altivec.vperm857// CHECK-BE-NEXT: [[REG1:%[0-9]+]] = bitcast <4 x i32> [[REG0]] to <4 x float>858// CHECK-BE-NEXT: [[REG2:%[0-9]+]] = bitcast <4 x float> [[REG1]] to <8 x i16>859// CHECK-BE-NEXT: ret <8 x i16> [[REG2]]860// CHECK: @llvm.ppc.vsx.xvcvsphp(<4 x float>861// CHECK: @llvm.ppc.vsx.xvcvsphp(<4 x float>862// CHECK: [[REG0:%[0-9]+]] = call <4 x i32> @llvm.ppc.altivec.vperm863// CHECK-NEXT: [[REG1:%[0-9]+]] = bitcast <4 x i32> [[REG0]] to <4 x float>864// CHECK-NEXT: [[REG2:%[0-9]+]] = bitcast <4 x float> [[REG1]] to <8 x i16>865// CHECK-NEXT: ret <8 x i16> [[REG2]]866 return vec_pack_to_short_fp32(vfa, vfb);867}868vector unsigned int test75(void) {869// CHECK-BE: @llvm.ppc.altivec.vrlwmi(<4 x i32870// CHECK-BE-NEXT: ret <4 x i32>871// CHECK: @llvm.ppc.altivec.vrlwmi(<4 x i32872// CHECK-NEXT: ret <4 x i32>873 return vec_rlmi(vuia, vuia, vuia);874}875vector unsigned long long test76(void) {876// CHECK-BE: @llvm.ppc.altivec.vrldmi(<2 x i64877// CHECK-BE-NEXT: ret <2 x i64>878// CHECK: @llvm.ppc.altivec.vrldmi(<2 x i64879// CHECK-NEXT: ret <2 x i64>880 return vec_rlmi(vula, vula, vula);881}882vector unsigned int test77(void) {883// CHECK-BE: %[[RES1:.+]] = shl <4 x i32884// CHECK-BE: %[[RES2:.+]] = or <4 x i32> %[[RES1]]885// CHECK-BE: @llvm.ppc.altivec.vrlwnm(<4 x i32886// CHECK-BE: ret <4 x i32>887// CHECK: %[[RES1:.+]] = shl <4 x i32888// CHECK: %[[RES2:.+]] = or <4 x i32> %[[RES1]]889// CHECK: @llvm.ppc.altivec.vrlwnm(<4 x i32890// CHECK: ret <4 x i32>891 return vec_rlnm(vuia, vuia, vuia);892}893vector unsigned long long test78(void) {894// CHECK-BE: %[[RES1:.+]] = shl <2 x i64895// CHECK-BE: %[[RES2:.+]] = or <2 x i64> %[[RES1]]896// CHECK-BE: @llvm.ppc.altivec.vrldnm(<2 x i64897// CHECK-BE-NEXT: ret <2 x i64>898// CHECK: %[[RES1:.+]] = shl <2 x i64899// CHECK: %[[RES2:.+]] = or <2 x i64> %[[RES1]]900// CHECK: @llvm.ppc.altivec.vrldnm(<2 x i64901// CHECK-NEXT: ret <2 x i64>902 return vec_rlnm(vula, vula, vula);903}904vector double test79(void) {905// CHECK-BE: extractelement <4 x float>906// CHECK-BE: fpext float907// CHECK-BE: insertelement <2 x double>908// CHECK-BE: extractelement <4 x float>909// CHECK-BE: fpext float910// CHECK-BE: insertelement <2 x double>911// CHECK: extractelement <4 x float>912// CHECK: fpext float913// CHECK: insertelement <2 x double>914// CHECK: extractelement <4 x float>915// CHECK: fpext float916// CHECK: insertelement <2 x double>917 return vec_unpackh(vfa);918}919vector double test80(void) {920// CHECK-BE: extractelement <4 x float>921// CHECK-BE: fpext float922// CHECK-BE: insertelement <2 x double>923// CHECK-BE: extractelement <4 x float>924// CHECK-BE: fpext float925// CHECK-BE: insertelement <2 x double>926// CHECK: extractelement <4 x float>927// CHECK: fpext float928// CHECK: insertelement <2 x double>929// CHECK: extractelement <4 x float>930// CHECK: fpext float931// CHECK: insertelement <2 x double>932 return vec_unpackl(vfa);933}934vector float test81(void) {935 // CHECK: extractelement <2 x double>936 // CHECK: fptrunc double937 // CHECK: insertelement <4 x float>938 // CHECK: extractelement <2 x double>939 // CHECK: fptrunc double940 // CHECK: insertelement <4 x float>941 // CHECK: extractelement <2 x double>942 // CHECK: fptrunc double943 // CHECK: insertelement <4 x float>944 // CHECK: extractelement <2 x double>945 // CHECK: fptrunc double946 // CHECK: insertelement <4 x float>947 // CHECK-LE: extractelement <2 x double>948 // CHECK-LE: fptrunc double949 // CHECK-LE: insertelement <4 x float>950 // CHECK-LE: extractelement <2 x double>951 // CHECK-LE: fptrunc double952 // CHECK-LE: insertelement <4 x float>953 // CHECK-LE: extractelement <2 x double>954 // CHECK-LE: fptrunc double955 // CHECK-LE: insertelement <4 x float>956 // CHECK-LE: extractelement <2 x double>957 // CHECK-LE: fptrunc double958 // CHECK-LE: insertelement <4 x float>959 return vec_pack(vda, vdb);960}961vector unsigned int test82(void) {962// CHECK-BE: @llvm.ppc.vsx.xvxexpsp(<4 x float> {{.+}})963// CHECK-BE-NEXT: ret <4 x i32>964// CHECK: @llvm.ppc.vsx.xvxexpsp(<4 x float> {{.+}})965// CHECK-NEXT: ret <4 x i32>966 return vec_extract_exp(vfa);967}968vector unsigned long long test83(void) {969// CHECK-BE: @llvm.ppc.vsx.xvxexpdp(<2 x double> {{.+}})970// CHECK-BE-NEXT: ret <2 x i64>971// CHECK: @llvm.ppc.vsx.xvxexpdp(<2 x double> {{.+}})972// CHECK-NEXT: ret <2 x i64>973 return vec_extract_exp(vda);974}975vector unsigned int test84(void) {976// CHECK-BE: @llvm.ppc.vsx.xvxsigsp(<4 x float> {{.+}})977// CHECK-BE-NEXT: ret <4 x i32>978// CHECK: @llvm.ppc.vsx.xvxsigsp(<4 x float> {{.+}})979// CHECK-NEXT: ret <4 x i32>980 return vec_extract_sig(vfa);981}982vector unsigned long long test85(void) {983// CHECK-BE: @llvm.ppc.vsx.xvxsigdp(<2 x double> {{.+}})984// CHECK-BE-NEXT: ret <2 x i64>985// CHECK: @llvm.ppc.vsx.xvxsigdp(<2 x double> {{.+}})986// CHECK-NEXT: ret <2 x i64>987 return vec_extract_sig(vda);988}989vector bool int test86(void) {990// CHECK-BE: @llvm.ppc.vsx.xvtstdcsp(<4 x float> {{.+}}, i32 127)991// CHECK-BE-NEXT: ret <4 x i32>992// CHECK: @llvm.ppc.vsx.xvtstdcsp(<4 x float> {{.+}}, i32 127)993// CHECK-NEXT: ret <4 x i32>994 return vec_test_data_class(vfa, __VEC_CLASS_FP_NOT_NORMAL);995}996vector bool long long test87(void) {997// CHECK-BE: @llvm.ppc.vsx.xvtstdcdp(<2 x double> {{.+}}, i32 127)998// CHECK-BE-NEXT: ret <2 x i64>999// CHECK: @llvm.ppc.vsx.xvtstdcdp(<2 x double> {{.+}}, i32 127)1000// CHECK-NEXT: ret <2 x i64>1001 return vec_test_data_class(vda, __VEC_CLASS_FP_NOT_NORMAL);1002}1003vector unsigned char test88(void) {1004// CHECK-BE: @llvm.ppc.vsx.lxvl(ptr %{{.+}}, i641005// CHECK-BE-NEXT-NEXT: ret <16 x i8>1006// CHECK: @llvm.ppc.vsx.lxvl(ptr %{{.+}}, i641007// CHECK-NEXT-NEXT: ret <16 x i8>1008 return vec_xl_len(uc,0);1009}1010vector signed char test89(void) {1011// CHECK-BE: @llvm.ppc.vsx.lxvl(ptr %{{.+}}, i641012// CHECK-BE-NEXT-NEXT: ret <16 x i8>1013// CHECK: @llvm.ppc.vsx.lxvl(ptr %{{.+}}, i641014// CHECK-NEXT-NEXT: ret <16 x i8>1015 return vec_xl_len(sc,0);1016}1017vector unsigned short test90(void) {1018// CHECK-BE: @llvm.ppc.vsx.lxvl(ptr %{{.+}}, i641019// CHECK-BE-NEXT-NEXT: ret <8 x i16>1020// CHECK: @llvm.ppc.vsx.lxvl(ptr %{{.+}}, i641021// CHECK-NEXT-NEXT: ret <8 x i16>1022 return vec_xl_len(us,0);1023}1024vector signed short test91(void) {1025// CHECK-BE: @llvm.ppc.vsx.lxvl(ptr %{{.+}}, i641026// CHECK-BE-NEXT-NEXT: ret <8 x i16>1027// CHECK: @llvm.ppc.vsx.lxvl(ptr %{{.+}}, i641028// CHECK-NEXT-NEXT: ret <8 x i16>1029 return vec_xl_len(ss,0);1030}1031vector unsigned int test92(void) {1032// CHECK-BE: @llvm.ppc.vsx.lxvl(ptr %{{.+}}, i641033// CHECK-BE-NEXT: ret <4 x i32>1034// CHECK: @llvm.ppc.vsx.lxvl(ptr %{{.+}}, i641035// CHECK-NEXT: ret <4 x i32>1036 return vec_xl_len(ui,0);1037}1038 1039vector signed int test93(void) {1040// CHECK-BE: @llvm.ppc.vsx.lxvl(ptr %{{.+}}, i641041// CHECK-BE-NEXT: ret <4 x i32>1042// CHECK: @llvm.ppc.vsx.lxvl(ptr %{{.+}}, i641043// CHECK-NEXT: ret <4 x i32>1044 return vec_xl_len(si,0);1045}1046 1047vector float test94(void) {1048// CHECK-BE: @llvm.ppc.vsx.lxvl(ptr %{{.+}}, i641049// CHECK-BE-NEXT-NEXT: ret <4 x i32>1050// CHECK: @llvm.ppc.vsx.lxvl(ptr %{{.+}}, i641051// CHECK-NEXT-NEXT: ret <4 x i32>1052 return vec_xl_len(f,0);1053}1054 1055vector unsigned long long test95(void) {1056// CHECK-BE: @llvm.ppc.vsx.lxvl(ptr %{{.+}}, i641057// CHECK-BE-NEXT-NEXT: ret <2 x i64>1058// CHECK: @llvm.ppc.vsx.lxvl(ptr %{{.+}}, i641059// CHECK-NEXT-NEXT: ret <2 x i64>1060 return vec_xl_len(ull,0);1061}1062 1063vector signed long long test96(void) {1064// CHECK-BE: @llvm.ppc.vsx.lxvl(ptr %{{.+}}, i641065// CHECK-BE-NEXT-NEXT: ret <2 x i64>1066// CHECK: @llvm.ppc.vsx.lxvl(ptr %{{.+}}, i641067// CHECK-NEXT-NEXT: ret <2 x i64>1068 return vec_xl_len(sll,0);1069}1070 1071vector double test97(void) {1072// CHECK-BE: @llvm.ppc.vsx.lxvl(ptr %{{.+}}, i641073// CHECK-BE-NEXT-NEXT: ret <2 x i64>1074// CHECK: @llvm.ppc.vsx.lxvl(ptr %{{.+}}, i641075// CHECK-NEXT-NEXT: ret <2 x i64>1076 return vec_xl_len(d,0);1077}1078 1079vector unsigned __int128 test98(void) {1080// CHECK-BE: @llvm.ppc.vsx.lxvl(ptr %{{.+}}, i641081// CHECK-BE-NEXT-NEXT: ret <1 x i128>1082// CHECK: @llvm.ppc.vsx.lxvl(ptr %{{.+}}, i641083// CHECK-NEXT-NEXT: ret <1 x i128>1084 return vec_xl_len(uint128,0);1085}1086 1087vector signed __int128 test99(void) {1088// CHECK-BE: @llvm.ppc.vsx.lxvl(ptr %{{.+}}, i641089// CHECK-BE-NEXT-NEXT: ret <1 x i128>1090// CHECK: @llvm.ppc.vsx.lxvl(ptr %{{.+}}, i641091// CHECK-NEXT-NEXT: ret <1 x i128>1092 return vec_xl_len(sint128,0);1093}1094 1095void test100(void) {1096// CHECK-BE: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, ptr %{{.+}}, i641097// CHECK: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, ptr %{{.+}}, i641098 return vec_xst_len(vuca,uc,0);1099}1100 1101void test101(void) {1102// CHECK-BE: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, ptr %{{.+}}, i641103// CHECK: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, ptr %{{.+}}, i641104 return vec_xst_len(vsca,sc,0);1105}1106 1107void test102(void) {1108// CHECK-BE: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, ptr %{{.+}}, i641109// CHECK: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, ptr %{{.+}}, i641110 return vec_xst_len(vusa,us,0);1111}1112 1113void test103(void) {1114// CHECK-BE: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, ptr %{{.+}}, i641115// CHECK: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, ptr %{{.+}}, i641116 return vec_xst_len(vssa,ss,0);1117}1118 1119void test104(void) {1120// CHECK-BE: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, ptr %{{.+}}, i641121// CHECK: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, ptr %{{.+}}, i641122 return vec_xst_len(vuia,ui,0);1123}1124 1125void test105(void) {1126// CHECK-BE: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, ptr %{{.+}}, i641127// CHECK: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, ptr %{{.+}}, i641128 return vec_xst_len(vsia,si,0);1129}1130 1131void test106(void) {1132// CHECK-BE: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, ptr %{{.+}}, i641133// CHECK: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, ptr %{{.+}}, i641134 return vec_xst_len(vfa,f,0);1135}1136 1137void test107(void) {1138// CHECK-BE: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, ptr %{{.+}}, i641139// CHECK: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, ptr %{{.+}}, i641140 return vec_xst_len(vula,ull,0);1141}1142 1143void test108(void) {1144// CHECK-BE: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, ptr %{{.+}}, i641145// CHECK: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, ptr %{{.+}}, i641146 return vec_xst_len(vsla,sll,0);1147}1148 1149void test109(void) {1150// CHECK-BE: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, ptr %{{.+}}, i641151// CHECK: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, ptr %{{.+}}, i641152 return vec_xst_len(vda,d,0);1153}1154 1155void test110(void) {1156// CHECK-BE: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, ptr %{{.+}}, i641157// CHECK: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, ptr %{{.+}}, i641158 return vec_xst_len(vui128a,uint128,0);1159}1160 1161void test111(void) {1162// CHECK-BE: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, ptr %{{.+}}, i641163// CHECK: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, ptr %{{.+}}, i641164 return vec_xst_len(vsi128a,sint128,0);1165}1166 1167vector unsigned char test112(void) {1168// CHECK-BE: @llvm.ppc.vsx.lxvll(ptr %{{.+}}, i641169// CHECK-BE: @llvm.ppc.altivec.lvsr(ptr %{{.+}}1170// CHECK-BE: @llvm.ppc.altivec.vperm1171// CHECK: @llvm.ppc.vsx.lxvll(ptr %{{.+}}, i641172// CHECK: @llvm.ppc.altivec.lvsr(ptr %{{.+}}1173// CHECK: @llvm.ppc.altivec.vperm1174 return vec_xl_len_r(uc,0);1175}1176void test113(void) {1177// CHECK-BE: @llvm.ppc.altivec.lvsl(ptr %{{.+}}1178// CHECK-BE: @llvm.ppc.altivec.vperm1179// CHECK-BE: @llvm.ppc.vsx.stxvll(<4 x i32> %{{.+}}, ptr %{{.+}}, i641180// CHECK: @llvm.ppc.altivec.lvsl(ptr %{{.+}}1181// CHECK: @llvm.ppc.altivec.vperm1182// CHECK: @llvm.ppc.vsx.stxvll(<4 x i32> %{{.+}}, ptr %{{.+}}, i641183 return vec_xst_len_r(vuca,uc,0);1184}1185vector float test114(void) {1186// CHECK-BE: shufflevector <8 x i16> {{.+}}, <8 x i16> {{.+}}, <8 x i32> <i32 poison, i32 0, i32 poison, i32 1, i32 poison, i32 2, i32 poison, i32 3>1187// CHECK-BE: @llvm.ppc.vsx.xvcvhpsp(<8 x i16> {{.+}})1188// CHECK-BE-NEXT: ret <4 x float>1189// CHECK: shufflevector <8 x i16> {{.+}}, <8 x i16> {{.+}}, <8 x i32> <i32 0, i32 poison, i32 1, i32 poison, i32 2, i32 poison, i32 3, i32 poison>1190// CHECK: @llvm.ppc.vsx.xvcvhpsp(<8 x i16> {{.+}})1191// CHECK-NEXT: ret <4 x float>1192 return vec_extract_fp32_from_shorth(vusa);1193}1194vector float test115(void) {1195// CHECK-BE: shufflevector <8 x i16> {{.+}}, <8 x i16> {{.+}}, <8 x i32> <i32 poison, i32 4, i32 poison, i32 5, i32 poison, i32 6, i32 poison, i32 7>1196// CHECK-BE: @llvm.ppc.vsx.xvcvhpsp(<8 x i16> {{.+}})1197// CHECK-BE-NEXT: ret <4 x float>1198// CHECK: shufflevector <8 x i16> {{.+}}, <8 x i16> {{.+}}, <8 x i32> <i32 4, i32 poison, i32 5, i32 poison, i32 6, i32 poison, i32 7, i32 poison>1199// CHECK: @llvm.ppc.vsx.xvcvhpsp(<8 x i16> {{.+}})1200// CHECK-NEXT: ret <4 x float>1201 return vec_extract_fp32_from_shortl(vusa);1202}1203vector unsigned char test116(void) {1204// CHECK-BE: [[T1:%.+]] = call <4 x i32> @llvm.ppc.vsx.xxinsertw(<4 x i32> {{.+}}, <2 x i64> {{.+}}, i32 7)1205// CHECK-BE-NEXT: bitcast <4 x i32> [[T1]] to <16 x i8>1206// CHECK: [[T1:%.+]] = shufflevector <2 x i64> {{.+}}, <2 x i64> {{.+}}, <2 x i32> <i32 1, i32 0>1207// CHECK-NEXT: [[T2:%.+]] = bitcast <2 x i64> [[T1]] to <4 x i32>1208// CHECK-NEXT: [[T3:%.+]] = call <4 x i32> @llvm.ppc.vsx.xxinsertw(<4 x i32> [[T2]], <2 x i64> {{.+}}, i32 5)1209 return vec_insert4b(vuia, vuca, 7);1210}1211vector unsigned char test117(void) {1212// CHECK-BE: [[T1:%.+]] = call <4 x i32> @llvm.ppc.vsx.xxinsertw(<4 x i32> {{.+}}, <2 x i64> {{.+}}, i32 12)1213// CHECK-BE-NEXT: bitcast <4 x i32> [[T1]] to <16 x i8>1214// CHECK: [[T1:%.+]] = shufflevector <2 x i64> {{.+}}, <2 x i64> {{.+}}, <2 x i32> <i32 1, i32 0>1215// CHECK-NEXT: [[T2:%.+]] = bitcast <2 x i64> [[T1]] to <4 x i32>1216// CHECK-NEXT: [[T3:%.+]] = call <4 x i32> @llvm.ppc.vsx.xxinsertw(<4 x i32> [[T2]], <2 x i64> {{.+}}, i32 0)1217 return vec_insert4b(vuia, vuca, 13);1218}1219vector unsigned long long test118(void) {1220// CHECK-BE: call <2 x i64> @llvm.ppc.vsx.xxextractuw(<2 x i64> {{.+}}, i32 11)1221// CHECK-BE-NEXT: ret <2 x i64>1222// CHECK: [[T1:%.+]] = call <2 x i64> @llvm.ppc.vsx.xxextractuw(<2 x i64> {{.+}}, i32 1)1223// CHECK-NEXT: shufflevector <2 x i64> [[T1]], <2 x i64> [[T1]], <2 x i32> <i32 1, i32 0>1224// CHECK-NEXT: ret <2 x i64>1225 return vec_extract4b(vuca, 11);1226}1227vector unsigned long long test119(void) {1228// CHECK-BE: call <2 x i64> @llvm.ppc.vsx.xxextractuw(<2 x i64> {{.+}}, i32 0)1229// CHECK-BE-NEXT: ret <2 x i64>1230// CHECK: [[T1:%.+]] = call <2 x i64> @llvm.ppc.vsx.xxextractuw(<2 x i64> {{.+}}, i32 12)1231// CHECK-NEXT: shufflevector <2 x i64> [[T1]], <2 x i64> [[T1]], <2 x i32> <i32 1, i32 0>1232// CHECK-NEXT: ret <2 x i64>1233 return vec_extract4b(vuca, -5);1234}1235 1236vector signed int test_vec_signexti_si_sc(void) {1237 // CHECK: @llvm.ppc.altivec.vextsb2w(<16 x i8>1238 // CHECK-NEXT: ret <4 x i32>1239 return vec_signexti(vsca);1240}1241 1242vector signed int test_vec_signexti_si_ss(void) {1243 // CHECK: @llvm.ppc.altivec.vextsh2w(<8 x i16>1244 // CHECK-NEXT: ret <4 x i32>1245 return vec_signexti(vssa);1246}1247 1248vector signed long long test_vec_signextll_sll_sc(void) {1249 // CHECK: @llvm.ppc.altivec.vextsb2d(<16 x i8>1250 // CHECK-NEXT: ret <2 x i64>1251 return vec_signextll(vsca);1252}1253 1254vector signed long long test_vec_signextll_sll_ss(void) {1255 // CHECK: @llvm.ppc.altivec.vextsh2d(<8 x i16>1256 // CHECK-NEXT: ret <2 x i64>1257 return vec_signextll(vssa);1258}1259 1260vector signed long long test_vec_signextll_sll_si(void) {1261 // CHECK: @llvm.ppc.altivec.vextsw2d(<4 x i32>1262 // CHECK-NEXT: ret <2 x i64>1263 return vec_signextll(vsia);1264}1265 1266vector unsigned long long test_vbpermd(void) {1267 // CHECK: @llvm.ppc.altivec.vbpermd(<2 x i64>1268 // CHECK-BE: @llvm.ppc.altivec.vbpermd(<2 x i64>1269 return vec_bperm(vula, vuca);1270}1271