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1// REQUIRES: powerpc-registered-target2// RUN: %clang_cc1 -flax-vector-conversions=none -target-feature \3// RUN:   +altivec -target-feature +vsx -triple powerpc64-unknown-unknown -emit-llvm \4// RUN:   -U__XL_COMPAT_ALTIVEC__ %s -o - | FileCheck %s5// RUN: %clang_cc1 -flax-vector-conversions=none -target-feature \6// RUN:   +altivec -target-feature +vsx -triple powerpc64le-unknown-unknown \7// RUN:   -emit-llvm -U__XL_COMPAT_ALTIVEC__ %s -o - | FileCheck %s -check-prefix=CHECK-LE8#include <altivec.h>9 10vector bool char vbc = { 0, 1, 0, 1, 0, 1, 0, 1,11                         0, 1, 0, 1, 0, 1, 0, 1 };12vector signed char vsc = { -8,  9, -10, 11, -12, 13, -14, 15,13                           -0,  1,  -2,  3,  -4,  5,  -6,  7};14vector unsigned char vuc = { 8,  9, 10, 11, 12, 13, 14, 15,15                             0,  1,  2,  3,  4,  5,  6,  7};16vector float vf = { -1.5, 2.5, -3.5, 4.5 };17vector double vd = { 3.5, -7.5 };18vector bool short vbs = { 0, 1, 0, 1, 0, 1, 0, 1 };19vector signed short vss = { -1, 2, -3, 4, -5, 6, -7, 8 };20vector unsigned short vus = { 0, 1, 2, 3, 4, 5, 6, 7 };21vector bool int vbi = { 0, 1, 0, 1 };22vector signed int vsi = { -1, 2, -3, 4 };23vector unsigned int vui = { 0, 1, 2, 3 };24vector bool long long vbll = { 1, 0 };25vector signed long long vsll = { 255LL, -937LL };26vector unsigned long long vull = { 1447LL, 2894LL };27double d = 23.4;28signed long long sll = 618LL;29unsigned long long ull = 618ULL;30float af[4] = {23.4f, 56.7f, 89.0f, 12.3f};31double ad[2] = {23.4, 56.7};32signed char asc[16] = { -8,  9, -10, 11, -12, 13, -14, 15,33                        -0,  1,  -2,  3,  -4,  5,  -6,  7};34unsigned char auc[16] = { 8,  9, 10, 11, 12, 13, 14, 15,35                          0,  1,  2,  3,  4,  5,  6,  7};36signed short ass[8] = { -1, 2, -3, 4, -5, 6, -7, 8 };37unsigned short aus[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };38signed int asi[4] = { -1, 2, -3, 4 };39unsigned int aui[4] = { 0, 1, 2, 3 };40signed long long asll[2] = { -1L, 2L };41unsigned long long aull[2] = { 1L, 2L };42 43vector float res_vf;44vector double res_vd;45vector bool char res_vbc;46vector signed char res_vsc;47vector unsigned char res_vuc;48vector bool short res_vbs;49vector signed short res_vss;50vector unsigned short res_vus;51vector bool int res_vbi;52vector signed int res_vsi;53vector unsigned int res_vui;54vector bool long long res_vbll;55vector signed long long res_vsll;56vector unsigned long long res_vull;57 58double res_d;59int res_i;60float res_af[4];61double res_ad[2];62signed char res_asc[16];63unsigned char res_auc[16];64signed short res_ass[8];65unsigned short res_aus[8];66signed int res_asi[4];67unsigned int res_aui[4];68 69void dummy() { }70 71void test1() {72// CHECK-LABEL: define{{.*}} void @test173// CHECK-LE-LABEL: define{{.*}} void @test174 75  res_vf = vec_abs(vf);76// CHECK: call <4 x float> @llvm.fabs.v4f32(<4 x float> %{{[0-9]*}})77// CHECK-LE: call <4 x float> @llvm.fabs.v4f32(<4 x float> %{{[0-9]*}})78 79  res_vd = vec_abs(vd);80// CHECK: call <2 x double> @llvm.fabs.v2f64(<2 x double> %{{[0-9]*}})81// CHECK-LE: call <2 x double> @llvm.fabs.v2f64(<2 x double> %{{[0-9]*}})82 83  res_vf = vec_nabs(vf);84// CHECK: [[VEC:%[0-9]+]] = call <4 x float> @llvm.fabs.v4f32(<4 x float> %{{[0-9]*}})85// CHECK-NEXT: fneg <4 x float> [[VEC]]86 87  res_vd = vec_nabs(vd);88// CHECK: [[VECD:%[0-9]+]] = call <2 x double> @llvm.fabs.v2f64(<2 x double> %{{[0-9]*}})89// CHECK: fneg <2 x double> [[VECD]]90 91  dummy();92// CHECK: call void @dummy()93// CHECK-LE: call void @dummy()94 95  res_vd = vec_add(vd, vd);96// CHECK: fadd <2 x double>97// CHECK-LE: fadd <2 x double>98 99  res_i = vec_any_ne(vf, vf);100// CHECK: @llvm.ppc.vsx.xvcmpeqsp.p101// CHECK-LE: @llvm.ppc.vsx.xvcmpeqsp.p102 103  res_i = vec_any_ne(vd, vd);104// CHECK: @llvm.ppc.vsx.xvcmpeqdp.p105// CHECK-LE: @llvm.ppc.vsx.xvcmpeqdp.p106 107  res_i = vec_any_nle(vf, vf);108// CHECK: @llvm.ppc.vsx.xvcmpgesp.p109// CHECK-LE: @llvm.ppc.vsx.xvcmpgesp.p110 111  res_i = vec_any_nle(vd, vd);112// CHECK: @llvm.ppc.vsx.xvcmpgedp.p113// CHECK-LE: @llvm.ppc.vsx.xvcmpgedp.p114 115  res_i = vec_any_nlt(vf, vf);116// CHECK: @llvm.ppc.vsx.xvcmpgtsp.p117// CHECK-LE: @llvm.ppc.vsx.xvcmpgtsp.p118 119  res_i = vec_any_nlt(vd, vd);120// CHECK: @llvm.ppc.vsx.xvcmpgtdp.p121// CHECK-LE: @llvm.ppc.vsx.xvcmpgtdp.p122 123  res_i = vec_any_nge(vf, vf);124// CHECK: @llvm.ppc.vsx.xvcmpgesp.p125// CHECK-LE: @llvm.ppc.vsx.xvcmpgesp.p126 127  res_i = vec_any_nge(vd, vd);128// CHECK: @llvm.ppc.vsx.xvcmpgedp.p129// CHECK-LE: @llvm.ppc.vsx.xvcmpgedp.p130 131  res_i = vec_any_ngt(vf, vf);132// CHECK: @llvm.ppc.vsx.xvcmpgtsp.p133// CHECK-LE: @llvm.ppc.vsx.xvcmpgtsp.p134 135  res_i = vec_any_ngt(vd, vd);136// CHECK: @llvm.ppc.vsx.xvcmpgtdp.p137// CHECK-LE: @llvm.ppc.vsx.xvcmpgtdp.p138 139  res_i = vec_any_nan(vf);140// CHECK: @llvm.ppc.vsx.xvcmpeqsp.p141// CHECK-LE: @llvm.ppc.vsx.xvcmpeqsp.p142 143  res_i = vec_any_nan(vd);144// CHECK: @llvm.ppc.vsx.xvcmpeqdp.p145// CHECK-LE: @llvm.ppc.vsx.xvcmpeqdp.p146 147  res_i = vec_any_numeric(vf);148// CHECK: @llvm.ppc.vsx.xvcmpeqsp.p149// CHECK-LE: @llvm.ppc.vsx.xvcmpeqsp.p150 151  res_i = vec_any_numeric(vd);152// CHECK: @llvm.ppc.vsx.xvcmpeqdp.p153// CHECK-LE: @llvm.ppc.vsx.xvcmpeqdp.p154 155  dummy();156// CHECK: call void @dummy()157// CHECK-LE: call void @dummy()158 159  res_i = vec_all_ne(vf, vf);160// CHECK: @llvm.ppc.vsx.xvcmpeqsp.p161// CHECK-LE: @llvm.ppc.vsx.xvcmpeqsp.p162 163  res_i = vec_all_ne(vd, vd);164// CHECK: @llvm.ppc.vsx.xvcmpeqdp.p165// CHECK-LE: @llvm.ppc.vsx.xvcmpeqdp.p166 167  res_i = vec_all_nle(vf, vf);168// CHECK: @llvm.ppc.vsx.xvcmpgesp.p169// CHECK-LE: @llvm.ppc.vsx.xvcmpgesp.p170 171  res_i = vec_all_nle(vd, vd);172// CHECK: @llvm.ppc.vsx.xvcmpgedp.p173// CHECK-LE: @llvm.ppc.vsx.xvcmpgedp.p174 175  res_i = vec_all_nlt(vf, vf);176// CHECK: @llvm.ppc.vsx.xvcmpgtsp.p177// CHECK-LE: @llvm.ppc.vsx.xvcmpgtsp.p178 179  res_i = vec_all_nlt(vd, vd);180// CHECK: @llvm.ppc.vsx.xvcmpgtdp.p181// CHECK-LE: @llvm.ppc.vsx.xvcmpgtdp.p182 183  res_i = vec_all_nge(vf, vf);184// CHECK: @llvm.ppc.vsx.xvcmpgesp.p185// CHECK-LE: @llvm.ppc.vsx.xvcmpgesp.p186 187  res_i = vec_all_nge(vd, vd);188// CHECK: @llvm.ppc.vsx.xvcmpgedp.p189// CHECK-LE: @llvm.ppc.vsx.xvcmpgedp.p190 191  res_i = vec_all_ngt(vf, vf);192// CHECK: @llvm.ppc.vsx.xvcmpgtsp.p193// CHECK-LE: @llvm.ppc.vsx.xvcmpgtsp.p194 195  res_i = vec_all_ngt(vd, vd);196// CHECK: @llvm.ppc.vsx.xvcmpgtdp.p197// CHECK-LE: @llvm.ppc.vsx.xvcmpgtdp.p198 199  res_i = vec_all_nan(vf);200// CHECK: @llvm.ppc.vsx.xvcmpeqsp.p201// CHECK-LE: @llvm.ppc.vsx.xvcmpeqsp.p202 203  res_i = vec_all_nan(vd);204// CHECK: @llvm.ppc.vsx.xvcmpeqdp.p205// CHECK-LE: @llvm.ppc.vsx.xvcmpeqdp.p206 207  res_i = vec_all_numeric(vf);208// CHECK: @llvm.ppc.vsx.xvcmpeqsp.p209// CHECK-LE: @llvm.ppc.vsx.xvcmpeqsp.p210 211  res_i = vec_all_numeric(vd);212// CHECK: @llvm.ppc.vsx.xvcmpeqdp.p213// CHECK-LE: @llvm.ppc.vsx.xvcmpeqdp.p214 215  dummy();216// CHECK: call void @dummy()217// CHECK-LE: call void @dummy()218 219  res_vd = vec_and(vbll, vd);220// CHECK: and <2 x i64>221// CHECK: bitcast <2 x i64> %{{[0-9]*}} to <2 x double>222// CHECK-LE: and <2 x i64>223// CHECK-LE: bitcast <2 x i64> %{{[0-9]*}} to <2 x double>224 225  res_vd = vec_and(vd, vbll);226// CHECK: and <2 x i64>227// CHECK: bitcast <2 x i64> %{{[0-9]*}} to <2 x double>228// CHECK-LE: and <2 x i64>229// CHECK-LE: bitcast <2 x i64> %{{[0-9]*}} to <2 x double>230 231  res_vd = vec_and(vd, vd);232// CHECK: and <2 x i64>233// CHECK: bitcast <2 x i64> %{{[0-9]*}} to <2 x double>234// CHECK-LE: and <2 x i64>235// CHECK-LE: bitcast <2 x i64> %{{[0-9]*}} to <2 x double>236 237  dummy();238// CHECK: call void @dummy()239// CHECK-LE: call void @dummy()240 241  res_vd = vec_andc(vbll, vd);242// CHECK: bitcast <2 x double> %{{[0-9]*}} to <2 x i64>243// CHECK: xor <2 x i64> %{{[0-9]*}}, splat (i64 -1)244// CHECK: and <2 x i64>245// CHECK: bitcast <2 x i64> %{{[0-9]*}} to <2 x double>246// CHECK-LE: bitcast <2 x double> %{{[0-9]*}} to <2 x i64>247// CHECK-LE: xor <2 x i64> %{{[0-9]*}}, splat (i64 -1)248// CHECK-LE: and <2 x i64>249// CHECK-LE: bitcast <2 x i64> %{{[0-9]*}} to <2 x double>250 251  dummy();252// CHECK: call void @dummy()253// CHECK-LE: call void @dummy()254 255  res_vd = vec_andc(vd, vbll);256// CHECK: bitcast <2 x double> %{{[0-9]*}} to <2 x i64>257// CHECK: xor <2 x i64> %{{[0-9]*}}, splat (i64 -1)258// CHECK: and <2 x i64>259// CHECK: bitcast <2 x i64> %{{[0-9]*}} to <2 x double>260// CHECK-LE: bitcast <2 x double> %{{[0-9]*}} to <2 x i64>261// CHECK-LE: xor <2 x i64> %{{[0-9]*}}, splat (i64 -1)262// CHECK-LE: and <2 x i64>263// CHECK-LE: bitcast <2 x i64> %{{[0-9]*}} to <2 x double>264 265  dummy();266// CHECK: call void @dummy()267 268  res_vd = vec_andc(vd, vd);269// CHECK: bitcast <2 x double> %{{[0-9]*}} to <2 x i64>270// CHECK: xor <2 x i64> %{{[0-9]*}}, splat (i64 -1)271// CHECK: and <2 x i64>272// CHECK: bitcast <2 x i64> %{{[0-9]*}} to <2 x double>273 274  dummy();275// CHECK: call void @dummy()276// CHECK-LE: call void @dummy()277 278  res_vd = vec_ceil(vd);279// CHECK: call <2 x double> @llvm.ceil.v2f64(<2 x double> %{{[0-9]*}})280// CHECK-LE: call <2 x double> @llvm.ceil.v2f64(<2 x double> %{{[0-9]*}})281 282  res_vf = vec_ceil(vf);283// CHECK: call <4 x float> @llvm.ceil.v4f32(<4 x float> %{{[0-9]*}})284// CHECK-LE: call <4 x float> @llvm.ceil.v4f32(<4 x float> %{{[0-9]*}})285 286  res_vd = vec_roundp(vd);287// CHECK: call <2 x double> @llvm.ceil.v2f64(<2 x double> %{{[0-9]*}})288// CHECK-LE: call <2 x double> @llvm.ceil.v2f64(<2 x double> %{{[0-9]*}})289 290  res_vf = vec_roundp(vf);291// CHECK: call <4 x float> @llvm.ceil.v4f32(<4 x float> %{{[0-9]*}})292// CHECK-LE: call <4 x float> @llvm.ceil.v4f32(<4 x float> %{{[0-9]*}})293 294  res_vbll = vec_cmpeq(vd, vd);295// CHECK: call <2 x i64> @llvm.ppc.vsx.xvcmpeqdp(<2 x double> %{{[0-9]*}}, <2 x double> %{{[0-9]*}})296// CHECK-LE: call <2 x i64> @llvm.ppc.vsx.xvcmpeqdp(<2 x double> %{{[0-9]*}}, <2 x double> %{{[0-9]*}})297 298  res_vbi = vec_cmpeq(vf, vf);299// CHECK: call <4 x i32> @llvm.ppc.vsx.xvcmpeqsp(<4 x float> %{{[0-9]*}}, <4 x float> %{{[0-9]*}})300// CHECK-LE: call <4 x i32> @llvm.ppc.vsx.xvcmpeqsp(<4 x float> %{{[0-9]*}}, <4 x float> %{{[0-9]*}})301 302  res_vbll = vec_cmpge(vd, vd);303// CHECK: call <2 x i64> @llvm.ppc.vsx.xvcmpgedp(<2 x double> %{{[0-9]*}}, <2 x double> %{{[0-9]*}})304// CHECK-LE: call <2 x i64> @llvm.ppc.vsx.xvcmpgedp(<2 x double> %{{[0-9]*}}, <2 x double> %{{[0-9]*}})305 306  res_vbi = vec_cmpge(vf, vf);307// CHECK: call <4 x i32> @llvm.ppc.vsx.xvcmpgesp(<4 x float> %{{[0-9]*}}, <4 x float> %{{[0-9]*}})308// CHECK-LE: call <4 x i32> @llvm.ppc.vsx.xvcmpgesp(<4 x float> %{{[0-9]*}}, <4 x float> %{{[0-9]*}})309 310  res_vbll = vec_cmpgt(vd, vd);311// CHECK: call <2 x i64> @llvm.ppc.vsx.xvcmpgtdp(<2 x double> %{{[0-9]*}}, <2 x double> %{{[0-9]*}})312// CHECK-LE: call <2 x i64> @llvm.ppc.vsx.xvcmpgtdp(<2 x double> %{{[0-9]*}}, <2 x double> %{{[0-9]*}})313 314  res_vbi = vec_cmpgt(vf, vf);315// CHECK: call <4 x i32> @llvm.ppc.vsx.xvcmpgtsp(<4 x float> %{{[0-9]*}}, <4 x float> %{{[0-9]*}})316// CHECK-LE: call <4 x i32> @llvm.ppc.vsx.xvcmpgtsp(<4 x float> %{{[0-9]*}}, <4 x float> %{{[0-9]*}})317 318  res_vbll = vec_cmple(vd, vd);319// CHECK: call <2 x i64> @llvm.ppc.vsx.xvcmpgedp(<2 x double> %{{[0-9]*}}, <2 x double> %{{[0-9]*}})320// CHECK-LE: call <2 x i64> @llvm.ppc.vsx.xvcmpgedp(<2 x double> %{{[0-9]*}}, <2 x double> %{{[0-9]*}})321 322  res_vbi = vec_cmple(vf, vf);323// CHECK: call <4 x i32> @llvm.ppc.vsx.xvcmpgesp(<4 x float> %{{[0-9]*}}, <4 x float> %{{[0-9]*}})324// CHECK-LE: call <4 x i32> @llvm.ppc.vsx.xvcmpgesp(<4 x float> %{{[0-9]*}}, <4 x float> %{{[0-9]*}})325 326  res_vbll = vec_cmplt(vd, vd);327// CHECK: call <2 x i64> @llvm.ppc.vsx.xvcmpgtdp(<2 x double> %{{[0-9]*}}, <2 x double> %{{[0-9]*}})328// CHECK-LE: call <2 x i64> @llvm.ppc.vsx.xvcmpgtdp(<2 x double> %{{[0-9]*}}, <2 x double> %{{[0-9]*}})329 330  res_vbi = vec_cmplt(vf, vf);331// CHECK: call <4 x i32> @llvm.ppc.vsx.xvcmpgtsp(<4 x float> %{{[0-9]*}}, <4 x float> %{{[0-9]*}})332// CHECK-LE: call <4 x i32> @llvm.ppc.vsx.xvcmpgtsp(<4 x float> %{{[0-9]*}}, <4 x float> %{{[0-9]*}})333 334  /* vec_cpsgn */335  res_vf = vec_cpsgn(vf, vf);336// CHECK: call <4 x float> @llvm.copysign.v4f32(<4 x float> %{{.+}}, <4 x float> %{{.+}})337// CHECK-LE: call <4 x float> @llvm.copysign.v4f32(<4 x float> %{{.+}}, <4 x float> %{{.+}})338 339  res_vd = vec_cpsgn(vd, vd);340// CHECK: call <2 x double> @llvm.copysign.v2f64(<2 x double> %{{.+}}, <2 x double> %{{.+}})341// CHECK-LE: call <2 x double> @llvm.copysign.v2f64(<2 x double> %{{.+}}, <2 x double> %{{.+}})342 343  /* vec_div */344  res_vsll = vec_div(vsll, vsll);345// CHECK: sdiv <2 x i64>346// CHECK-LE: sdiv <2 x i64>347 348  res_vull = vec_div(vull, vull);349// CHECK: udiv <2 x i64>350// CHECK-LE: udiv <2 x i64>351 352  res_vf = vec_div(vf, vf);353// CHECK: fdiv <4 x float>354// CHECK-LE: fdiv <4 x float>355 356  res_vd = vec_div(vd, vd);357// CHECK: fdiv <2 x double>358// CHECK-LE: fdiv <2 x double>359 360  /* vec_max */361  res_vf = vec_max(vf, vf);362// CHECK: @llvm.ppc.vsx.xvmaxsp363// CHECK-LE: @llvm.ppc.vsx.xvmaxsp364 365  res_vd = vec_max(vd, vd);366// CHECK: @llvm.ppc.vsx.xvmaxdp367// CHECK-LE: @llvm.ppc.vsx.xvmaxdp368 369  res_vf = vec_vmaxfp(vf, vf);370// CHECK: @llvm.ppc.vsx.xvmaxsp371// CHECK-LE: @llvm.ppc.vsx.xvmaxsp372 373  /* vec_min */374  res_vf = vec_min(vf, vf);375// CHECK: @llvm.ppc.vsx.xvminsp376// CHECK-LE: @llvm.ppc.vsx.xvminsp377 378  res_vd = vec_min(vd, vd);379// CHECK: @llvm.ppc.vsx.xvmindp380// CHECK-LE: @llvm.ppc.vsx.xvmindp381 382  res_vf = vec_vminfp(vf, vf);383// CHECK: @llvm.ppc.vsx.xvminsp384// CHECK-LE: @llvm.ppc.vsx.xvminsp385 386  res_d = __builtin_vsx_xsmaxdp(d, d);387// CHECK: @llvm.ppc.vsx.xsmaxdp388// CHECK-LE: @llvm.ppc.vsx.xsmaxdp389 390  res_d = __builtin_vsx_xsmindp(d, d);391// CHECK: @llvm.ppc.vsx.xsmindp392// CHECK-LE: @llvm.ppc.vsx.xsmindp393 394  /* vec_perm */395  res_vsll = vec_perm(vsll, vsll, vuc);396// CHECK: @llvm.ppc.altivec.vperm397// CHECK-LE: @llvm.ppc.altivec.vperm398 399  res_vull = vec_perm(vull, vull, vuc);400// CHECK: @llvm.ppc.altivec.vperm401// CHECK-LE: @llvm.ppc.altivec.vperm402 403  res_vbll = vec_perm(vbll, vbll, vuc);404// CHECK: [[T1:%.+]] = bitcast <2 x i64> {{.+}} to <4 x i32>405// CHECK: [[T2:%.+]] = bitcast <2 x i64> {{.+}} to <4 x i32>406// CHECK: call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> [[T1]], <4 x i32> [[T2]], <16 x i8>407// CHECK-LE: xor <16 x i8>408// CHECK-LE: [[T1:%.+]] = bitcast <2 x i64> {{.+}} to <4 x i32>409// CHECK-LE: [[T2:%.+]] = bitcast <2 x i64> {{.+}} to <4 x i32>410// CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> [[T1]], <4 x i32> [[T2]], <16 x i8>411 412  res_vf = vec_round(vf);413// CHECK: call <4 x float> @llvm.ppc.altivec.vrfin(<4 x float>414// CHECK-LE: call <4 x float> @llvm.ppc.altivec.vrfin(<4 x float>415 416  res_vd = vec_perm(vd, vd, vuc);417// CHECK: @llvm.ppc.altivec.vperm418// CHECK-LE: @llvm.ppc.altivec.vperm419 420  res_vd = vec_splat(vd, 1);421// CHECK: [[T1:%.+]] = bitcast <2 x double> {{.+}} to <4 x i32>422// CHECK: [[T2:%.+]] = bitcast <2 x double> {{.+}} to <4 x i32>423// CHECK: call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> [[T1]], <4 x i32> [[T2]], <16 x i8>424// CHECK-LE: xor <16 x i8>425// CHECK-LE: [[T1:%.+]] = bitcast <2 x double> {{.+}} to <4 x i32>426// CHECK-LE: [[T2:%.+]] = bitcast <2 x double> {{.+}} to <4 x i32>427// CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> [[T1]], <4 x i32> [[T2]], <16 x i8>428 429  res_vbll = vec_splat(vbll, 1);430// CHECK: [[T1:%.+]] = bitcast <2 x i64> {{.+}} to <4 x i32>431// CHECK: [[T2:%.+]] = bitcast <2 x i64> {{.+}} to <4 x i32>432// CHECK: call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> [[T1]], <4 x i32> [[T2]], <16 x i8>433// CHECK-LE: xor <16 x i8>434// CHECK-LE: [[T1:%.+]] = bitcast <2 x i64> {{.+}} to <4 x i32>435// CHECK-LE: [[T2:%.+]] = bitcast <2 x i64> {{.+}} to <4 x i32>436// CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> [[T1]], <4 x i32> [[T2]], <16 x i8>437 438  res_vsll =  vec_splat(vsll, 1);439// CHECK: [[T1:%.+]] = bitcast <2 x i64> {{.+}} to <4 x i32>440// CHECK: [[T2:%.+]] = bitcast <2 x i64> {{.+}} to <4 x i32>441// CHECK: call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> [[T1]], <4 x i32> [[T2]], <16 x i8>442// CHECK-LE: xor <16 x i8>443// CHECK-LE: [[T1:%.+]] = bitcast <2 x i64> {{.+}} to <4 x i32>444// CHECK-LE: [[T2:%.+]] = bitcast <2 x i64> {{.+}} to <4 x i32>445// CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> [[T1]], <4 x i32> [[T2]], <16 x i8>446 447  res_vull =  vec_splat(vull, 1);448// CHECK: [[T1:%.+]] = bitcast <2 x i64> {{.+}} to <4 x i32>449// CHECK: [[T2:%.+]] = bitcast <2 x i64> {{.+}} to <4 x i32>450// CHECK: call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> [[T1]], <4 x i32> [[T2]], <16 x i8>451// CHECK-LE: xor <16 x i8>452// CHECK-LE: [[T1:%.+]] = bitcast <2 x i64> {{.+}} to <4 x i32>453// CHECK-LE: [[T2:%.+]] = bitcast <2 x i64> {{.+}} to <4 x i32>454// CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> [[T1]], <4 x i32> [[T2]], <16 x i8>455 456  res_vsi = vec_pack(vsll, vsll);457// CHECK: @llvm.ppc.altivec.vperm458// CHECK-LE: @llvm.ppc.altivec.vperm459 460  res_vui = vec_pack(vull, vull);461// CHECK: @llvm.ppc.altivec.vperm462// CHECK-LE: @llvm.ppc.altivec.vperm463 464  res_vbi = vec_pack(vbll, vbll);465// CHECK: @llvm.ppc.altivec.vperm466// CHECK-LE: @llvm.ppc.altivec.vperm467 468  res_vsll = vec_vperm(vsll, vsll, vuc);469// CHECK: @llvm.ppc.altivec.vperm470// CHECK-LE: @llvm.ppc.altivec.vperm471 472  res_vull = vec_vperm(vull, vull, vuc);473// CHECK: @llvm.ppc.altivec.vperm474// CHECK-LE: @llvm.ppc.altivec.vperm475 476  res_vd = vec_vperm(vd, vd, vuc);477// CHECK: @llvm.ppc.altivec.vperm478// CHECK-LE: @llvm.ppc.altivec.vperm479 480  /* vec_vsx_ld */481 482  res_vbi = vec_vsx_ld(0, &vbi);483// CHECK: @llvm.ppc.vsx.lxvw4x484// CHECK-LE: @llvm.ppc.vsx.lxvw4x485 486  res_vsi = vec_vsx_ld(0, &vsi);487// CHECK: @llvm.ppc.vsx.lxvw4x488// CHECK-LE: @llvm.ppc.vsx.lxvw4x489 490  res_vsi = vec_vsx_ld(0, asi);491// CHECK: @llvm.ppc.vsx.lxvw4x492// CHECK-LE: @llvm.ppc.vsx.lxvw4x493 494  res_vui = vec_vsx_ld(0, &vui);495// CHECK: @llvm.ppc.vsx.lxvw4x496// CHECK-LE: @llvm.ppc.vsx.lxvw4x497 498  res_vui = vec_vsx_ld(0, aui);499// CHECK: @llvm.ppc.vsx.lxvw4x500// CHECK-LE: @llvm.ppc.vsx.lxvw4x501 502  res_vf = vec_vsx_ld (0, &vf);503// CHECK: @llvm.ppc.vsx.lxvw4x504// CHECK-LE: @llvm.ppc.vsx.lxvw4x505 506  res_vf = vec_vsx_ld (0, af);507// CHECK: @llvm.ppc.vsx.lxvw4x508// CHECK-LE: @llvm.ppc.vsx.lxvw4x509 510  res_vsll = vec_vsx_ld(0, &vsll);511// CHECK: @llvm.ppc.vsx.lxvd2x512// CHECK-LE: @llvm.ppc.vsx.lxvd2x513 514  res_vull = vec_vsx_ld(0, &vull);515// CHECK: @llvm.ppc.vsx.lxvd2x516// CHECK-LE: @llvm.ppc.vsx.lxvd2x517 518  res_vd = vec_vsx_ld(0, &vd);519// CHECK: @llvm.ppc.vsx.lxvd2x520// CHECK-LE: @llvm.ppc.vsx.lxvd2x521 522  res_vd = vec_vsx_ld(0, ad);523// CHECK: @llvm.ppc.vsx.lxvd2x524// CHECK-LE: @llvm.ppc.vsx.lxvd2x525 526  res_vbs = vec_vsx_ld(0, &vbs);527// CHECK: @llvm.ppc.vsx.lxvw4x528// CHECK-LE: @llvm.ppc.vsx.lxvw4x529 530  res_vss = vec_vsx_ld(0, &vss);531// CHECK: @llvm.ppc.vsx.lxvw4x532// CHECK-LE: @llvm.ppc.vsx.lxvw4x533 534  res_vss = vec_vsx_ld(0, ass);535// CHECK: @llvm.ppc.vsx.lxvw4x536// CHECK-LE: @llvm.ppc.vsx.lxvw4x537 538  res_vus = vec_vsx_ld(0, &vus);539// CHECK: @llvm.ppc.vsx.lxvw4x540// CHECK-LE: @llvm.ppc.vsx.lxvw4x541 542  res_vus = vec_vsx_ld(0, aus);543// CHECK: @llvm.ppc.vsx.lxvw4x544// CHECK-LE: @llvm.ppc.vsx.lxvw4x545 546  res_vbc = vec_vsx_ld(0, &vbc);547// CHECK: @llvm.ppc.vsx.lxvw4x548// CHECK-LE: @llvm.ppc.vsx.lxvw4x549 550  res_vsc = vec_vsx_ld(0, &vsc);551// CHECK: @llvm.ppc.vsx.lxvw4x552// CHECK-LE: @llvm.ppc.vsx.lxvw4x553 554  res_vuc = vec_vsx_ld(0, &vuc);555// CHECK: @llvm.ppc.vsx.lxvw4x556// CHECK-LE: @llvm.ppc.vsx.lxvw4x557 558  res_vsc = vec_vsx_ld(0, asc);559// CHECK: @llvm.ppc.vsx.lxvw4x560// CHECK-LE: @llvm.ppc.vsx.lxvw4x561 562  res_vuc = vec_vsx_ld(0, auc);563// CHECK: @llvm.ppc.vsx.lxvw4x564// CHECK-LE: @llvm.ppc.vsx.lxvw4x565 566  /* vec_vsx_st */567 568  vec_vsx_st(vbi, 0, &res_vbi);569// CHECK: @llvm.ppc.vsx.stxvw4x570// CHECK-LE: @llvm.ppc.vsx.stxvw4x571 572  vec_vsx_st(vbi, 0, res_aui);573// CHECK: @llvm.ppc.vsx.stxvw4x574// CHECK-LE: @llvm.ppc.vsx.stxvw4x575 576  vec_vsx_st(vbi, 0, res_asi);577// CHECK: @llvm.ppc.vsx.stxvw4x578// CHECK-LE: @llvm.ppc.vsx.stxvw4x579 580  vec_vsx_st(vsi, 0, &res_vsi);581// CHECK: @llvm.ppc.vsx.stxvw4x582// CHECK-LE: @llvm.ppc.vsx.stxvw4x583 584  vec_vsx_st(vsi, 0, res_asi);585// CHECK: @llvm.ppc.vsx.stxvw4x586// CHECK-LE: @llvm.ppc.vsx.stxvw4x587 588  vec_vsx_st(vui, 0, &res_vui);589// CHECK: @llvm.ppc.vsx.stxvw4x590// CHECK-LE: @llvm.ppc.vsx.stxvw4x591 592  vec_vsx_st(vui, 0, res_aui);593// CHECK: @llvm.ppc.vsx.stxvw4x594// CHECK-LE: @llvm.ppc.vsx.stxvw4x595 596  vec_vsx_st(vf, 0, &res_vf);597// CHECK: @llvm.ppc.vsx.stxvw4x598// CHECK-LE: @llvm.ppc.vsx.stxvw4x599 600  vec_vsx_st(vf, 0, res_af);601// CHECK: @llvm.ppc.vsx.stxvw4x602// CHECK-LE: @llvm.ppc.vsx.stxvw4x603 604  vec_vsx_st(vsll, 0, &res_vsll);605// CHECK: @llvm.ppc.vsx.stxvd2x606// CHECK-LE: @llvm.ppc.vsx.stxvd2x607 608  vec_vsx_st(vull, 0, &res_vull);609// CHECK: @llvm.ppc.vsx.stxvd2x610// CHECK-LE: @llvm.ppc.vsx.stxvd2x611 612  vec_vsx_st(vd, 0, &res_vd);613// CHECK: @llvm.ppc.vsx.stxvd2x614// CHECK-LE: @llvm.ppc.vsx.stxvd2x615 616  vec_vsx_st(vd, 0, res_ad);617// CHECK: @llvm.ppc.vsx.stxvd2x618// CHECK-LE: @llvm.ppc.vsx.stxvd2x619 620  vec_vsx_st(vbs, 0, &res_vbs);621// CHECK: @llvm.ppc.vsx.stxvw4x622// CHECK-LE: @llvm.ppc.vsx.stxvw4x623 624  vec_vsx_st(vbs, 0, res_aus);625// CHECK: @llvm.ppc.vsx.stxvw4x626// CHECK-LE: @llvm.ppc.vsx.stxvw4x627 628  vec_vsx_st(vbs, 0, res_ass);629// CHECK: @llvm.ppc.vsx.stxvw4x630// CHECK-LE: @llvm.ppc.vsx.stxvw4x631 632  vec_vsx_st(vss, 0, &res_vss);633// CHECK: @llvm.ppc.vsx.stxvw4x634// CHECK-LE: @llvm.ppc.vsx.stxvw4x635 636  vec_vsx_st(vss, 0, res_ass);637// CHECK: @llvm.ppc.vsx.stxvw4x638// CHECK-LE: @llvm.ppc.vsx.stxvw4x639 640  vec_vsx_st(vus, 0, &res_vus);641// CHECK: @llvm.ppc.vsx.stxvw4x642// CHECK-LE: @llvm.ppc.vsx.stxvw4x643 644  vec_vsx_st(vus, 0, res_aus);645// CHECK: @llvm.ppc.vsx.stxvw4x646// CHECK-LE: @llvm.ppc.vsx.stxvw4x647 648  vec_vsx_st(vsc, 0, &res_vsc);649// CHECK: @llvm.ppc.vsx.stxvw4x650// CHECK-LE: @llvm.ppc.vsx.stxvw4x651 652  vec_vsx_st(vsc, 0, res_asc);653// CHECK: @llvm.ppc.vsx.stxvw4x654// CHECK-LE: @llvm.ppc.vsx.stxvw4x655 656  vec_vsx_st(vuc, 0, &res_vuc);657// CHECK: @llvm.ppc.vsx.stxvw4x658// CHECK-LE: @llvm.ppc.vsx.stxvw4x659 660  vec_vsx_st(vuc, 0, res_auc);661// CHECK: @llvm.ppc.vsx.stxvw4x662// CHECK-LE: @llvm.ppc.vsx.stxvw4x663 664  vec_vsx_st(vbc, 0, &res_vbc);665// CHECK: @llvm.ppc.vsx.stxvw4x666// CHECK-LE: @llvm.ppc.vsx.stxvw4x667 668  vec_vsx_st(vbc, 0, res_asc);669// CHECK: @llvm.ppc.vsx.stxvw4x670// CHECK-LE: @llvm.ppc.vsx.stxvw4x671 672  vec_vsx_st(vbc, 0, res_auc);673// CHECK: @llvm.ppc.vsx.stxvw4x674// CHECK-LE: @llvm.ppc.vsx.stxvw4x675 676  /* vec_and */677  res_vsll = vec_and(vsll, vsll);678// CHECK: and <2 x i64>679// CHECK-LE: and <2 x i64>680 681  res_vsll = vec_and(vbll, vsll);682// CHECK: and <2 x i64>683// CHECK-LE: and <2 x i64>684 685  res_vsll = vec_and(vsll, vbll);686// CHECK: and <2 x i64>687// CHECK-LE: and <2 x i64>688 689  res_vull = vec_and(vull, vull);690// CHECK: and <2 x i64>691// CHECK-LE: and <2 x i64>692 693  res_vull = vec_and(vbll, vull);694// CHECK: and <2 x i64>695// CHECK-LE: and <2 x i64>696 697  res_vull = vec_and(vull, vbll);698// CHECK: and <2 x i64>699// CHECK-LE: and <2 x i64>700 701  res_vbll = vec_and(vbll, vbll);702// CHECK: and <2 x i64>703// CHECK-LE: and <2 x i64>704 705  /* vec_vand */706  res_vsll = vec_vand(vsll, vsll);707// CHECK: and <2 x i64>708// CHECK-LE: and <2 x i64>709 710  res_vsll = vec_vand(vbll, vsll);711// CHECK: and <2 x i64>712// CHECK-LE: and <2 x i64>713 714  res_vsll = vec_vand(vsll, vbll);715// CHECK: and <2 x i64>716// CHECK-LE: and <2 x i64>717 718  res_vull = vec_vand(vull, vull);719// CHECK: and <2 x i64>720// CHECK-LE: and <2 x i64>721 722  res_vull = vec_vand(vbll, vull);723// CHECK: and <2 x i64>724// CHECK-LE: and <2 x i64>725 726  res_vull = vec_vand(vull, vbll);727// CHECK: and <2 x i64>728// CHECK-LE: and <2 x i64>729 730  res_vbll = vec_vand(vbll, vbll);731// CHECK: and <2 x i64>732// CHECK-LE: and <2 x i64>733 734  /* vec_andc */735  res_vsll = vec_andc(vsll, vsll);736// CHECK: xor <2 x i64>737// CHECK: and <2 x i64>738// CHECK-LE: xor <2 x i64>739// CHECK-LE: and <2 x i64>740 741  res_vsll = vec_andc(vbll, vsll);742// CHECK: xor <2 x i64>743// CHECK: and <2 x i64>744// CHECK-LE: xor <2 x i64>745// CHECK-LE: and <2 x i64>746 747  res_vsll = vec_andc(vsll, vbll);748// CHECK: xor <2 x i64>749// CHECK: and <2 x i64>750// CHECK-LE: xor <2 x i64>751// CHECK-LE: and <2 x i64>752 753  res_vull = vec_andc(vull, vull);754// CHECK: xor <2 x i64>755// CHECK: and <2 x i64>756// CHECK-LE: xor <2 x i64>757// CHECK-LE: and <2 x i64>758 759  res_vull = vec_andc(vbll, vull);760// CHECK: xor <2 x i64>761// CHECK: and <2 x i64>762// CHECK-LE: xor <2 x i64>763// CHECK-LE: and <2 x i64>764 765  res_vull = vec_andc(vull, vbll);766// CHECK: xor <2 x i64>767// CHECK: and <2 x i64>768// CHECK-LE: xor <2 x i64>769// CHECK-LE: and <2 x i64>770 771  res_vbll = vec_andc(vbll, vbll);772// CHECK: xor <2 x i64>773// CHECK: and <2 x i64>774// CHECK-LE: xor <2 x i64>775// CHECK-LE: and <2 x i64>776 777  res_vf = vec_floor(vf);778// CHECK: call <4 x float> @llvm.floor.v4f32(<4 x float> %{{[0-9]+}})779// CHECK-LE: call <4 x float> @llvm.floor.v4f32(<4 x float> %{{[0-9]+}})780 781  res_vd = vec_floor(vd);782// CHECK: call <2 x double> @llvm.floor.v2f64(<2 x double> %{{[0-9]+}})783// CHECK-LE: call <2 x double> @llvm.floor.v2f64(<2 x double> %{{[0-9]+}})784 785  res_vf = vec_roundm(vf);786// CHECK: call <4 x float> @llvm.floor.v4f32(<4 x float> %{{[0-9]+}})787// CHECK-LE: call <4 x float> @llvm.floor.v4f32(<4 x float> %{{[0-9]+}})788 789  res_vd = vec_roundm(vd);790// CHECK: call <2 x double> @llvm.floor.v2f64(<2 x double> %{{[0-9]+}})791// CHECK-LE: call <2 x double> @llvm.floor.v2f64(<2 x double> %{{[0-9]+}})792 793  res_vf = vec_madd(vf, vf, vf);794// CHECK: call <4 x float> @llvm.fma.v4f32(<4 x float> %{{[0-9]+}}, <4 x float> %{{[0-9]+}}, <4 x float> %{{[0-9]+}})795// CHECK-LE: call <4 x float> @llvm.fma.v4f32(<4 x float> %{{[0-9]+}}, <4 x float> %{{[0-9]+}}, <4 x float> %{{[0-9]+}})796 797  res_vd = vec_madd(vd, vd, vd);798// CHECK: call <2 x double> @llvm.fma.v2f64(<2 x double> %{{[0-9]+}}, <2 x double> %{{[0-9]+}}, <2 x double> %{{[0-9]+}})799// CHECK-LE: call <2 x double> @llvm.fma.v2f64(<2 x double> %{{[0-9]+}}, <2 x double> %{{[0-9]+}}, <2 x double> %{{[0-9]+}})800 801  /* vec_mergeh */802  res_vsll = vec_mergeh(vsll, vsll);803// CHECK: @llvm.ppc.altivec.vperm804// CHECK-LE: @llvm.ppc.altivec.vperm805 806  res_vsll = vec_mergeh(vsll, vbll);807// CHECK: @llvm.ppc.altivec.vperm808// CHECK-LE: @llvm.ppc.altivec.vperm809 810  res_vsll = vec_mergeh(vbll, vsll);811// CHECK: @llvm.ppc.altivec.vperm812// CHECK-LE: @llvm.ppc.altivec.vperm813 814  res_vull = vec_mergeh(vull, vull);815// CHECK: @llvm.ppc.altivec.vperm816// CHECK-LE: @llvm.ppc.altivec.vperm817 818  res_vull = vec_mergeh(vull, vbll);819// CHECK: @llvm.ppc.altivec.vperm820// CHECK-LE: @llvm.ppc.altivec.vperm821 822  res_vull = vec_mergeh(vbll, vull);823// CHECK: @llvm.ppc.altivec.vperm824// CHECK-LE: @llvm.ppc.altivec.vperm825 826  /* vec_mergel */827  res_vsll = vec_mergel(vsll, vsll);828// CHECK: @llvm.ppc.altivec.vperm829// CHECK-LE: @llvm.ppc.altivec.vperm830 831  res_vsll = vec_mergel(vsll, vbll);832// CHECK: @llvm.ppc.altivec.vperm833// CHECK-LE: @llvm.ppc.altivec.vperm834 835  res_vsll = vec_mergel(vbll, vsll);836// CHECK: @llvm.ppc.altivec.vperm837// CHECK-LE: @llvm.ppc.altivec.vperm838 839  res_vull = vec_mergel(vull, vull);840// CHECK: @llvm.ppc.altivec.vperm841// CHECK-LE: @llvm.ppc.altivec.vperm842 843  res_vull = vec_mergel(vull, vbll);844// CHECK: @llvm.ppc.altivec.vperm845// CHECK-LE: @llvm.ppc.altivec.vperm846 847  res_vull = vec_mergel(vbll, vull);848// CHECK: @llvm.ppc.altivec.vperm849// CHECK-LE: @llvm.ppc.altivec.vperm850 851  /* vec_msub */852  res_vf = vec_msub(vf, vf, vf);853// CHECK: fneg <4 x float> %{{[0-9]+}}854// CHECK-NEXT: call <4 x float> @llvm.fma.v4f32(<4 x float> %{{[0-9]+}}, <4 x float> %{{[0-9]+}}, <4 x float>855// CHECK-LE: fneg <4 x float> %{{[0-9]+}}856// CHECK-LE-NEXT: call <4 x float> @llvm.fma.v4f32(<4 x float> %{{[0-9]+}}, <4 x float> %{{[0-9]+}}, <4 x float>857 858  res_vd = vec_msub(vd, vd, vd);859// CHECK: fneg <2 x double> %{{[0-9]+}}860// CHECK-NEXT: call <2 x double> @llvm.fma.v2f64(<2 x double> %{{[0-9]+}}, <2 x double> %{{[0-9]+}}, <2 x double>861// CHECK-LE: fneg <2 x double> %{{[0-9]+}}862// CHECK-LE-NEXT: call <2 x double> @llvm.fma.v2f64(<2 x double> %{{[0-9]+}}, <2 x double> %{{[0-9]+}}, <2 x double>863 864  res_vsll = vec_mul(vsll, vsll);865// CHECK: mul <2 x i64>866// CHECK-LE: mul <2 x i64>867 868  res_vull = vec_mul(vull, vull);869// CHECK: mul <2 x i64>870// CHECK-LE: mul <2 x i64>871 872  res_vf = vec_mul(vf, vf);873// CHECK: fmul <4 x float> %{{[0-9]+}}, %{{[0-9]+}}874// CHECK-LE: fmul <4 x float> %{{[0-9]+}}, %{{[0-9]+}}875 876  res_vd = vec_mul(vd, vd);877// CHECK: fmul <2 x double> %{{[0-9]+}}, %{{[0-9]+}}878// CHECK-LE: fmul <2 x double> %{{[0-9]+}}, %{{[0-9]+}}879 880  res_vf = vec_nearbyint(vf);881// CHECK: call <4 x float> @llvm.round.v4f32(<4 x float> %{{[0-9]+}})882// CHECK-LE: call <4 x float> @llvm.round.v4f32(<4 x float> %{{[0-9]+}})883 884  res_vd = vec_nearbyint(vd);885// CHECK: call <2 x double> @llvm.round.v2f64(<2 x double> %{{[0-9]+}})886// CHECK-LE: call <2 x double> @llvm.round.v2f64(<2 x double> %{{[0-9]+}})887 888  res_vf = vec_nmadd(vf, vf, vf);889// CHECK: [[FM:[0-9]+]] = call <4 x float> @llvm.fma.v4f32(<4 x float> %{{[0-9]+}}, <4 x float> %{{[0-9]+}}, <4 x float> %{{[0-9]+}})890// CHECK-NEXT: fneg <4 x float> %[[FM]]891// CHECK-LE: [[FM:[0-9]+]] = call <4 x float> @llvm.fma.v4f32(<4 x float> %{{[0-9]+}}, <4 x float> %{{[0-9]+}}, <4 x float> %{{[0-9]+}})892// CHECK-LE-NEXT: fneg <4 x float> %[[FM]]893 894  res_vd = vec_nmadd(vd, vd, vd);895// CHECK: [[FM:[0-9]+]] = call <2 x double> @llvm.fma.v2f64(<2 x double> %{{[0-9]+}}, <2 x double> %{{[0-9]+}}, <2 x double> %{{[0-9]+}})896// CHECK-NEXT: fneg <2 x double> %[[FM]]897// CHECK-LE: [[FM:[0-9]+]] = call <2 x double> @llvm.fma.v2f64(<2 x double> %{{[0-9]+}}, <2 x double> %{{[0-9]+}}, <2 x double> %{{[0-9]+}})898// CHECK-LE-NEXT: fneg <2 x double> %[[FM]]899 900  res_vf = vec_nmsub(vf, vf, vf);901// CHECK: call <4 x float> @llvm.ppc.fnmsub.v4f32(<4 x float> %{{[0-9]+}}, <4 x float> %{{[0-9]+}}, <4 x float>902// CHECK-LE: call <4 x float> @llvm.ppc.fnmsub.v4f32(<4 x float> %{{[0-9]+}}, <4 x float> %{{[0-9]+}}, <4 x float>903 904  res_vd = vec_nmsub(vd, vd, vd);905// CHECK: [[FM:[0-9]+]] = call <2 x double> @llvm.ppc.fnmsub.v2f64(<2 x double> %{{[0-9]+}}, <2 x double> %{{[0-9]+}}, <2 x double>906// CHECK-LE: [[FM:[0-9]+]] = call <2 x double> @llvm.ppc.fnmsub.v2f64(<2 x double> %{{[0-9]+}}, <2 x double> %{{[0-9]+}}, <2 x double>907 908  /* vec_nor */909  res_vsll = vec_nor(vsll, vsll);910// CHECK: or <2 x i64>911// CHECK: xor <2 x i64>912// CHECK-LE: or <2 x i64>913// CHECK-LE: xor <2 x i64>914 915  res_vull = vec_nor(vull, vull);916// CHECK: or <2 x i64>917// CHECK: xor <2 x i64>918// CHECK-LE: or <2 x i64>919// CHECK-LE: xor <2 x i64>920 921  res_vbll = vec_nor(vbll, vbll);922// CHECK: or <2 x i64>923// CHECK: xor <2 x i64>924// CHECK-LE: or <2 x i64>925// CHECK-LE: xor <2 x i64>926 927  res_vd = vec_nor(vd, vd);928// CHECK: bitcast <2 x double> %{{[0-9]+}} to <2 x i64>929// CHECK: [[OR:%.+]] = or <2 x i64> %{{[0-9]+}}, %{{[0-9]+}}930// CHECK-NEXT: xor <2 x i64> [[OR]], splat (i64 -1)931// CHECK-LE: bitcast <2 x double> %{{[0-9]+}} to <2 x i64>932// CHECK-LE: [[OR:%.+]] = or <2 x i64> %{{[0-9]+}}, %{{[0-9]+}}933// CHECK-LE-NEXT: xor <2 x i64> [[OR]], splat (i64 -1)934 935  /* vec_or */936  res_vsll = vec_or(vsll, vsll);937// CHECK: or <2 x i64>938// CHECK-LE: or <2 x i64>939 940  res_vsll = vec_or(vbll, vsll);941// CHECK: or <2 x i64>942// CHECK-LE: or <2 x i64>943 944  res_vsll = vec_or(vsll, vbll);945// CHECK: or <2 x i64>946// CHECK-LE: or <2 x i64>947 948  res_vull = vec_or(vull, vull);949// CHECK: or <2 x i64>950// CHECK-LE: or <2 x i64>951 952  res_vull = vec_or(vbll, vull);953// CHECK: or <2 x i64>954// CHECK-LE: or <2 x i64>955 956  res_vull = vec_or(vull, vbll);957// CHECK: or <2 x i64>958// CHECK-LE: or <2 x i64>959 960  res_vbll = vec_or(vbll, vbll);961// CHECK: or <2 x i64>962// CHECK-LE: or <2 x i64>963 964  res_vd = vec_or(vd, vd);965// CHECK: bitcast <2 x double> %{{[0-9]+}} to <2 x i64>966// CHECK: or <2 x i64> %{{[0-9]+}}, %{{[0-9]+}}967// CHECK-LE: bitcast <2 x double> %{{[0-9]+}} to <2 x i64>968// CHECK-LE: or <2 x i64> %{{[0-9]+}}, %{{[0-9]+}}969 970  res_vd = vec_or(vbll, vd);971// CHECK: [[T1:%.+]] = bitcast <2 x double> %{{[0-9]+}} to <2 x i64>972// CHECK: [[T2:%.+]] = or <2 x i64> %{{[0-9]+}}, [[T1]]973// CHECK: bitcast <2 x i64> [[T2]] to <2 x double>974// CHECK-LE: [[T1:%.+]] = bitcast <2 x double> %{{[0-9]+}} to <2 x i64>975// CHECK-LE: [[T2:%.+]] = or <2 x i64> %{{[0-9]+}}, [[T1]]976// CHECK-LE: bitcast <2 x i64> [[T2]] to <2 x double>977 978  res_vd = vec_or(vd, vbll);979// CHECK: [[T1:%.+]] = bitcast <2 x double> %{{[0-9]+}} to <2 x i64>980// CHECK: [[T2:%.+]] = or <2 x i64> [[T1]], %{{[0-9]+}}981// CHECK: bitcast <2 x i64> [[T2]] to <2 x double>982// CHECK-LE: [[T1:%.+]] = bitcast <2 x double> %{{[0-9]+}} to <2 x i64>983// CHECK-LE: [[T2:%.+]] = or <2 x i64> [[T1]], %{{[0-9]+}}984// CHECK-LE: bitcast <2 x i64> [[T2]] to <2 x double>985 986  res_vf = vec_re(vf);987// CHECK: call <4 x float> @llvm.ppc.vsx.xvresp(<4 x float>988// CHECK-LE: call <4 x float> @llvm.ppc.vsx.xvresp(<4 x float>989 990  res_vd = vec_re(vd);991// CHECK: call <2 x double> @llvm.ppc.vsx.xvredp(<2 x double>992// CHECK-LE: call <2 x double> @llvm.ppc.vsx.xvredp(<2 x double>993 994  res_vf = vec_rint(vf);995// CHECK: call <4 x float> @llvm.rint.v4f32(<4 x float> %{{[0-9]+}})996// CHECK-LE: call <4 x float> @llvm.rint.v4f32(<4 x float> %{{[0-9]+}})997 998  res_vd = vec_rint(vd);999// CHECK: call <2 x double> @llvm.rint.v2f64(<2 x double> %{{[0-9]+}})1000// CHECK-LE: call <2 x double> @llvm.rint.v2f64(<2 x double> %{{[0-9]+}})1001 1002  res_vf = vec_rsqrte(vf);1003// CHECK: call <4 x float> @llvm.ppc.vsx.xvrsqrtesp(<4 x float> %{{[0-9]+}})1004// CHECK-LE: call <4 x float> @llvm.ppc.vsx.xvrsqrtesp(<4 x float> %{{[0-9]+}})1005 1006  res_vf = vec_roundc(vf);1007// CHECK: call <4 x float> @llvm.rint.v4f32(<4 x float> %{{[0-9]+}})1008// CHECK-LE: call <4 x float> @llvm.rint.v4f32(<4 x float> %{{[0-9]+}})1009 1010  res_vd = vec_roundc(vd);1011// CHECK: call <2 x double> @llvm.rint.v2f64(<2 x double> %{{[0-9]+}})1012// CHECK-LE: call <2 x double> @llvm.rint.v2f64(<2 x double> %{{[0-9]+}})1013 1014  res_vd = vec_rsqrte(vd);1015// CHECK: call <2 x double> @llvm.ppc.vsx.xvrsqrtedp(<2 x double> %{{[0-9]+}})1016// CHECK-LE: call <2 x double> @llvm.ppc.vsx.xvrsqrtedp(<2 x double> %{{[0-9]+}})1017 1018  res_i = vec_test_swsqrt(vd);1019// CHECK: call i32 @llvm.ppc.vsx.xvtsqrtdp(<2 x double> %{{[0-9]+}})1020// CHECK-LE: call i32 @llvm.ppc.vsx.xvtsqrtdp(<2 x double> %{{[0-9]+}})1021 1022  res_i = vec_test_swsqrts(vf);1023// CHECK: call i32 @llvm.ppc.vsx.xvtsqrtsp(<4 x float> %{{[0-9]+}})1024// CHECK-LE: call i32 @llvm.ppc.vsx.xvtsqrtsp(<4 x float> %{{[0-9]+}})1025 1026  res_i = vec_test_swdiv(vd, vd);1027// CHECK: call i32 @llvm.ppc.vsx.xvtdivdp(<2 x double> %{{[0-9]+}}, <2 x double> %{{[0-9]+}})1028// CHECK-LE: call i32 @llvm.ppc.vsx.xvtdivdp(<2 x double> %{{[0-9]+}}, <2 x double> %{{[0-9]+}})1029 1030  res_i = vec_test_swdivs(vf, vf);1031// CHECK: call i32 @llvm.ppc.vsx.xvtdivsp(<4 x float> %{{[0-9]+}}, <4 x float> %{{[0-9]+}})1032// CHECK-LE: call i32 @llvm.ppc.vsx.xvtdivsp(<4 x float> %{{[0-9]+}}, <4 x float> %{{[0-9]+}})1033 1034 1035  dummy();1036// CHECK: call void @dummy()1037// CHECK-LE: call void @dummy()1038 1039  res_vd = vec_sel(vd, vd, vbll);1040// CHECK: xor <2 x i64> %{{[0-9]+}}, splat (i64 -1)1041// CHECK: and <2 x i64> %{{[0-9]+}},1042// CHECK: and <2 x i64> %{{[0-9]+}}, %{{[0-9]+}}1043// CHECK: or <2 x i64>1044// CHECK: bitcast <2 x i64> %{{[0-9]+}} to <2 x double>1045// CHECK-LE: xor <2 x i64> %{{[0-9]+}}, splat (i64 -1)1046// CHECK-LE: and <2 x i64> %{{[0-9]+}},1047// CHECK-LE: and <2 x i64> %{{[0-9]+}}, %{{[0-9]+}}1048// CHECK-LE: or <2 x i64>1049// CHECK-LE: bitcast <2 x i64> %{{[0-9]+}} to <2 x double>1050 1051  dummy();1052// CHECK: call void @dummy()1053// CHECK-LE: call void @dummy()1054 1055  res_vd = vec_sel(vd, vd, vull);1056// CHECK: xor <2 x i64> %{{[0-9]+}}, splat (i64 -1)1057// CHECK: and <2 x i64> %{{[0-9]+}},1058// CHECK: and <2 x i64> %{{[0-9]+}}, %{{[0-9]+}}1059// CHECK: or <2 x i64>1060// CHECK: bitcast <2 x i64> %{{[0-9]+}} to <2 x double>1061// CHECK-LE: xor <2 x i64> %{{[0-9]+}}, splat (i64 -1)1062// CHECK-LE: and <2 x i64> %{{[0-9]+}},1063// CHECK-LE: and <2 x i64> %{{[0-9]+}}, %{{[0-9]+}}1064// CHECK-LE: or <2 x i64>1065// CHECK-LE: bitcast <2 x i64> %{{[0-9]+}} to <2 x double>1066 1067  res_vbll = vec_sel(vbll, vbll, vbll);1068// CHECK: xor <2 x i64> %{{[0-9]+}}, splat (i64 -1)1069// CHECK: and <2 x i64> %{{[0-9]+}},1070// CHECK: and <2 x i64> %{{[0-9]+}}, %{{[0-9]+}}1071// CHECK: or <2 x i64>1072// CHECK-LE: xor <2 x i64> %{{[0-9]+}}, splat (i64 -1)1073// CHECK-LE: and <2 x i64> %{{[0-9]+}},1074// CHECK-LE: and <2 x i64> %{{[0-9]+}}, %{{[0-9]+}}1075// CHECK-LE: or <2 x i64>1076 1077  res_vbll = vec_sel(vbll, vbll, vull);1078// CHECK: xor <2 x i64> %{{[0-9]+}}, splat (i64 -1)1079// CHECK: and <2 x i64> %{{[0-9]+}},1080// CHECK: and <2 x i64> %{{[0-9]+}}, %{{[0-9]+}}1081// CHECK: or <2 x i64>1082// CHECK-LE: xor <2 x i64> %{{[0-9]+}}, splat (i64 -1)1083// CHECK-LE: and <2 x i64> %{{[0-9]+}},1084// CHECK-LE: and <2 x i64> %{{[0-9]+}}, %{{[0-9]+}}1085// CHECK-LE: or <2 x i64>1086 1087  res_vsll = vec_sel(vsll, vsll, vbll);1088// CHECK: xor <2 x i64> %{{[0-9]+}}, splat (i64 -1)1089// CHECK: and <2 x i64> %{{[0-9]+}},1090// CHECK: and <2 x i64> %{{[0-9]+}}, %{{[0-9]+}}1091// CHECK: or <2 x i64>1092// CHECK-LE: xor <2 x i64> %{{[0-9]+}}, splat (i64 -1)1093// CHECK-LE: and <2 x i64> %{{[0-9]+}},1094// CHECK-LE: and <2 x i64> %{{[0-9]+}}, %{{[0-9]+}}1095// CHECK-LE: or <2 x i64>1096 1097  res_vsll = vec_sel(vsll, vsll, vull);1098// CHECK: xor <2 x i64> %{{[0-9]+}}, splat (i64 -1)1099// CHECK: and <2 x i64> %{{[0-9]+}},1100// CHECK: and <2 x i64> %{{[0-9]+}}, %{{[0-9]+}}1101// CHECK: or <2 x i64>1102// CHECK-LE: xor <2 x i64> %{{[0-9]+}}, splat (i64 -1)1103// CHECK-LE: and <2 x i64> %{{[0-9]+}},1104// CHECK-LE: and <2 x i64> %{{[0-9]+}}, %{{[0-9]+}}1105// CHECK-LE: or <2 x i64>1106 1107  res_vull = vec_sel(vull, vull, vbll);1108// CHECK: xor <2 x i64> %{{[0-9]+}}, splat (i64 -1)1109// CHECK: and <2 x i64> %{{[0-9]+}},1110// CHECK: and <2 x i64> %{{[0-9]+}}, %{{[0-9]+}}1111// CHECK: or <2 x i64>1112// CHECK-LE: xor <2 x i64> %{{[0-9]+}}, splat (i64 -1)1113// CHECK-LE: and <2 x i64> %{{[0-9]+}},1114// CHECK-LE: and <2 x i64> %{{[0-9]+}}, %{{[0-9]+}}1115// CHECK-LE: or <2 x i64>1116 1117  res_vull = vec_sel(vull, vull, vull);1118// CHECK: xor <2 x i64> %{{[0-9]+}}, splat (i64 -1)1119// CHECK: and <2 x i64> %{{[0-9]+}},1120// CHECK: and <2 x i64> %{{[0-9]+}}, %{{[0-9]+}}1121// CHECK: or <2 x i64>1122// CHECK-LE: xor <2 x i64> %{{[0-9]+}}, splat (i64 -1)1123// CHECK-LE: and <2 x i64> %{{[0-9]+}},1124// CHECK-LE: and <2 x i64> %{{[0-9]+}}, %{{[0-9]+}}1125// CHECK-LE: or <2 x i64>1126 1127  res_vf = vec_sqrt(vf);1128// CHECK: call <4 x float> @llvm.sqrt.v4f32(<4 x float> %{{[0-9]+}})1129// CHECK-LE: call <4 x float> @llvm.sqrt.v4f32(<4 x float> %{{[0-9]+}})1130 1131  res_vd = vec_sqrt(vd);1132// CHECK: call <2 x double> @llvm.sqrt.v2f64(<2 x double> %{{[0-9]+}})1133// CHECK-LE: call <2 x double> @llvm.sqrt.v2f64(<2 x double> %{{[0-9]+}})1134 1135  res_vd = vec_sub(vd, vd);1136// CHECK: fsub <2 x double> %{{[0-9]+}}, %{{[0-9]+}}1137// CHECK-LE: fsub <2 x double> %{{[0-9]+}}, %{{[0-9]+}}1138 1139  res_vf = vec_trunc(vf);1140// CHECK: call <4 x float> @llvm.trunc.v4f32(<4 x float> %{{[0-9]+}})1141// CHECK-LE: call <4 x float> @llvm.trunc.v4f32(<4 x float> %{{[0-9]+}})1142 1143  res_vd = vec_trunc(vd);1144// CHECK: call <2 x double> @llvm.trunc.v2f64(<2 x double> %{{[0-9]+}})1145// CHECK-LE: call <2 x double> @llvm.trunc.v2f64(<2 x double> %{{[0-9]+}})1146 1147  res_vf = vec_roundz(vf);1148// CHECK: call <4 x float> @llvm.trunc.v4f32(<4 x float> %{{[0-9]+}})1149// CHECK-LE: call <4 x float> @llvm.trunc.v4f32(<4 x float> %{{[0-9]+}})1150 1151  res_vd = vec_roundz(vd);1152// CHECK: call <2 x double> @llvm.trunc.v2f64(<2 x double> %{{[0-9]+}})1153// CHECK-LE: call <2 x double> @llvm.trunc.v2f64(<2 x double> %{{[0-9]+}})1154 1155  /* vec_vor */1156  res_vsll = vec_vor(vsll, vsll);1157// CHECK: or <2 x i64>1158// CHECK-LE: or <2 x i64>1159 1160  res_vsll = vec_vor(vbll, vsll);1161// CHECK: or <2 x i64>1162// CHECK-LE: or <2 x i64>1163 1164  res_vsll = vec_vor(vsll, vbll);1165// CHECK: or <2 x i64>1166// CHECK-LE: or <2 x i64>1167 1168  res_vull = vec_vor(vull, vull);1169// CHECK: or <2 x i64>1170// CHECK-LE: or <2 x i64>1171 1172  res_vull = vec_vor(vbll, vull);1173// CHECK: or <2 x i64>1174// CHECK-LE: or <2 x i64>1175 1176  res_vull = vec_vor(vull, vbll);1177// CHECK: or <2 x i64>1178// CHECK-LE: or <2 x i64>1179 1180  res_vbll = vec_vor(vbll, vbll);1181// CHECK: or <2 x i64>1182// CHECK-LE: or <2 x i64>1183 1184  /* vec_xor */1185  res_vsll = vec_xor(vsll, vsll);1186// CHECK: xor <2 x i64>1187// CHECK-LE: xor <2 x i64>1188 1189  res_vsll = vec_xor(vbll, vsll);1190// CHECK: xor <2 x i64>1191// CHECK-LE: xor <2 x i64>1192 1193  res_vsll = vec_xor(vsll, vbll);1194// CHECK: xor <2 x i64>1195// CHECK-LE: xor <2 x i64>1196 1197  res_vull = vec_xor(vull, vull);1198// CHECK: xor <2 x i64>1199// CHECK-LE: xor <2 x i64>1200 1201  res_vull = vec_xor(vbll, vull);1202// CHECK: xor <2 x i64>1203// CHECK-LE: xor <2 x i64>1204 1205  res_vull = vec_xor(vull, vbll);1206// CHECK: xor <2 x i64>1207// CHECK-LE: xor <2 x i64>1208 1209  res_vbll = vec_xor(vbll, vbll);1210// CHECK: xor <2 x i64>1211// CHECK-LE: xor <2 x i64>1212 1213  dummy();1214// CHECK: call void @dummy()1215// CHECK-LE: call void @dummy()1216 1217  res_vd = vec_xor(vd, vd);1218// CHECK: [[X1:%.+]] = xor <2 x i64> %{{[0-9]+}}, %{{[0-9]+}}1219// CHECK: bitcast <2 x i64> [[X1]] to <2 x double>1220// CHECK-LE: [[X1:%.+]] = xor <2 x i64> %{{[0-9]+}}, %{{[0-9]+}}1221// CHECK-LE: bitcast <2 x i64> [[X1]] to <2 x double>1222 1223  dummy();1224// CHECK: call void @dummy()1225// CHECK-LE: call void @dummy()1226 1227  res_vd = vec_xor(vd, vbll);1228// CHECK: [[X1:%.+]] = xor <2 x i64> %{{[0-9]+}}, %{{[0-9]+}}1229// CHECK: bitcast <2 x i64> [[X1]] to <2 x double>1230// CHECK-LE: [[X1:%.+]] = xor <2 x i64> %{{[0-9]+}}, %{{[0-9]+}}1231// CHECK-LE: bitcast <2 x i64> [[X1]] to <2 x double>1232 1233  dummy();1234// CHECK: call void @dummy()1235// CHECK-LE: call void @dummy()1236 1237  res_vd = vec_xor(vbll, vd);1238// CHECK: [[X1:%.+]] = xor <2 x i64> %{{[0-9]+}}, %{{[0-9]+}}1239// CHECK: bitcast <2 x i64> [[X1]] to <2 x double>1240// CHECK-LE: [[X1:%.+]] = xor <2 x i64> %{{[0-9]+}}, %{{[0-9]+}}1241// CHECK-LE: bitcast <2 x i64> [[X1]] to <2 x double>1242 1243  /* vec_vxor */1244  res_vsll = vec_vxor(vsll, vsll);1245// CHECK: xor <2 x i64>1246// CHECK-LE: xor <2 x i64>1247 1248  res_vsll = vec_vxor(vbll, vsll);1249// CHECK: xor <2 x i64>1250// CHECK-LE: xor <2 x i64>1251 1252  res_vsll = vec_vxor(vsll, vbll);1253// CHECK: xor <2 x i64>1254// CHECK-LE: xor <2 x i64>1255 1256  res_vull = vec_vxor(vull, vull);1257// CHECK: xor <2 x i64>1258// CHECK-LE: xor <2 x i64>1259 1260  res_vull = vec_vxor(vbll, vull);1261// CHECK: xor <2 x i64>1262// CHECK-LE: xor <2 x i64>1263 1264  res_vull = vec_vxor(vull, vbll);1265// CHECK: xor <2 x i64>1266// CHECK-LE: xor <2 x i64>1267 1268  res_vbll = vec_vxor(vbll, vbll);1269// CHECK: xor <2 x i64>1270// CHECK-LE: xor <2 x i64>1271 1272  res_vsll = vec_cts(vd, 0);1273// CHECK: fmul <2 x double>1274// CHECK: fptosi <2 x double> %{{.*}} to <2 x i64>1275// CHECK-LE: fmul <2 x double>1276// CHECK-LE: fptosi <2 x double> %{{.*}} to <2 x i64>1277 1278  res_vsll = vec_cts(vd, 31);1279// CHECK: fmul <2 x double>1280// CHECK: fptosi <2 x double> %{{.*}} to <2 x i64>1281// CHECK-LE: fmul <2 x double>1282// CHECK-LE: fptosi <2 x double> %{{.*}} to <2 x i64>1283 1284  res_vsll = vec_ctsl(vf, 3);1285  // CHECK: fmul <4 x float> {{%.*}}, splat (float 8.000000e+00)1286  // CHECK: call <2 x i64> @llvm.ppc.vsx.xvcvspsxds(<4 x float>1287  // CHECK-LE: fmul <4 x float> {{%.*}}, splat (float 8.000000e+00)1288  // CHECK-LE:  shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 7, i32 0, i32 1, i32 2>1289  // CHECK-LE: call <2 x i64> @llvm.ppc.vsx.xvcvspsxds(<4 x float>1290 1291  res_vsll = vec_ctsl(vd, 3);1292  // CHECK: fmul <2 x double> {{%.*}}, splat (double 8.000000e+00)1293  // CHECK: fptosi <2 x double> {{%.*}} to <2 x i64>1294  // CHECK-LE: fmul <2 x double> {{%.*}}, splat (double 8.000000e+00)1295  // CHECK-LE: fptosi <2 x double> {{%.*}} to <2 x i64>1296 1297  res_vull = vec_ctu(vd, 0);1298// CHECK: fmul <2 x double>1299// CHECK: fptoui <2 x double> %{{.*}} to <2 x i64>1300// CHECK-LE: fmul <2 x double>1301// CHECK-LE: fptoui <2 x double> %{{.*}} to <2 x i64>1302 1303  res_vull = vec_ctu(vd, 31);1304// CHECK: fmul <2 x double>1305// CHECK: fptoui <2 x double> %{{.*}} to <2 x i64>1306// CHECK-LE: fmul <2 x double>1307// CHECK-LE: fptoui <2 x double> %{{.*}} to <2 x i64>1308 1309  res_vull = vec_ctul(vf, 3);1310  // CHECK: fmul <4 x float> {{%.*}}, splat (float 8.000000e+00)1311  // CHECK: call <2 x i64> @llvm.ppc.vsx.xvcvspuxds(<4 x float>1312  // CHECK-LE: fmul <4 x float> {{%.*}}, splat (float 8.000000e+00)1313  // CHECK-LE:  shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 7, i32 0, i32 1, i32 2>1314  // CHECK-LE: call <2 x i64> @llvm.ppc.vsx.xvcvspuxds(<4 x float>1315 1316  res_vull = vec_ctul(vd, 3);1317  // CHECK: fmul <2 x double> {{%.*}}, splat (double 8.000000e+00)1318  // CHECK: fptoui <2 x double> {{%.*}} to <2 x i64>1319  // CHECK-LE: fmul <2 x double> {{%.*}}, splat (double 8.000000e+00)1320  // CHECK-LE: fptoui <2 x double> {{%.*}} to <2 x i64>1321 1322  res_vf = vec_ctf(vsll, 0);1323// CHECK: sitofp <2 x i64> %{{.*}} to <2 x double>1324// CHECK: fmul <2 x double>1325// CHECK-LE: sitofp <2 x i64> %{{.*}} to <2 x double>1326// CHECK-LE: fmul <2 x double>1327 1328  res_vf = vec_ctf(vsll, 31);1329// CHECK: sitofp <2 x i64> %{{.*}} to <2 x double>1330// CHECK: fmul <2 x double>1331// CHECK-LE: sitofp <2 x i64> %{{.*}} to <2 x double>1332// CHECK-LE: fmul <2 x double>1333 1334  res_vf = vec_ctf(vull, 0);1335// CHECK: uitofp <2 x i64> %{{.*}} to <2 x double>1336// CHECK: fmul <2 x double>1337// CHECK-LE: uitofp <2 x i64> %{{.*}} to <2 x double>1338// CHECK-LE: fmul <2 x double>1339 1340  res_vf = vec_ctf(vull, 31);1341// CHECK: uitofp <2 x i64> %{{.*}} to <2 x double>1342// CHECK: fmul <2 x double>1343// CHECK-LE: uitofp <2 x i64> %{{.*}} to <2 x double>1344// CHECK-LE: fmul <2 x double>1345 1346  res_vd = vec_ctd(vsll, 2);1347// CHECK: sitofp <2 x i64> %{{.*}} to <2 x double>1348// CHECK: fmul <2 x double> {{.*}} splat (double 2.500000e-01)1349// CHECK-LE: sitofp <2 x i64> %{{.*}} to <2 x double>1350// CHECK-LE: fmul <2 x double> {{.*}} splat (double 2.500000e-01)1351 1352  res_vd = vec_ctd(vull, 2);1353// CHECK: uitofp <2 x i64> %{{.*}} to <2 x double>1354// CHECK: fmul <2 x double> {{.*}} splat (double 2.500000e-01)1355// CHECK-LE: uitofp <2 x i64> %{{.*}} to <2 x double>1356// CHECK-LE: fmul <2 x double> {{.*}} splat (double 2.500000e-01)1357 1358  res_vd = vec_ctd(vsi, 2);1359// CHECK: call <2 x double> @llvm.ppc.vsx.xvcvsxwdp(<4 x i32>1360// CHECK: fmul <2 x double> {{.*}} splat (double 2.500000e-01)1361// CHECK-LE: vperm1362// CHECK-LE: call <2 x double> @llvm.ppc.vsx.xvcvsxwdp(<4 x i32>1363// CHECK-LE: fmul <2 x double> {{.*}} splat (double 2.500000e-01)1364 1365  res_vd = vec_ctd(vui, 2);1366// CHECK: call <2 x double> @llvm.ppc.vsx.xvcvuxwdp(<4 x i32>1367// CHECK: fmul <2 x double> {{.*}} splat (double 2.500000e-01)1368// CHECK-LE: vperm1369// CHECK-LE: call <2 x double> @llvm.ppc.vsx.xvcvuxwdp(<4 x i32>1370// CHECK-LE: fmul <2 x double> {{.*}} splat (double 2.500000e-01)1371 1372  res_vsll = vec_signed(vd);1373// CHECK: fptosi <2 x double>1374// CHECK-LE: fptosi <2 x double>1375 1376  res_vsi = vec_signed2(vd, vd);1377// CHECK: extractelement <2 x double>1378// CHECK: fptosi double1379// CHECK: insertelement <4 x i32>1380// CHECK: extractelement <2 x double>1381// CHECK: fptosi double1382// CHECK: insertelement <4 x i32>1383// CHECK: extractelement <2 x double>1384// CHECK: fptosi double1385// CHECK: insertelement <4 x i32>1386// CHECK: extractelement <2 x double>1387// CHECK: fptosi double1388// CHECK: insertelement <4 x i32>1389// CHECK-LE: extractelement <2 x double>1390// CHECK-LE: fptosi double1391// CHECK-LE: insertelement <4 x i32>1392// CHECK-LE: extractelement <2 x double>1393// CHECK-LE: fptosi double1394// CHECK-LE: insertelement <4 x i32>1395// CHECK-LE: extractelement <2 x double>1396// CHECK-LE: fptosi double1397// CHECK-LE: insertelement <4 x i32>1398// CHECK-LE: extractelement <2 x double>1399// CHECK-LE: fptosi double1400// CHECK-LE: insertelement <4 x i32>1401 1402  res_vsi = vec_signede(vd);1403// CHECK: @llvm.ppc.vsx.xvcvdpsxws(<2 x double>1404// CHECK-LE: @llvm.ppc.vsx.xvcvdpsxws(<2 x double>1405// CHECK-LE: sub nsw i32 161406// CHECK-LE: sub nsw i32 171407// CHECK-LE: sub nsw i32 181408// CHECK-LE: sub nsw i32 311409// CHECK-LE: @llvm.ppc.altivec.vperm1410 1411  res_vsi = vec_signedo(vd);1412// CHECK: @llvm.ppc.vsx.xvcvdpsxws(<2 x double>1413// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 11414// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 21415// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 31416// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 151417// CHECK: @llvm.ppc.altivec.vperm1418// CHECK-LE: @llvm.ppc.vsx.xvcvdpsxws(<2 x double>1419 1420  res_vull = vec_unsigned(vd);1421// CHECK: fptoui <2 x double>1422// CHECK-LE: fptoui <2 x double>1423 1424  res_vui = vec_unsigned2(vd, vd);1425// CHECK: extractelement <2 x double>1426// CHECK: fptoui double1427// CHECK: insertelement <4 x i32>1428// CHECK: extractelement <2 x double>1429// CHECK: fptoui double1430// CHECK: insertelement <4 x i32>1431// CHECK: extractelement <2 x double>1432// CHECK: fptoui double1433// CHECK: insertelement <4 x i32>1434// CHECK: extractelement <2 x double>1435// CHECK: fptoui double1436// CHECK: insertelement <4 x i32>1437// CHECK-LE: extractelement <2 x double>1438// CHECK-LE: fptoui double1439// CHECK-LE: insertelement <4 x i32>1440// CHECK-LE: extractelement <2 x double>1441// CHECK-LE: fptoui double1442// CHECK-LE: insertelement <4 x i32>1443// CHECK-LE: extractelement <2 x double>1444// CHECK-LE: fptoui double1445// CHECK-LE: insertelement <4 x i32>1446// CHECK-LE: extractelement <2 x double>1447// CHECK-LE: fptoui double1448// CHECK-LE: insertelement <4 x i32>1449 1450  res_vui = vec_unsignede(vd);1451// CHECK: @llvm.ppc.vsx.xvcvdpuxws(<2 x double>1452// CHECK-LE: @llvm.ppc.vsx.xvcvdpuxws(<2 x double>1453// CHECK-LE: sub nsw i32 161454// CHECK-LE: sub nsw i32 171455// CHECK-LE: sub nsw i32 181456// CHECK-LE: sub nsw i32 311457// CHECK-LE: @llvm.ppc.altivec.vperm1458 1459  res_vui = vec_unsignedo(vd);1460// CHECK: @llvm.ppc.vsx.xvcvdpuxws(<2 x double>1461// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 11462// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 21463// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 31464// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 151465// CHECK: @llvm.ppc.altivec.vperm1466// CHECK-LE: @llvm.ppc.vsx.xvcvdpuxws(<2 x double>1467 1468  res_vf = vec_float2(vsll, vsll);1469// CHECK: extractelement <2 x i64>1470// CHECK: sitofp i641471// CHECK: insertelement <4 x float>1472// CHECK: extractelement <2 x i64>1473// CHECK: sitofp i641474// CHECK: insertelement <4 x float>1475// CHECK: extractelement <2 x i64>1476// CHECK: sitofp i641477// CHECK: insertelement <4 x float>1478// CHECK: extractelement <2 x i64>1479// CHECK: sitofp i641480// CHECK: insertelement <4 x float>1481// CHECK-LE: extractelement <2 x i64>1482// CHECK-LE: sitofp i641483// CHECK-LE: insertelement <4 x float>1484// CHECK-LE: extractelement <2 x i64>1485// CHECK-LE: sitofp i641486// CHECK-LE: insertelement <4 x float>1487// CHECK-LE: extractelement <2 x i64>1488// CHECK-LE: sitofp i641489// CHECK-LE: insertelement <4 x float>1490// CHECK-LE: extractelement <2 x i64>1491// CHECK-LE: sitofp i641492// CHECK-LE: insertelement <4 x float>1493 1494  res_vf = vec_float2(vull, vull);1495// CHECK: extractelement <2 x i64>1496// CHECK: uitofp i641497// CHECK: insertelement <4 x float>1498// CHECK: extractelement <2 x i64>1499// CHECK: uitofp i641500// CHECK: insertelement <4 x float>1501// CHECK: extractelement <2 x i64>1502// CHECK: uitofp i641503// CHECK: insertelement <4 x float>1504// CHECK: extractelement <2 x i64>1505// CHECK: uitofp i641506// CHECK: insertelement <4 x float>1507// CHECK-LE: extractelement <2 x i64>1508// CHECK-LE: uitofp i641509// CHECK-LE: insertelement <4 x float>1510// CHECK-LE: extractelement <2 x i64>1511// CHECK-LE: uitofp i641512// CHECK-LE: insertelement <4 x float>1513// CHECK-LE: extractelement <2 x i64>1514// CHECK-LE: uitofp i641515// CHECK-LE: insertelement <4 x float>1516// CHECK-LE: extractelement <2 x i64>1517// CHECK-LE: uitofp i641518// CHECK-LE: insertelement <4 x float>1519 1520  res_vf = vec_float2(vd, vd);1521// CHECK: extractelement <2 x double>1522// CHECK: fptrunc double1523// CHECK: insertelement <4 x float>1524// CHECK: extractelement <2 x double>1525// CHECK: fptrunc double1526// CHECK: insertelement <4 x float>1527// CHECK: extractelement <2 x double>1528// CHECK: fptrunc double1529// CHECK: insertelement <4 x float>1530// CHECK: extractelement <2 x double>1531// CHECK: fptrunc double1532// CHECK: insertelement <4 x float>1533// CHECK-LE: extractelement <2 x double>1534// CHECK-LE: fptrunc double1535// CHECK-LE: insertelement <4 x float>1536// CHECK-LE: extractelement <2 x double>1537// CHECK-LE: fptrunc double1538// CHECK-LE: insertelement <4 x float>1539// CHECK-LE: extractelement <2 x double>1540// CHECK-LE: fptrunc double1541// CHECK-LE: insertelement <4 x float>1542// CHECK-LE: extractelement <2 x double>1543// CHECK-LE: fptrunc double1544// CHECK-LE: insertelement <4 x float>1545 1546  res_vf = vec_floate(vsll);1547// CHECK: @llvm.ppc.vsx.xvcvsxdsp1548// CHECK-LE: @llvm.ppc.vsx.xvcvsxdsp1549// CHECK-LE: sub nsw i32 161550// CHECK-LE: sub nsw i32 171551// CHECK-LE: sub nsw i32 181552// CHECK-LE: sub nsw i32 311553// CHECK-LE: @llvm.ppc.altivec.vperm1554 1555  res_vf = vec_floate(vull);1556// CHECK: @llvm.ppc.vsx.xvcvuxdsp1557// CHECK-LE: @llvm.ppc.vsx.xvcvuxdsp1558// CHECK-LE: sub nsw i32 161559// CHECK-LE: sub nsw i32 171560// CHECK-LE: sub nsw i32 181561// CHECK-LE: sub nsw i32 311562// CHECK-LE: @llvm.ppc.altivec.vperm1563 1564  res_vf = vec_floate(vd);1565// CHECK: @llvm.ppc.vsx.xvcvdpsp1566// CHECK-LE: @llvm.ppc.vsx.xvcvdpsp1567// CHECK-LE: sub nsw i32 161568// CHECK-LE: sub nsw i32 171569// CHECK-LE: sub nsw i32 181570// CHECK-LE: sub nsw i32 311571// CHECK-LE: @llvm.ppc.altivec.vperm1572 1573  res_vf = vec_cvf(vd);1574// CHECK: @llvm.ppc.vsx.xvcvdpsp1575// CHECK-LE: @llvm.ppc.vsx.xvcvdpsp1576// CHECK-LE: sub nsw i32 161577// CHECK-LE: sub nsw i32 171578// CHECK-LE: sub nsw i32 181579// CHECK-LE: sub nsw i32 311580// CHECK-LE: @llvm.ppc.altivec.vperm1581 1582  res_vf = vec_floato(vsll);1583// CHECK: @llvm.ppc.vsx.xvcvsxdsp1584// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 11585// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 21586// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 31587// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 151588// CHECK: @llvm.ppc.altivec.vperm1589// CHECK-LE: @llvm.ppc.vsx.xvcvsxdsp1590 1591  res_vf = vec_floato(vull);1592// CHECK: @llvm.ppc.vsx.xvcvuxdsp1593// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 11594// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 21595// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 31596// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 151597// CHECK: @llvm.ppc.altivec.vperm1598// CHECK-LE: @llvm.ppc.vsx.xvcvuxdsp1599 1600  res_vf = vec_floato(vd);1601// CHECK: @llvm.ppc.vsx.xvcvdpsp1602// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 11603// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 21604// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 31605// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 151606// CHECK: @llvm.ppc.altivec.vperm1607// CHECK-LE: @llvm.ppc.vsx.xvcvdpsp1608 1609  res_vd = vec_double(vsll);1610// CHECK: sitofp <2 x i64>1611// CHECK-LE: sitofp <2 x i64>1612 1613  res_vd = vec_double(vull);1614// CHECK: uitofp <2 x i64>1615// CHECK-LE: uitofp <2 x i64>1616 1617  res_vd = vec_doublee(vsi);1618// CHECK: @llvm.ppc.vsx.xvcvsxwdp(<4 x i321619// CHECK-LE: sub nsw i32 161620// CHECK-LE: sub nsw i32 171621// CHECK-LE: sub nsw i32 181622// CHECK-LE: sub nsw i32 311623// CHECK-LE: @llvm.ppc.altivec.vperm1624// CHECK-LE: @llvm.ppc.vsx.xvcvsxwdp(<4 x i321625 1626  res_vd = vec_doublee(vui);1627// CHECK: @llvm.ppc.vsx.xvcvuxwdp(<4 x i321628// CHECK-LE: sub nsw i32 161629// CHECK-LE: sub nsw i32 171630// CHECK-LE: sub nsw i32 181631// CHECK-LE: sub nsw i32 311632// CHECK-LE: @llvm.ppc.altivec.vperm1633// CHECK-LE: @llvm.ppc.vsx.xvcvuxwdp(<4 x i321634 1635  res_vd = vec_doublee(vf);1636// CHECK: @llvm.ppc.vsx.xvcvspdp(<4 x float1637// CHECK-LE: sub nsw i32 161638// CHECK-LE: sub nsw i32 171639// CHECK-LE: sub nsw i32 181640// CHECK-LE: sub nsw i32 311641// CHECK-LE: @llvm.ppc.altivec.vperm1642// CHECK-LE: @llvm.ppc.vsx.xvcvspdp(<4 x float1643 1644  res_vd = vec_cvf(vf);1645// CHECK: @llvm.ppc.vsx.xvcvspdp(<4 x float1646// CHECK-LE: sub nsw i32 161647// CHECK-LE: sub nsw i32 171648// CHECK-LE: sub nsw i32 181649// CHECK-LE: sub nsw i32 311650// CHECK-LE: @llvm.ppc.altivec.vperm1651// CHECK-LE: @llvm.ppc.vsx.xvcvspdp(<4 x float1652 1653  res_vd = vec_doubleh(vsi);1654// CHECK: extractelement <4 x i32>1655// CHECK: sitofp i321656// CHECK: insertelement <2 x double>1657// CHECK: extractelement <4 x i32>1658// CHECK: sitofp i321659// CHECK: insertelement <2 x double>1660// CHECK-LE: extractelement <4 x i32>1661// CHECK-LE: sitofp i321662// CHECK-LE: insertelement <2 x double>1663// CHECK-LE: extractelement <4 x i32>1664// CHECK-LE: sitofp i321665// CHECK-LE: insertelement <2 x double>1666 1667  res_vd = vec_doubleh(vui);1668// CHECK: extractelement <4 x i32>1669// CHECK: uitofp i321670// CHECK: insertelement <2 x double>1671// CHECK: extractelement <4 x i32>1672// CHECK: uitofp i321673// CHECK: insertelement <2 x double>1674// CHECK-LE: extractelement <4 x i32>1675// CHECK-LE: uitofp i321676// CHECK-LE: insertelement <2 x double>1677// CHECK-LE: extractelement <4 x i32>1678// CHECK-LE: uitofp i321679// CHECK-LE: insertelement <2 x double>1680 1681  res_vd = vec_doubleh(vf);1682// CHECK: extractelement <4 x float>1683// CHECK: fpext float1684// CHECK: insertelement <2 x double>1685// CHECK: extractelement <4 x float>1686// CHECK: fpext float1687// CHECK: insertelement <2 x double>1688// CHECK-LE: extractelement <4 x float>1689// CHECK-LE: fpext float1690// CHECK-LE: insertelement <2 x double>1691// CHECK-LE: extractelement <4 x float>1692// CHECK-LE: fpext float1693// CHECK-LE: insertelement <2 x double>1694 1695  res_vd = vec_doublel(vsi);1696// CHECK: extractelement <4 x i32>1697// CHECK: sitofp i321698// CHECK: insertelement <2 x double>1699// CHECK: extractelement <4 x i32>1700// CHECK: sitofp i321701// CHECK: insertelement <2 x double>1702// CHECK-LE: extractelement <4 x i32>1703// CHECK-LE: sitofp i321704// CHECK-LE: insertelement <2 x double>1705// CHECK-LE: extractelement <4 x i32>1706// CHECK-LE: sitofp i321707// CHECK-LE: insertelement <2 x double>1708 1709  res_vd = vec_doublel(vui);1710// CHECK: extractelement <4 x i32>1711// CHECK: uitofp i321712// CHECK: insertelement <2 x double>1713// CHECK: extractelement <4 x i32>1714// CHECK: uitofp i321715// CHECK: insertelement <2 x double>1716// CHECK-LE: extractelement <4 x i32>1717// CHECK-LE: uitofp i321718// CHECK-LE: insertelement <2 x double>1719// CHECK-LE: extractelement <4 x i32>1720// CHECK-LE: uitofp i321721// CHECK-LE: insertelement <2 x double>1722 1723  res_vd = vec_doublel(vf);1724// CHECK: extractelement <4 x float>1725// CHECK: fpext float1726// CHECK: insertelement <2 x double>1727// CHECK: extractelement <4 x float>1728// CHECK: fpext float1729// CHECK: insertelement <2 x double>1730// CHECK-LE: extractelement <4 x float>1731// CHECK-LE: fpext float1732// CHECK-LE: insertelement <2 x double>1733// CHECK-LE: extractelement <4 x float>1734// CHECK-LE: fpext float1735// CHECK-LE: insertelement <2 x double>1736 1737  res_vd = vec_doubleo(vsi);1738// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 11739// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 21740// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 31741// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 151742// CHECK: @llvm.ppc.altivec.vperm1743// CHECK: @llvm.ppc.vsx.xvcvsxwdp(<4 x i32>1744// CHECK-LE: @llvm.ppc.vsx.xvcvsxwdp(<4 x i32>1745 1746  res_vd = vec_doubleo(vui);1747// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 11748// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 21749// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 31750// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 151751// CHECK: @llvm.ppc.altivec.vperm1752// CHECK: @llvm.ppc.vsx.xvcvuxwdp(<4 x i32>1753// CHECK-LE: @llvm.ppc.vsx.xvcvuxwdp(<4 x i32>1754 1755  res_vd = vec_doubleo(vf);1756// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 11757// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 21758// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 31759// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 151760// CHECK: @llvm.ppc.altivec.vperm1761// CHECK: @llvm.ppc.vsx.xvcvspdp(<4 x float>1762// CHECK-LE: @llvm.ppc.vsx.xvcvspdp(<4 x float>1763 1764  res_vbll = vec_reve(vbll);1765// CHECK: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 1, i32 0>1766// CHECK-LE: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 1, i32 0>1767 1768  res_vsll = vec_reve(vsll);1769// CHECK: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 1, i32 0>1770// CHECK-LE: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 1, i32 0>1771 1772  res_vull = vec_reve(vull);1773// CHECK: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 1, i32 0>1774// CHECK-LE: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 1, i32 0>1775 1776  res_vd = vec_reve(vd);1777// CHECK: shufflevector <2 x double> %{{[0-9]+}}, <2 x double> %{{[0-9]+}}, <2 x i32> <i32 1, i32 0>1778// CHECK-LE: shufflevector <2 x double> %{{[0-9]+}}, <2 x double> %{{[0-9]+}}, <2 x i32> <i32 1, i32 0>1779 1780  res_vbll = vec_revb(vbll);1781// CHECK: store <16 x i8> <i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 15, i8 14, i8 13, i8 12, i8 11, i8 10, i8 9, i8 8>, ptr {{%.+}}, align 161782// CHECK: call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> {{%.+}}, <4 x i32> {{%.+}}, <16 x i8> {{%.+}})1783// CHECK-LE: store <16 x i8> <i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 15, i8 14, i8 13, i8 12, i8 11, i8 10, i8 9, i8 8>, ptr {{%.+}}, align 161784// CHECK-LE: store <16 x i8> splat (i8 -1), ptr {{%.+}}, align 161785// CHECK-LE: xor <16 x i8>1786// CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> {{%.+}}, <4 x i32> {{%.+}}, <16 x i8> {{%.+}})1787 1788  res_vsll = vec_revb(vsll);1789// CHECK: store <16 x i8> <i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 15, i8 14, i8 13, i8 12, i8 11, i8 10, i8 9, i8 8>, ptr {{%.+}}, align 161790// CHECK: call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> {{%.+}}, <4 x i32> {{%.+}}, <16 x i8> {{%.+}})1791// CHECK-LE: store <16 x i8> <i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 15, i8 14, i8 13, i8 12, i8 11, i8 10, i8 9, i8 8>, ptr {{%.+}}, align 161792// CHECK-LE: store <16 x i8> splat (i8 -1), ptr {{%.+}}, align 161793// CHECK-LE: xor <16 x i8>1794// CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> {{%.+}}, <4 x i32> {{%.+}}, <16 x i8> {{%.+}})1795 1796  res_vull = vec_revb(vull);1797// CHECK: store <16 x i8> <i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 15, i8 14, i8 13, i8 12, i8 11, i8 10, i8 9, i8 8>, ptr {{%.+}}, align 161798// CHECK: call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> {{%.+}}, <4 x i32> {{%.+}}, <16 x i8> {{%.+}})1799// CHECK-LE: store <16 x i8> <i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 15, i8 14, i8 13, i8 12, i8 11, i8 10, i8 9, i8 8>, ptr {{%.+}}, align 161800// CHECK-LE: store <16 x i8> splat (i8 -1), ptr {{%.+}}, align 161801// CHECK-LE: xor <16 x i8>1802// CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> {{%.+}}, <4 x i32> {{%.+}}, <16 x i8> {{%.+}})1803 1804  res_vd = vec_revb(vd);1805// CHECK: store <16 x i8> <i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 15, i8 14, i8 13, i8 12, i8 11, i8 10, i8 9, i8 8>, ptr {{%.+}}, align 161806// CHECK: call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> {{%.+}}, <4 x i32> {{%.+}}, <16 x i8> {{%.+}})1807// CHECK-LE: store <16 x i8> <i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 15, i8 14, i8 13, i8 12, i8 11, i8 10, i8 9, i8 8>, ptr {{%.+}}, align 161808// CHECK-LE: store <16 x i8> splat (i8 -1), ptr {{%.+}}, align 161809// CHECK-LE: xor <16 x i8>1810// CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> {{%.+}}, <4 x i32> {{%.+}}, <16 x i8> {{%.+}})1811 1812  res_vbll = vec_sld(vbll, vbll, 0);1813// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 11814// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 21815// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 31816// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 151817// CHECK: @llvm.ppc.altivec.vperm1818// CHECK-LE: sub nsw i32 161819// CHECK-LE: sub nsw i32 171820// CHECK-LE: sub nsw i32 181821// CHECK-LE: sub nsw i32 311822// CHECK-LE: @llvm.ppc.altivec.vperm1823 1824  res_vsll = vec_sld(vsll, vsll, 0);1825// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 11826// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 21827// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 31828// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 151829// CHECK: @llvm.ppc.altivec.vperm1830// CHECK-LE: sub nsw i32 161831// CHECK-LE: sub nsw i32 171832// CHECK-LE: sub nsw i32 181833// CHECK-LE: sub nsw i32 311834// CHECK-LE: @llvm.ppc.altivec.vperm1835 1836  res_vull = vec_sld(vull, vull, 0);1837// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 11838// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 21839// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 31840// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 151841// CHECK: @llvm.ppc.altivec.vperm1842// CHECK-LE: sub nsw i32 161843// CHECK-LE: sub nsw i32 171844// CHECK-LE: sub nsw i32 181845// CHECK-LE: sub nsw i32 311846// CHECK-LE: @llvm.ppc.altivec.vperm1847 1848  res_vd = vec_sld(vd, vd, 0);1849// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 11850// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 21851// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 31852// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 151853// CHECK: @llvm.ppc.altivec.vperm1854// CHECK-LE: sub nsw i32 161855// CHECK-LE: sub nsw i32 171856// CHECK-LE: sub nsw i32 181857// CHECK-LE: sub nsw i32 311858// CHECK-LE: @llvm.ppc.altivec.vperm1859 1860  res_vsll = vec_sldw(vsll, vsll, 0);1861// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 11862// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 21863// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 31864// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 151865// CHECK: @llvm.ppc.altivec.vperm1866// CHECK-LE: sub nsw i32 161867// CHECK-LE: sub nsw i32 171868// CHECK-LE: sub nsw i32 181869// CHECK-LE: sub nsw i32 311870// CHECK-LE: @llvm.ppc.altivec.vperm1871 1872  res_vull = vec_sldw(vull, vull, 0);1873// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 11874// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 21875// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 31876// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 151877// CHECK: @llvm.ppc.altivec.vperm1878// CHECK-LE: sub nsw i32 161879// CHECK-LE: sub nsw i32 171880// CHECK-LE: sub nsw i32 181881// CHECK-LE: sub nsw i32 311882// CHECK-LE: @llvm.ppc.altivec.vperm1883 1884  res_vd = vec_sldw(vd, vd, 0);1885// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 11886// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 21887// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 31888// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 151889// CHECK: @llvm.ppc.altivec.vperm1890// CHECK-LE: sub nsw i32 161891// CHECK-LE: sub nsw i32 171892// CHECK-LE: sub nsw i32 181893// CHECK-LE: sub nsw i32 311894// CHECK-LE: @llvm.ppc.altivec.vperm1895 1896  res_vsll = vec_sll(vsll, vuc);1897// CHECK: @llvm.ppc.altivec.vsl1898// CHECK-LE: @llvm.ppc.altivec.vsl1899 1900res_vull = vec_sll(vull, vuc);1901// CHECK: @llvm.ppc.altivec.vsl1902// CHECK-LE: @llvm.ppc.altivec.vsl1903 1904res_vsll = vec_slo(vsll, vsc);1905// CHECK: @llvm.ppc.altivec.vslo1906// CHECK-LE: @llvm.ppc.altivec.vslo1907 1908  res_vsll = vec_slo(vsll, vuc);1909// CHECK: @llvm.ppc.altivec.vslo1910// CHECK-LE: @llvm.ppc.altivec.vslo1911 1912  res_vull = vec_slo(vull, vsc);1913// CHECK: @llvm.ppc.altivec.vslo1914// CHECK-LE: @llvm.ppc.altivec.vslo1915 1916  res_vull = vec_slo(vull, vuc);1917// CHECK: @llvm.ppc.altivec.vslo1918// CHECK-LE: @llvm.ppc.altivec.vslo1919 1920  res_vsll = vec_srl(vsll, vuc);1921// CHECK: @llvm.ppc.altivec.vsr1922// CHECK-LE: @llvm.ppc.altivec.vsr1923 1924  res_vull = vec_srl(vull, vuc);1925// CHECK: @llvm.ppc.altivec.vsr1926// CHECK-LE: @llvm.ppc.altivec.vsr1927 1928  res_vsll = vec_sro(vsll, vsc);1929// CHECK: @llvm.ppc.altivec.vsro1930// CHECK-LE: @llvm.ppc.altivec.vsro1931 1932  res_vsll = vec_sro(vsll, vuc);1933// CHECK: @llvm.ppc.altivec.vsro1934// CHECK-LE: @llvm.ppc.altivec.vsro1935 1936  res_vull = vec_sro(vull, vsc);1937// CHECK: @llvm.ppc.altivec.vsro1938// CHECK-LE: @llvm.ppc.altivec.vsro1939 1940  res_vull = vec_sro(vull, vuc);1941// CHECK: @llvm.ppc.altivec.vsro1942// CHECK-LE: @llvm.ppc.altivec.vsro1943 1944res_vsll = vec_xl(sll, asll);1945// CHECK: load <2 x i64>, ptr %{{[0-9]+}}, align 11946// CHECK-LE: load <2 x i64>, ptr %{{[0-9]+}}, align 11947 1948res_vull = vec_xl(sll, aull);1949// CHECK: load <2 x i64>, ptr %{{[0-9]+}}, align 11950// CHECK-LE: load <2 x i64>, ptr %{{[0-9]+}}, align 11951 1952res_vd = vec_xl(sll, ad);1953// CHECK: load <2 x double>, ptr %{{[0-9]+}}, align 11954// CHECK-LE: load <2 x double>, ptr %{{[0-9]+}}, align 11955 1956vec_xst(vsll, sll, asll);1957// CHECK: store <2 x i64> %{{[0-9]+}}, ptr %{{[0-9]+}}, align 11958// CHECK-LE: store <2 x i64> %{{[0-9]+}}, ptr %{{[0-9]+}}, align 11959 1960vec_xst(vull, sll, aull);1961// CHECK: store <2 x i64> %{{[0-9]+}}, ptr %{{[0-9]+}}, align 11962// CHECK-LE: store <2 x i64> %{{[0-9]+}}, ptr %{{[0-9]+}}, align 11963 1964vec_xst(vd, sll, ad);1965// CHECK: store <2 x double> %{{[0-9]+}}, ptr %{{[0-9]+}}, align 11966// CHECK-LE: store <2 x double> %{{[0-9]+}}, ptr %{{[0-9]+}}, align 11967 1968res_vsll = vec_xl_be(sll, asll);1969// CHECK: load <2 x i64>, ptr %{{[0-9]+}}, align 11970// CHECK-LE: call <2 x double> @llvm.ppc.vsx.lxvd2x.be(ptr %{{[0-9]+}})1971 1972res_vull = vec_xl_be(sll, aull);1973// CHECK: load <2 x i64>, ptr %{{[0-9]+}}, align 11974// CHECK-LE: call <2 x double> @llvm.ppc.vsx.lxvd2x.be(ptr %{{[0-9]+}})1975 1976res_vd = vec_xl_be(sll, ad);1977// CHECK: load <2 x double>, ptr %{{[0-9]+}}, align 11978// CHECK-LE: call <2 x double> @llvm.ppc.vsx.lxvd2x.be(ptr %{{[0-9]+}})1979 1980res_vsc = vec_xl_be(sll, asc);1981// CHECK: load <16 x i8>, ptr %{{.+}}, align 11982// CHECK-LE: call <2 x double> @llvm.ppc.vsx.lxvd2x.be(ptr %{{[0-9]+}})1983// CHECK-LE: shufflevector <16 x i8> %{{[0-9]+}}, <16 x i8> %{{[0-9]+}}, <16 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8>1984 1985res_vuc = vec_xl_be(sll, auc);1986// CHECK: load <16 x i8>, ptr %{{.+}}, align 11987// CHECK-LE: call <2 x double> @llvm.ppc.vsx.lxvd2x.be(ptr %{{[0-9]+}})1988// CHECK-LE: shufflevector <16 x i8> %{{[0-9]+}}, <16 x i8> %{{[0-9]+}}, <16 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8>1989 1990res_vss = vec_xl_be(sll, ass);1991// CHECK: load <8 x i16>, ptr %{{.+}}, align 11992// CHECK-LE: call <2 x double> @llvm.ppc.vsx.lxvd2x.be(ptr %{{[0-9]+}})1993// CHECK-LE: shufflevector <8 x i16> %{{[0-9]+}}, <8 x i16> %{{[0-9]+}}, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>1994 1995res_vus = vec_xl_be(sll, aus);1996// CHECK: load <8 x i16>, ptr %{{.+}}, align 11997// CHECK-LE: call <2 x double> @llvm.ppc.vsx.lxvd2x.be(ptr %{{[0-9]+}})1998// CHECK-LE: shufflevector <8 x i16> %{{[0-9]+}}, <8 x i16> %{{[0-9]+}}, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>1999 2000res_vsi = vec_xl_be(sll, asi);2001// CHECK: load <4 x i32>, ptr %{{.+}}, align 12002// CHECK-LE: call <4 x i32> @llvm.ppc.vsx.lxvw4x.be(ptr %{{[0-9]+}})2003 2004res_vui = vec_xl_be(sll, aui);2005// CHECK: load <4 x i32>, ptr %{{.+}}, align 12006// CHECK-LE: call <4 x i32> @llvm.ppc.vsx.lxvw4x.be(ptr %{{[0-9]+}})2007 2008res_vf = vec_xl_be(sll, af);2009// CHECK: load <4 x float>, ptr %{{.+}}, align 12010// CHECK-LE: call <4 x i32> @llvm.ppc.vsx.lxvw4x.be(ptr %{{[0-9]+}})2011 2012res_vsll = vec_xlds(sll, asll);2013// CHECK: load i642014// CHECK: insertelement <2 x i64>2015// CHECK: shufflevector <2 x i64>2016// CHECK-LE: load i642017// CHECK-LE: insertelement <2 x i64>2018// CHECK-LE: shufflevector <2 x i64>2019 2020res_vull = vec_xlds(sll, aull);2021// CHECK: load i642022// CHECK: insertelement <2 x i64>2023// CHECK: shufflevector <2 x i64>2024// CHECK-LE: load i642025// CHECK-LE: insertelement <2 x i64>2026// CHECK-LE: shufflevector <2 x i64>2027 2028res_vd = vec_xlds(sll, ad);2029// CHECK: load double2030// CHECK: insertelement <2 x double>2031// CHECK: shufflevector <2 x double>2032// CHECK-LE: load double2033// CHECK-LE: insertelement <2 x double>2034// CHECK-LE: shufflevector <2 x double>2035 2036res_vsi = vec_load_splats(sll, asi);2037// CHECK: load i322038// CHECK: insertelement <4 x i32>2039// CHECK: shufflevector <4 x i32>2040// CHECK-LE: load i322041// CHECK-LE: insertelement <4 x i32>2042// CHECK-LE: shufflevector <4 x i32>2043 2044res_vsi = vec_load_splats(ull, asi);2045// CHECK: load i322046// CHECK: insertelement <4 x i32>2047// CHECK: shufflevector <4 x i32>2048// CHECK-LE: load i322049// CHECK-LE: insertelement <4 x i32>2050// CHECK-LE: shufflevector <4 x i32>2051 2052res_vui = vec_load_splats(sll, aui);2053// CHECK: load i322054// CHECK: insertelement <4 x i32>2055// CHECK: shufflevector <4 x i32>2056// CHECK-LE: load i322057// CHECK-LE: insertelement <4 x i32>2058// CHECK-LE: shufflevector <4 x i32>2059 2060res_vui = vec_load_splats(ull, aui);2061// CHECK: load i322062// CHECK: insertelement <4 x i32>2063// CHECK: shufflevector <4 x i32>2064// CHECK-LE: load i322065// CHECK-LE: insertelement <4 x i32>2066// CHECK-LE: shufflevector <4 x i32>2067 2068res_vf = vec_load_splats(sll, af);2069// CHECK: load float2070// CHECK: insertelement <4 x float>2071// CHECK: shufflevector <4 x float>2072// CHECK-LE: load float2073// CHECK-LE: insertelement <4 x float>2074// CHECK-LE: shufflevector <4 x float>2075 2076res_vf = vec_load_splats(ull, af);2077// CHECK: load float2078// CHECK: insertelement <4 x float>2079// CHECK: shufflevector <4 x float>2080// CHECK-LE: load float2081// CHECK-LE: insertelement <4 x float>2082// CHECK-LE: shufflevector <4 x float>2083 2084vec_xst_be(vsll, sll, asll);2085// CHECK: store <2 x i64> %{{[0-9]+}}, ptr %{{[0-9]+}}, align 12086// CHECK-LE: call void @llvm.ppc.vsx.stxvd2x.be(<2 x double> %{{[0-9]+}}, ptr %{{[0-9]+}})2087 2088vec_xst_be(vull, sll, aull);2089// CHECK: store <2 x i64> %{{[0-9]+}}, ptr %{{[0-9]+}}, align 12090// CHECK-LE: call void @llvm.ppc.vsx.stxvd2x.be(<2 x double> %{{[0-9]+}}, ptr %{{[0-9]+}})2091 2092vec_xst_be(vd, sll, ad);2093// CHECK: store <2 x double> %{{[0-9]+}}, ptr %{{[0-9]+}}, align 12094// CHECK-LE: call void @llvm.ppc.vsx.stxvd2x.be(<2 x double> %{{[0-9]+}}, ptr %{{[0-9]+}})2095 2096vec_xst_be(vsc, sll, asc);2097// CHECK: store <16 x i8> %{{[0-9]+}}, ptr %{{.+}}, align 12098// CHECK-LE: shufflevector <16 x i8> %{{[0-9]+}}, <16 x i8> %{{[0-9]+}}, <16 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8>2099// CHECK-LE: call void @llvm.ppc.vsx.stxvd2x.be(<2 x double> %{{[0-9]+}}, ptr %{{[0-9]+}})2100 2101vec_xst_be(vuc, sll, auc);2102// CHECK: store <16 x i8> %{{[0-9]+}}, ptr %{{.+}}, align 12103// CHECK-LE: shufflevector <16 x i8> %{{[0-9]+}}, <16 x i8> %{{[0-9]+}}, <16 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8>2104// CHECK-LE: call void @llvm.ppc.vsx.stxvd2x.be(<2 x double> %{{[0-9]+}}, ptr %{{[0-9]+}})2105 2106vec_xst_be(vss, sll, ass);2107// CHECK: store <8 x i16> %{{[0-9]+}}, ptr %{{.+}}, align 12108// CHECK-LE: shufflevector <8 x i16> %{{[0-9]+}}, <8 x i16> %{{[0-9]+}}, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>2109// CHECK-LE: call void @llvm.ppc.vsx.stxvd2x.be(<2 x double> %{{[0-9]+}}, ptr %{{[0-9]+}})2110 2111vec_xst_be(vus, sll, aus);2112// CHECK: store <8 x i16> %{{[0-9]+}}, ptr %{{.+}}, align 12113// CHECK-LE: shufflevector <8 x i16> %{{[0-9]+}}, <8 x i16> %{{[0-9]+}}, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>2114// CHECK-LE: call void @llvm.ppc.vsx.stxvd2x.be(<2 x double> %{{[0-9]+}}, ptr %{{[0-9]+}})2115 2116vec_xst_be(vsi, sll, asi);2117// CHECK: store <4 x i32> %{{[0-9]+}}, ptr %{{.+}}, align 12118// CHECK-LE: call void @llvm.ppc.vsx.stxvw4x.be(<4 x i32> %{{[0-9]+}}, ptr %{{[0-9]+}})2119 2120vec_xst_be(vui, sll, aui);2121// CHECK: store <4 x i32> %{{[0-9]+}}, ptr %{{.+}}, align 12122// CHECK-LE: call void @llvm.ppc.vsx.stxvw4x.be(<4 x i32> %{{[0-9]+}}, ptr %{{[0-9]+}})2123 2124vec_xst_be(vf, sll, af);2125// CHECK: store <4 x float> %{{[0-9]+}}, ptr %{{.+}}, align 12126// CHECK-LE: call void @llvm.ppc.vsx.stxvw4x.be(<4 x i32> %{{[0-9]+}}, ptr %{{[0-9]+}})2127 2128  res_vf = vec_neg(vf);2129// CHECK: fneg <4 x float> {{%[0-9]+}}2130// CHECK-LE: fneg <4 x float> {{%[0-9]+}}2131 2132  res_vd = vec_neg(vd);2133// CHECK: fneg <2 x double> {{%[0-9]+}}2134// CHECK-LE: fneg <2 x double> {{%[0-9]+}}2135 2136res_vd = vec_xxpermdi(vd, vd, 0);2137// CHECK: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 0, i32 2>2138// CHECK-LE: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 0, i32 2>2139 2140res_vf = vec_xxpermdi(vf, vf, 1);2141// CHECK: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 0, i32 3>2142// CHECK-LE: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 0, i32 3>2143 2144res_vsll = vec_xxpermdi(vsll, vsll, 2);2145// CHECK: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 1, i32 2>2146// CHECK-LE: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 1, i32 2>2147 2148res_vull = vec_xxpermdi(vull, vull, 3);2149// CHECK: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 1, i32 3>2150// CHECK-LE: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 1, i32 3>2151 2152res_vsi = vec_xxpermdi(vsi, vsi, 0);2153// CHECK: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 0, i32 2>2154// CHECK-LE: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 0, i32 2>2155 2156res_vui = vec_xxpermdi(vui, vui, 1);2157// CHECK: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 0, i32 3>2158// CHECK-LE: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 0, i32 3>2159 2160res_vss = vec_xxpermdi(vss, vss, 2);2161// CHECK: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 1, i32 2>2162// CHECK-LE: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 1, i32 2>2163 2164res_vus = vec_xxpermdi(vus, vus, 3);2165// CHECK: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 1, i32 3>2166// CHECK-LE: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 1, i32 3>2167 2168res_vsc = vec_xxpermdi(vsc, vsc, 0);2169// CHECK: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 0, i32 2>2170// CHECK-LE: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 0, i32 2>2171 2172res_vuc = vec_xxpermdi(vuc, vuc, 1);2173// CHECK: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 0, i32 3>2174// CHECK-LE: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 0, i32 3>2175 2176res_vd = vec_permi(vd, vd, 0);2177// CHECK: shufflevector <2 x double> %{{[0-9]+}}, <2 x double> %{{[0-9]+}}, <2 x i32> <i32 0, i32 2>2178// CHECK-LE: shufflevector <2 x double> %{{[0-9]+}}, <2 x double> %{{[0-9]+}}, <2 x i32> <i32 0, i32 2>2179 2180res_vsll = vec_permi(vsll, vsll, 2);2181// CHECK: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 1, i32 2>2182// CHECK-LE: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 1, i32 2>2183 2184res_vull = vec_permi(vull, vull, 3);2185// CHECK: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 1, i32 3>2186// CHECK-LE: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 1, i32 3>2187 2188res_vbll = vec_permi(vbll, vbll, 3);2189// CHECK: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 1, i32 3>2190// CHECK-LE: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 1, i32 3>2191 2192res_vd = vec_xxsldwi(vd, vd, 0);2193// CHECK: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 0, i32 1, i32 2, i32 3>2194// CHECK-LE: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 0, i32 1, i32 2, i32 3>2195 2196res_vf = vec_xxsldwi(vf, vf, 1);2197// CHECK: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 1, i32 2, i32 3, i32 4>2198// CHECK-LE: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 7, i32 0, i32 1, i32 2>2199 2200res_vsll = vec_xxsldwi(vsll, vsll, 2);2201// CHECK: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 2, i32 3, i32 4, i32 5>2202// CHECK-LE: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 6, i32 7, i32 0, i32 1>2203 2204res_vull = vec_xxsldwi(vull, vull, 3);2205// CHECK: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 3, i32 4, i32 5, i32 6>2206// CHECK-LE: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 5, i32 6, i32 7, i32 0>2207 2208res_vsi = vec_xxsldwi(vsi, vsi, 0);2209// CHECK: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 0, i32 1, i32 2, i32 3>2210// CHECK-LE: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 0, i32 1, i32 2, i32 3>2211 2212res_vui = vec_xxsldwi(vui, vui, 1);2213// CHECK: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 1, i32 2, i32 3, i32 4>2214// CHECK-LE: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 7, i32 0, i32 1, i32 2>2215 2216res_vss = vec_xxsldwi(vss, vss, 2);2217// CHECK: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 2, i32 3, i32 4, i32 5>2218// CHECK-LE: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 6, i32 7, i32 0, i32 1>2219 2220 2221res_vus = vec_xxsldwi(vus, vus, 3);2222// CHECK: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 3, i32 4, i32 5, i32 6>2223// CHECK-LE: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 5, i32 6, i32 7, i32 0>2224 2225res_vsc = vec_xxsldwi(vsc, vsc, 0);2226// CHECK: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 0, i32 1, i32 2, i32 3>2227// CHECK-LE: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 0, i32 1, i32 2, i32 3>2228 2229res_vuc = vec_xxsldwi(vuc, vuc, 1);2230// CHECK: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 1, i32 2, i32 3, i32 4>2231// CHECK-LE: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 7, i32 0, i32 1, i32 2>2232 2233res_vd = vec_promote(d, 0);2234// CHECK: store <2 x double> zeroinitializer2235// CHECK: store <2 x double> poison2236// CHECK: insertelement <2 x double>2237// CHECK-LE: store <2 x double> zeroinitializer2238// CHECK-LE: store <2 x double> poison2239// CHECK-LE: insertelement <2 x double>2240 2241res_vsll = vec_promote(sll, 0);2242// CHECK: store <2 x i64> zeroinitializer2243// CHECK: store <2 x i64> poison2244// CHECK: insertelement <2 x i64>2245// CHECK-LE: store <2 x i64> zeroinitializer2246// CHECK-LE: store <2 x i64> poison2247// CHECK-LE: insertelement <2 x i64>2248 2249res_vull = vec_promote(ull, 0);2250// CHECK: store <2 x i64> zeroinitializer2251// CHECK: store <2 x i64> poison2252// CHECK: insertelement <2 x i64>2253// CHECK-LE: store <2 x i64> zeroinitializer2254// CHECK-LE: store <2 x i64> poison2255// CHECK-LE: insertelement <2 x i64>2256 2257res_vsc = vec_promote(asc[0], 8);2258// CHECK: store <16 x i8> zeroinitializer2259// CHECK: store <16 x i8> poison2260// CHECK: [[IDX:%.*]] = and i32 {{.*}}, 152261// CHECK: insertelement <16 x i8> {{.*}}, i8 {{.*}}, i32 [[IDX]]2262// CHECK-LE: store <16 x i8> zeroinitializer2263// CHECK-LE: store <16 x i8> poison2264// CHECK-LE: [[IDX:%.*]] = and i32 {{.*}}, 152265// CHECK-LE: insertelement <16 x i8> {{.*}}, i8 {{.*}}, i32 [[IDX]]2266 2267res_vuc = vec_promote(auc[0], 8);2268// CHECK: store <16 x i8> zeroinitializer2269// CHECK: store <16 x i8> poison2270// CHECK: [[IDX:%.*]] = and i32 {{.*}}, 152271// CHECK: insertelement <16 x i8> {{.*}}, i8 {{.*}}, i32 [[IDX]]2272// CHECK-LE: store <16 x i8> zeroinitializer2273// CHECK-LE: store <16 x i8> poison2274// CHECK-LE: [[IDX:%.*]] = and i32 {{.*}}, 152275// CHECK-LE: insertelement <16 x i8> {{.*}}, i8 {{.*}}, i32 [[IDX]]2276}2277 2278// The return type of the call expression may be different from the return type of the shufflevector.2279// Wrong implementation could crash the compiler, add this test case to check that and avoid ICE.2280vector int xxpermdi_should_not_assert(vector int a, vector int b) {2281  return vec_xxpermdi(a, b, 0);2282// CHECK-LABEL: xxpermdi_should_not_assert2283// CHECK:  bitcast <4 x i32> %{{[0-9]+}} to <2 x i64>2284// CHECK-NEXT:  bitcast <4 x i32> %{{[0-9]+}} to <2 x i64>2285// CHECK-NEXT:  shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 0, i32 2>2286// CHECK-NEXT:  bitcast <2 x i64> %{{[0-9]+}} to <4 x i32>2287 2288// CHECK-LE:  bitcast <4 x i32> %{{[0-9]+}} to <2 x i64>2289// CHECK-LE-NEXT:  bitcast <4 x i32> %{{[0-9]+}} to <2 x i64>2290// CHECK-LE-NEXT:  shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 0, i32 2>2291// CHECK-LE-NEXT:  bitcast <2 x i64> %{{[0-9]+}} to <4 x i32>2292}2293 2294vector double xxsldwi_should_not_assert(vector double a, vector double b) {2295  return vec_xxsldwi(a, b, 0);2296// CHECK-LABEL: xxsldwi_should_not_assert2297// CHECK:  bitcast <2 x double> %{{[0-9]+}} to <4 x i32>2298// CHECK-NEXT:  bitcast <2 x double> %{{[0-9]+}} to <4 x i32>2299// CHECK-NEXT:  shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 0, i32 1, i32 2, i32 3>2300// CHECK-NEXT:  bitcast <4 x i32> %{{[0-9]+}} to <2 x double>2301 2302// CHECK-LE:  bitcast <2 x double> %{{[0-9]+}} to <4 x i32>2303// CHECK-NEXT-LE:  bitcast <2 x double> %{{[0-9]+}} to <4 x i32>2304// CHECK-NEXT-LE:  shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 0, i32 1, i32 2, i32 3>2305// CHECK-NEXT-LE:  bitcast <4 x i32> %{{[0-9]+}} to <2 x double>2306}2307 2308void test_vector_cpsgn_float(vector float a, vector float b) {2309// CHECK-LABEL: test_vector_cpsgn_float2310// CHECK-NOT: SEPARATOR2311// CHECK-DAG: [[RA:%[0-9]+]] = load <4 x float>, ptr %__a.addr2312// CHECK-DAG: [[RB:%[0-9]+]] = load <4 x float>, ptr %__b.addr2313// CHECK-NEXT: call <4 x float> @llvm.copysign.v4f32(<4 x float> [[RB]], <4 x float> [[RA]])2314  vec_cpsgn(a, b);2315}2316 2317void test_vector_cpsgn_double(vector double a, vector double b) {2318// CHECK-LABEL: test_vector_cpsgn_double2319// CHECK-NOT: SEPARATOR2320// CHECK-DAG: [[RA:%[0-9]+]] = load <2 x double>, ptr %__a.addr2321// CHECK-DAG: [[RB:%[0-9]+]] = load <2 x double>, ptr %__b.addr2322// CHECK-NEXT: call <2 x double> @llvm.copysign.v2f64(<2 x double> [[RB]], <2 x double> [[RA]])2323  vec_cpsgn(a, b);2324}2325 2326void test_builtin_xvcpsgnsp(vector float a, vector float b) {2327// CHECK-LABEL: test_builtin_xvcpsgnsp2328// CHECK-NOT: SEPARATOR2329// CHECK-DAG: [[RA:%[0-9]+]] = load <4 x float>, ptr %a.addr2330// CHECK-DAG: [[RB:%[0-9]+]] = load <4 x float>, ptr %b.addr2331// CHECK-NEXT: call <4 x float> @llvm.copysign.v4f32(<4 x float> [[RA]], <4 x float> [[RB]])2332  __builtin_vsx_xvcpsgnsp(a, b);2333}2334 2335void test_builtin_xvcpsgndp(vector double a, vector double b) {2336// CHECK-LABEL: test_builtin_xvcpsgndp2337// CHECK-NOT: SEPARATOR2338// CHECK-DAG: [[RA:%[0-9]+]] = load <2 x double>, ptr %a.addr2339// CHECK-DAG: [[RB:%[0-9]+]] = load <2 x double>, ptr %b.addr2340// CHECK-NEXT: call <2 x double> @llvm.copysign.v2f64(<2 x double> [[RA]], <2 x double> [[RB]])2341  __builtin_vsx_xvcpsgndp(a, b);2342}2343 2344vector double test_recipdivd(vector double a, vector double b) {2345  // CHECK-LABEL: test_recipdivd2346  // CHECK: fdiv fast <2 x double>2347  // CHECK-LE-LABEL: test_recipdivd2348  // CHECK-LE: fdiv fast <2 x double>2349  return vec_recipdiv(a, b);2350}2351 2352vector double test_rsqrtd(vector double a, vector double b) {2353  // CHECK-LABEL: test_rsqrtd2354  // CHECK: call fast <2 x double> @llvm.sqrt.v2f642355  // CHECK: fdiv fast <2 x double> splat (double 1.000000e+00),2356  // CHECK-LE-LABEL: test_rsqrtd2357  // CHECK-LE: call fast <2 x double> @llvm.sqrt.v2f642358  // CHECK-LE: fdiv fast <2 x double> splat (double 1.000000e+00)2359  return vec_rsqrt(a);2360}2361 2362void test_p8overloads_backwards_compat() {2363  // CHECK-LABEL: test_p8overloads_backwards_compat2364  res_vsll = vec_add(vsll, vsll);2365  // CHECK: add <4 x i32>2366  // CHECK: call <4 x i32> @llvm.ppc.altivec.vaddcuw2367  // CHECK: shufflevector <16 x i8> {{%.*}}, <16 x i8> {{%.*}}, <16 x i32> <i32 0, i32 0, i32 0, i32 7, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 15, i32 0, i32 0, i32 0, i32 0>2368  // CHECK: add <4 x i32>2369  // CHECK-LE: add <2 x i64>2370  res_vull = vec_add(vull, vull);2371  // CHECK: add <4 x i32>2372  // CHECK: call <4 x i32> @llvm.ppc.altivec.vaddcuw2373  // CHECK: shufflevector <16 x i8> {{%.*}}, <16 x i8> {{%.*}}, <16 x i32> <i32 0, i32 0, i32 0, i32 7, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 15, i32 0, i32 0, i32 0, i32 0>2374  // CHECK: add <4 x i32>2375  // CHECK-LE: add <2 x i64>2376  dummy();2377  // CHECK: call void @dummy()2378  // CHECK-LE: call void @dummy()2379 2380  res_vbll = vec_cmpeq(vsll, vsll);2381  // CHECK: call <4 x i32> @llvm.ppc.altivec.vcmpequw2382  // CHECK: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 1, i32 2, i32 3, i32 0>2383  // CHECK: and <4 x i32>2384  // CHECK: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 0, i32 0, i32 2, i32 2>2385  // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vcmpequw2386  // CHECK-LE: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 3, i32 0, i32 1, i32 2>2387  // CHECK-LE: and <4 x i32>2388  // CHECK-LE: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 1, i32 1, i32 3, i32 3>2389  res_vbll = vec_cmpeq(vull, vull);2390  // CHECK: call <4 x i32> @llvm.ppc.altivec.vcmpequw2391  // CHECK: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 1, i32 2, i32 3, i32 0>2392  // CHECK: and <4 x i32>2393  // CHECK: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 0, i32 0, i32 2, i32 2>2394  // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vcmpequw2395  // CHECK-LE: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 3, i32 0, i32 1, i32 2>2396  // CHECK-LE: and <4 x i32>2397  // CHECK-LE: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 1, i32 1, i32 3, i32 3>2398  res_vbll = vec_cmpeq(vbll, vbll);2399  // CHECK: call <4 x i32> @llvm.ppc.altivec.vcmpequw2400  // CHECK: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 1, i32 2, i32 3, i32 0>2401  // CHECK: and <4 x i32>2402  // CHECK: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 0, i32 0, i32 2, i32 2>2403  // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vcmpequw2404  // CHECK-LE: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 3, i32 0, i32 1, i32 2>2405  // CHECK-LE: and <4 x i32>2406  // CHECK-LE: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 1, i32 1, i32 3, i32 3>2407  dummy();2408  // CHECK: call void @dummy()2409  // CHECK-LE: call void @dummy()2410 2411  res_vbll = vec_cmpgt(vsll, vsll);2412  // CHECK: call <4 x i32> @llvm.ppc.altivec.vcmpgtsw2413  // CHECK: call <4 x i32> @llvm.ppc.altivec.vcmpgtuw2414  // CHECK: call <4 x i32> @llvm.ppc.altivec.vcmpequw2415  // CHECK: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 1, i32 2, i32 3, i32 0>2416  // CHECK: and <4 x i32>2417  // CHECK: or <4 x i32>2418  // CHECK: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 0, i32 0, i32 2, i32 2>2419  // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vcmpgtsw2420  // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vcmpgtuw2421  // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vcmpequw2422  // CHECK-LE: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 3, i32 0, i32 1, i32 2>2423  // CHECK-LE: and <4 x i32>2424  // CHECK-LE: or <4 x i32>2425  // CHECK-LE: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 1, i32 1, i32 3, i32 3>2426  res_vbll = vec_cmpgt(vull, vull);2427  // CHECK: call <4 x i32> @llvm.ppc.altivec.vcmpgtuw2428  // CHECK: call <4 x i32> @llvm.ppc.altivec.vcmpequw2429  // CHECK: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 1, i32 2, i32 3, i32 0>2430  // CHECK: and <4 x i32>2431  // CHECK: or <4 x i32>2432  // CHECK: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 0, i32 0, i32 2, i32 2>2433  // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vcmpgtuw2434  // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vcmpequw2435  // CHECK-LE: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 3, i32 0, i32 1, i32 2>2436  // CHECK-LE: and <4 x i32>2437  // CHECK-LE: or <4 x i32>2438  // CHECK-LE: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 1, i32 1, i32 3, i32 3>2439  dummy();2440  // CHECK: call void @dummy()2441  // CHECK-LE: call void @dummy()2442 2443  res_vbll = vec_cmpge(vsll, vsll);2444  // CHECK: call <4 x i32> @llvm.ppc.altivec.vcmpgtsw2445  // CHECK: call <4 x i32> @llvm.ppc.altivec.vcmpgtuw2446  // CHECK: call <4 x i32> @llvm.ppc.altivec.vcmpequw2447  // CHECK: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 1, i32 2, i32 3, i32 0>2448  // CHECK: and <4 x i32>2449  // CHECK: or <4 x i32>2450  // CHECK: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 0, i32 0, i32 2, i32 2>2451  // CHECK: xor <2 x i64> {{%.*}}, splat (i64 -1)2452  // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vcmpgtsw2453  // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vcmpgtuw2454  // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vcmpequw2455  // CHECK-LE: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 3, i32 0, i32 1, i32 2>2456  // CHECK-LE: and <4 x i32>2457  // CHECK-LE: or <4 x i32>2458  // CHECK-LE: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 1, i32 1, i32 3, i32 3>2459  // CHECK-LE: xor <2 x i64> {{%.*}}, splat (i64 -1)2460  res_vbll = vec_cmpge(vull, vull);2461  // CHECK: call <4 x i32> @llvm.ppc.altivec.vcmpgtuw2462  // CHECK: call <4 x i32> @llvm.ppc.altivec.vcmpequw2463  // CHECK: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 1, i32 2, i32 3, i32 0>2464  // CHECK: and <4 x i32>2465  // CHECK: or <4 x i32>2466  // CHECK: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 0, i32 0, i32 2, i32 2>2467  // CHECK: xor <2 x i64> {{%.*}}, splat (i64 -1)2468  // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vcmpgtuw2469  // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vcmpequw2470  // CHECK-LE: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 3, i32 0, i32 1, i32 2>2471  // CHECK-LE: and <4 x i32>2472  // CHECK-LE: or <4 x i32>2473  // CHECK-LE: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 1, i32 1, i32 3, i32 3>2474  // CHECK-LE: xor <2 x i64> {{%.*}}, splat (i64 -1)2475  dummy();2476  // CHECK: call void @dummy()2477  // CHECK-LE: call void @dummy()2478 2479  res_vbll = vec_cmplt(vsll, vsll);2480  // CHECK: call <4 x i32> @llvm.ppc.altivec.vcmpgtsw2481  // CHECK: call <4 x i32> @llvm.ppc.altivec.vcmpgtuw2482  // CHECK: call <4 x i32> @llvm.ppc.altivec.vcmpequw2483  // CHECK: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 1, i32 2, i32 3, i32 0>2484  // CHECK: and <4 x i32>2485  // CHECK: or <4 x i32>2486  // CHECK: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 0, i32 0, i32 2, i32 2>2487  // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vcmpgtsw2488  // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vcmpgtuw2489  // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vcmpequw2490  // CHECK-LE: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 3, i32 0, i32 1, i32 2>2491  // CHECK-LE: and <4 x i32>2492  // CHECK-LE: or <4 x i32>2493  // CHECK-LE: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 1, i32 1, i32 3, i32 3>2494  res_vbll = vec_cmplt(vull, vull);2495  // CHECK: call <4 x i32> @llvm.ppc.altivec.vcmpgtuw2496  // CHECK: call <4 x i32> @llvm.ppc.altivec.vcmpequw2497  // CHECK: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 1, i32 2, i32 3, i32 0>2498  // CHECK: and <4 x i32>2499  // CHECK: or <4 x i32>2500  // CHECK: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 0, i32 0, i32 2, i32 2>2501  // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vcmpgtuw2502  // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vcmpequw2503  // CHECK-LE: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 3, i32 0, i32 1, i32 2>2504  // CHECK-LE: and <4 x i32>2505  // CHECK-LE: or <4 x i32>2506  // CHECK-LE: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 1, i32 1, i32 3, i32 3>2507  dummy();2508  // CHECK: call void @dummy()2509  // CHECK-LE: call void @dummy()2510 2511  res_vbll = vec_cmple(vsll, vsll);2512  // CHECK: call <4 x i32> @llvm.ppc.altivec.vcmpgtsw2513  // CHECK: call <4 x i32> @llvm.ppc.altivec.vcmpgtuw2514  // CHECK: call <4 x i32> @llvm.ppc.altivec.vcmpequw2515  // CHECK: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 1, i32 2, i32 3, i32 0>2516  // CHECK: and <4 x i32>2517  // CHECK: or <4 x i32>2518  // CHECK: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 0, i32 0, i32 2, i32 2>2519  // CHECK: xor <2 x i64> {{%.*}}, splat (i64 -1)2520  // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vcmpgtsw2521  // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vcmpgtuw2522  // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vcmpequw2523  // CHECK-LE: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 3, i32 0, i32 1, i32 2>2524  // CHECK-LE: and <4 x i32>2525  // CHECK-LE: or <4 x i32>2526  // CHECK-LE: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 1, i32 1, i32 3, i32 3>2527  // CHECK-LE: xor <2 x i64> {{%.*}}, splat (i64 -1)2528  res_vbll = vec_cmple(vull, vull);2529  // CHECK: call <4 x i32> @llvm.ppc.altivec.vcmpgtuw2530  // CHECK: call <4 x i32> @llvm.ppc.altivec.vcmpequw2531  // CHECK: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 1, i32 2, i32 3, i32 0>2532  // CHECK: and <4 x i32>2533  // CHECK: or <4 x i32>2534  // CHECK: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 0, i32 0, i32 2, i32 2>2535  // CHECK: xor <2 x i64> {{%.*}}, splat (i64 -1)2536  // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vcmpgtuw2537  // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vcmpequw2538  // CHECK-LE: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 3, i32 0, i32 1, i32 2>2539  // CHECK-LE: and <4 x i32>2540  // CHECK-LE: or <4 x i32>2541  // CHECK-LE: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 1, i32 1, i32 3, i32 3>2542  // CHECK-LE: xor <2 x i64> {{%.*}}, splat (i64 -1)2543  dummy();2544  // CHECK: call void @dummy()2545  // CHECK-LE: call void @dummy()2546 2547  res_vsll = vec_sl(vsll, vull);2548  // CHECK: urem <2 x i64> {{%.*}}, splat (i64 64)2549  // CHECK: call <4 x i32> @llvm.ppc.altivec.vslo2550  // CHECK: call <4 x i32> @llvm.ppc.altivec.vsl2551  // CHECK: shufflevector <2 x i64> {{%.*}}, <2 x i64> {{%.*}}, <2 x i32> <i32 1, i32 0>2552  // CHECK: shufflevector <2 x i64> {{%.*}}, <2 x i64> {{%.*}}, <2 x i32> <i32 1, i32 0>2553  // CHECK: call <4 x i32> @llvm.ppc.altivec.vslo2554  // CHECK: call <4 x i32> @llvm.ppc.altivec.vsl2555  // CHECK: shufflevector <2 x i64> {{%.*}}, <2 x i64> {{%.*}}, <2 x i32> <i32 1, i32 3>2556  // CHECK-LE: urem <2 x i64> {{%.*}}, splat (i64 64)2557  // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vslo2558  // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vsl2559  // CHECK-LE: shufflevector <2 x i64> {{%.*}}, <2 x i64> {{%.*}}, <2 x i32> <i32 1, i32 0>2560  // CHECK-LE: shufflevector <2 x i64> {{%.*}}, <2 x i64> {{%.*}}, <2 x i32> <i32 1, i32 0>2561  // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vslo2562  // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vsl2563  // CHECK-LE: shufflevector <2 x i64> {{%.*}}, <2 x i64> {{%.*}}, <2 x i32> <i32 0, i32 2>2564  res_vull = vec_sl(vull, vull);2565  // CHECK: urem <2 x i64> {{%.*}}, splat (i64 64)2566  // CHECK: call <4 x i32> @llvm.ppc.altivec.vslo2567  // CHECK: call <4 x i32> @llvm.ppc.altivec.vsl2568  // CHECK: shufflevector <2 x i64> {{%.*}}, <2 x i64> {{%.*}}, <2 x i32> <i32 1, i32 0>2569  // CHECK: shufflevector <2 x i64> {{%.*}}, <2 x i64> {{%.*}}, <2 x i32> <i32 1, i32 0>2570  // CHECK: call <4 x i32> @llvm.ppc.altivec.vslo2571  // CHECK: call <4 x i32> @llvm.ppc.altivec.vsl2572  // CHECK: shufflevector <2 x i64> {{%.*}}, <2 x i64> {{%.*}}, <2 x i32> <i32 1, i32 3>2573  // CHECK-LE: urem <2 x i64> {{%.*}}, splat (i64 64)2574  // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vslo2575  // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vsl2576  // CHECK-LE: shufflevector <2 x i64> {{%.*}}, <2 x i64> {{%.*}}, <2 x i32> <i32 1, i32 0>2577  // CHECK-LE: shufflevector <2 x i64> {{%.*}}, <2 x i64> {{%.*}}, <2 x i32> <i32 1, i32 0>2578  // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vslo2579  // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vsl2580  // CHECK-LE: shufflevector <2 x i64> {{%.*}}, <2 x i64> {{%.*}}, <2 x i32> <i32 0, i32 2>2581  dummy();2582  // CHECK: call void @dummy()2583  // CHECK-LE: call void @dummy()2584 2585  res_vsll = vec_sr(vsll, vull);2586  // CHECK: urem <2 x i64> {{%.*}}, splat (i64 64)2587  // CHECK: shufflevector <2 x i64> {{%.*}}, <2 x i64> {{%.*}}, <2 x i32> <i32 1, i32 0>2588  // CHECK: call <4 x i32> @llvm.ppc.altivec.vsro2589  // CHECK: call <4 x i32> @llvm.ppc.altivec.vsr2590  // CHECK: shufflevector <2 x i64> {{%.*}}, <2 x i64> {{%.*}}, <2 x i32> <i32 1, i32 0>2591  // CHECK: call <4 x i32> @llvm.ppc.altivec.vsro2592  // CHECK: call <4 x i32> @llvm.ppc.altivec.vsr2593  // CHECK: shufflevector <2 x i64> {{%.*}}, <2 x i64> {{%.*}}, <2 x i32> <i32 0, i32 2>2594  // CHECK-LE: urem <2 x i64> {{%.*}}, splat (i64 64)2595  // CHECK-LE: shufflevector <2 x i64> {{%.*}}, <2 x i64> {{%.*}}, <2 x i32> <i32 1, i32 0>2596  // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vsro2597  // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vsr2598  // CHECK-LE: shufflevector <2 x i64> {{%.*}}, <2 x i64> {{%.*}}, <2 x i32> <i32 1, i32 0>2599  // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vsro2600  // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vsr2601  // CHECK-LE: shufflevector <2 x i64> {{%.*}}, <2 x i64> {{%.*}}, <2 x i32> <i32 1, i32 3>2602  res_vull = vec_sr(vull, vull);2603  // CHECK: urem <2 x i64> {{%.*}}, splat (i64 64)2604  // CHECK: shufflevector <2 x i64> {{%.*}}, <2 x i64> {{%.*}}, <2 x i32> <i32 1, i32 0>2605  // CHECK: call <4 x i32> @llvm.ppc.altivec.vsro2606  // CHECK: call <4 x i32> @llvm.ppc.altivec.vsr2607  // CHECK: shufflevector <2 x i64> {{%.*}}, <2 x i64> {{%.*}}, <2 x i32> <i32 1, i32 0>2608  // CHECK: call <4 x i32> @llvm.ppc.altivec.vsro2609  // CHECK: call <4 x i32> @llvm.ppc.altivec.vsr2610  // CHECK: shufflevector <2 x i64> {{%.*}}, <2 x i64> {{%.*}}, <2 x i32> <i32 0, i32 2>2611  // CHECK-LE: urem <2 x i64> {{%.*}}, splat (i64 64)2612  // CHECK-LE: shufflevector <2 x i64> {{%.*}}, <2 x i64> {{%.*}}, <2 x i32> <i32 1, i32 0>2613  // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vsro2614  // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vsr2615  // CHECK-LE: shufflevector <2 x i64> {{%.*}}, <2 x i64> {{%.*}}, <2 x i32> <i32 1, i32 0>2616  // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vsro2617  // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vsr2618  // CHECK-LE: shufflevector <2 x i64> {{%.*}}, <2 x i64> {{%.*}}, <2 x i32> <i32 1, i32 3>2619  dummy();2620  // CHECK: call void @dummy()2621  // CHECK-LE: call void @dummy()2622 2623  res_vsll = vec_sra(vsll, vull);2624  // CHECK: urem <2 x i64> {{%.*}}, splat (i64 64)2625  // CHECK: ashr <2 x i64>2626  // CHECK-LE: urem <2 x i64> {{%.*}}, splat (i64 64)2627  // CHECK-LE: ashr <2 x i64>2628  res_vull = vec_sra(vull, vull);2629  // CHECK: urem <2 x i64> {{%.*}}, splat (i64 64)2630  // CHECK: ashr <2 x i64>2631  // CHECK-LE: urem <2 x i64> {{%.*}}, splat (i64 64)2632  // CHECK-LE: ashr <2 x i64>2633 2634  /* ----------------------- predicates --------------------------- */2635  /* vec_all_eq */2636  res_i = vec_all_eq(vsll, vsll);2637  // CHECK: xor <2 x i64>2638  // CHECK: @llvm.ppc.altivec.vcmpequw.p2639  // CHECK-LE: xor <2 x i64>2640  // CHECK-LE: @llvm.ppc.altivec.vcmpequw.p2641 2642  res_i = vec_all_eq(vsll, vbll);2643  // CHECK: xor <2 x i64>2644  // CHECK: @llvm.ppc.altivec.vcmpequw.p2645  // CHECK-LE: xor <2 x i64>2646  // CHECK-LE: @llvm.ppc.altivec.vcmpequw.p2647 2648  res_i = vec_all_eq(vull, vull);2649  // CHECK: xor <2 x i64>2650  // CHECK: @llvm.ppc.altivec.vcmpequw.p2651  // CHECK-LE: xor <2 x i64>2652  // CHECK-LE: @llvm.ppc.altivec.vcmpequw.p2653 2654  res_i = vec_all_eq(vull, vbll);2655  // CHECK: xor <2 x i64>2656  // CHECK: @llvm.ppc.altivec.vcmpequw.p2657  // CHECK-LE: xor <2 x i64>2658  // CHECK-LE: @llvm.ppc.altivec.vcmpequw.p2659 2660  res_i = vec_all_eq(vbll, vsll);2661  // CHECK: xor <2 x i64>2662  // CHECK: @llvm.ppc.altivec.vcmpequw.p2663  // CHECK-LE: xor <2 x i64>2664  // CHECK-LE: @llvm.ppc.altivec.vcmpequw.p2665 2666  res_i = vec_all_eq(vbll, vull);2667  // CHECK: xor <2 x i64>2668  // CHECK: @llvm.ppc.altivec.vcmpequw.p2669  // CHECK-LE: xor <2 x i64>2670  // CHECK-LE: @llvm.ppc.altivec.vcmpequw.p2671 2672  res_i = vec_all_eq(vbll, vbll);2673  // CHECK: xor <2 x i64>2674  // CHECK: @llvm.ppc.altivec.vcmpequw.p2675  // CHECK-LE: xor <2 x i64>2676  // CHECK-LE: @llvm.ppc.altivec.vcmpequw.p2677 2678  /* vec_all_ne */2679  res_i = vec_all_ne(vsll, vsll);2680  // CHECK: @llvm.ppc.altivec.vcmpequd.p2681  // CHECK-LE: @llvm.ppc.altivec.vcmpequd.p2682 2683  res_i = vec_all_ne(vsll, vbll);2684  // CHECK: @llvm.ppc.altivec.vcmpequd.p2685  // CHECK-LE: @llvm.ppc.altivec.vcmpequd.p2686 2687  res_i = vec_all_ne(vull, vull);2688  // CHECK: @llvm.ppc.altivec.vcmpequd.p2689  // CHECK-LE: @llvm.ppc.altivec.vcmpequd.p2690 2691  res_i = vec_all_ne(vull, vbll);2692  // CHECK: @llvm.ppc.altivec.vcmpequd.p2693  // CHECK-LE: @llvm.ppc.altivec.vcmpequd.p2694 2695  res_i = vec_all_ne(vbll, vsll);2696  // CHECK: @llvm.ppc.altivec.vcmpequd.p2697  // CHECK-LE: @llvm.ppc.altivec.vcmpequd.p2698 2699  res_i = vec_all_ne(vbll, vull);2700  // CHECK: @llvm.ppc.altivec.vcmpequd.p2701  // CHECK-LE: @llvm.ppc.altivec.vcmpequd.p2702 2703  res_i = vec_all_ne(vbll, vbll);2704  // CHECK: @llvm.ppc.altivec.vcmpequd.p2705  // CHECK-LE: @llvm.ppc.altivec.vcmpequd.p2706 2707  dummy();2708  // CHECK: @dummy2709 2710  /* vec_any_eq */2711  res_i = vec_any_eq(vsll, vsll);2712  // CHECK: @llvm.ppc.altivec.vcmpequd.p2713  // CHECK-LE: @llvm.ppc.altivec.vcmpequd.p2714 2715  res_i = vec_any_eq(vsll, vbll);2716  // CHECK: @llvm.ppc.altivec.vcmpequd.p2717  // CHECK-LE: @llvm.ppc.altivec.vcmpequd.p2718 2719  res_i = vec_any_eq(vull, vull);2720  // CHECK: @llvm.ppc.altivec.vcmpequd.p2721  // CHECK-LE: @llvm.ppc.altivec.vcmpequd.p2722 2723  res_i = vec_any_eq(vull, vbll);2724  // CHECK: @llvm.ppc.altivec.vcmpequd.p2725  // CHECK-LE: @llvm.ppc.altivec.vcmpequd.p2726 2727  res_i = vec_any_eq(vbll, vsll);2728  // CHECK: @llvm.ppc.altivec.vcmpequd.p2729  // CHECK-LE: @llvm.ppc.altivec.vcmpequd.p2730 2731  res_i = vec_any_eq(vbll, vull);2732  // CHECK: @llvm.ppc.altivec.vcmpequd.p2733  // CHECK-LE: @llvm.ppc.altivec.vcmpequd.p2734 2735  res_i = vec_any_eq(vbll, vbll);2736  // CHECK: @llvm.ppc.altivec.vcmpequd.p2737  // CHECK-LE: @llvm.ppc.altivec.vcmpequd.p2738 2739  /* vec_any_ne */2740  res_i = vec_any_ne(vsll, vsll);2741  // CHECK: xor <2 x i64>2742  // CHECK: @llvm.ppc.altivec.vcmpequw.p2743  // CHECK: xor i12744  // CHECK-LE: xor <2 x i64>2745  // CHECK-LE: @llvm.ppc.altivec.vcmpequw.p2746  // CHECK-LE: xor i12747 2748  res_i = vec_any_ne(vsll, vbll);2749  // CHECK: xor <2 x i64>2750  // CHECK: @llvm.ppc.altivec.vcmpequw.p2751  // CHECK: xor i12752  // CHECK-LE: xor <2 x i64>2753  // CHECK-LE: @llvm.ppc.altivec.vcmpequw.p2754  // CHECK-LE: xor i12755 2756  res_i = vec_any_ne(vull, vull);2757  // CHECK: xor <2 x i64>2758  // CHECK: @llvm.ppc.altivec.vcmpequw.p2759  // CHECK: xor i12760  // CHECK-LE: xor <2 x i64>2761  // CHECK-LE: @llvm.ppc.altivec.vcmpequw.p2762  // CHECK-LE: xor i12763 2764  res_i = vec_any_ne(vull, vbll);2765  // CHECK: xor <2 x i64>2766  // CHECK: @llvm.ppc.altivec.vcmpequw.p2767  // CHECK: xor i12768  // CHECK-LE: xor <2 x i64>2769  // CHECK-LE: @llvm.ppc.altivec.vcmpequw.p2770  // CHECK-LE: xor i12771 2772  res_i = vec_any_ne(vbll, vsll);2773  // CHECK: xor <2 x i64>2774  // CHECK: @llvm.ppc.altivec.vcmpequw.p2775  // CHECK: xor i12776  // CHECK-LE: xor <2 x i64>2777  // CHECK-LE: @llvm.ppc.altivec.vcmpequw.p2778  // CHECK-LE: xor i12779 2780  res_i = vec_any_ne(vbll, vull);2781  // CHECK: xor <2 x i64>2782  // CHECK: @llvm.ppc.altivec.vcmpequw.p2783  // CHECK: xor i12784  // CHECK-LE: xor <2 x i64>2785  // CHECK-LE: @llvm.ppc.altivec.vcmpequw.p2786  // CHECK-LE: xor i12787 2788  res_i = vec_any_ne(vbll, vbll);2789  // CHECK: xor <2 x i64>2790  // CHECK: @llvm.ppc.altivec.vcmpequw.p2791  // CHECK: xor i12792  // CHECK-LE: xor <2 x i64>2793  // CHECK-LE: @llvm.ppc.altivec.vcmpequw.p2794  // CHECK-LE: xor i12795 2796  /* vec_all_ge */2797  res_i = vec_all_ge(vsll, vsll);2798  // CHECK: @llvm.ppc.altivec.vcmpgtsd.p2799  // CHECK-LE: @llvm.ppc.altivec.vcmpgtsd.p2800 2801  res_i = vec_all_ge(vsll, vbll);2802  // CHECK: @llvm.ppc.altivec.vcmpgtsd.p2803  // CHECK-LE: @llvm.ppc.altivec.vcmpgtsd.p2804 2805  res_i = vec_all_ge(vull, vull);2806  // CHECK: @llvm.ppc.altivec.vcmpgtud.p2807  // CHECK-LE: @llvm.ppc.altivec.vcmpgtud.p2808 2809  res_i = vec_all_ge(vull, vbll);2810  // CHECK: @llvm.ppc.altivec.vcmpgtud.p2811  // CHECK-LE: @llvm.ppc.altivec.vcmpgtud.p2812 2813  res_i = vec_all_ge(vbll, vsll);2814  // CHECK: @llvm.ppc.altivec.vcmpgtsd.p2815  // CHECK-LE: @llvm.ppc.altivec.vcmpgtsd.p2816 2817  res_i = vec_all_ge(vbll, vull);2818  // CHECK: @llvm.ppc.altivec.vcmpgtud.p2819  // CHECK-LE: @llvm.ppc.altivec.vcmpgtud.p2820 2821  res_i = vec_all_ge(vbll, vbll);2822  // CHECK: @llvm.ppc.altivec.vcmpgtud.p2823  // CHECK-LE: @llvm.ppc.altivec.vcmpgtud.p2824 2825  /* vec_all_gt */2826  res_i = vec_all_gt(vsll, vsll);2827  // CHECK: @llvm.ppc.altivec.vcmpgtsd.p2828  // CHECK-LE: @llvm.ppc.altivec.vcmpgtsd.p2829 2830  res_i = vec_all_gt(vsll, vbll);2831  // CHECK: @llvm.ppc.altivec.vcmpgtsd.p2832  // CHECK-LE: @llvm.ppc.altivec.vcmpgtsd.p2833 2834  res_i = vec_all_gt(vull, vull);2835  // CHECK: @llvm.ppc.altivec.vcmpgtud.p2836  // CHECK-LE: @llvm.ppc.altivec.vcmpgtud.p2837 2838  res_i = vec_all_gt(vull, vbll);2839  // CHECK: @llvm.ppc.altivec.vcmpgtud.p2840  // CHECK-LE: @llvm.ppc.altivec.vcmpgtud.p2841 2842  res_i = vec_all_gt(vbll, vsll);2843  // CHECK: @llvm.ppc.altivec.vcmpgtsd.p2844  // CHECK-LE: @llvm.ppc.altivec.vcmpgtsd.p2845 2846  res_i = vec_all_gt(vbll, vull);2847  // CHECK: @llvm.ppc.altivec.vcmpgtud.p2848  // CHECK-LE: @llvm.ppc.altivec.vcmpgtud.p2849 2850  res_i = vec_all_gt(vbll, vbll);2851  // CHECK: @llvm.ppc.altivec.vcmpgtud.p2852  // CHECK-LE: @llvm.ppc.altivec.vcmpgtud.p2853 2854  /* vec_all_le */2855  res_i = vec_all_le(vsll, vsll);2856  // CHECK: @llvm.ppc.altivec.vcmpgtsd.p2857  // CHECK-LE: @llvm.ppc.altivec.vcmpgtsd.p2858 2859  res_i = vec_all_le(vsll, vbll);2860  // CHECK: @llvm.ppc.altivec.vcmpgtsd.p2861  // CHECK-LE: @llvm.ppc.altivec.vcmpgtsd.p2862 2863  res_i = vec_all_le(vull, vull);2864  // CHECK: @llvm.ppc.altivec.vcmpgtud.p2865  // CHECK-LE: @llvm.ppc.altivec.vcmpgtud.p2866 2867  res_i = vec_all_le(vull, vbll);2868  // CHECK: @llvm.ppc.altivec.vcmpgtud.p2869  // CHECK-LE: @llvm.ppc.altivec.vcmpgtud.p2870 2871  res_i = vec_all_le(vbll, vsll);2872  // CHECK: @llvm.ppc.altivec.vcmpgtsd.p2873  // CHECK-LE: @llvm.ppc.altivec.vcmpgtsd.p2874 2875  res_i = vec_all_le(vbll, vull);2876  // CHECK: @llvm.ppc.altivec.vcmpgtud.p2877  // CHECK-LE: @llvm.ppc.altivec.vcmpgtud.p2878 2879  res_i = vec_all_le(vbll, vbll);2880  // CHECK: @llvm.ppc.altivec.vcmpgtud.p2881  // CHECK-LE: @llvm.ppc.altivec.vcmpgtud.p2882 2883  /* vec_all_lt */2884  res_i = vec_all_lt(vsll, vsll);2885  // CHECK: @llvm.ppc.altivec.vcmpgtsd.p2886  // CHECK-LE: @llvm.ppc.altivec.vcmpgtsd.p2887 2888  res_i = vec_all_lt(vsll, vbll);2889  // CHECK: @llvm.ppc.altivec.vcmpgtsd.p2890  // CHECK-LE: @llvm.ppc.altivec.vcmpgtsd.p2891 2892  res_i = vec_all_lt(vull, vull);2893  // CHECK: @llvm.ppc.altivec.vcmpgtud.p2894  // CHECK-LE: @llvm.ppc.altivec.vcmpgtud.p2895 2896  res_i = vec_all_lt(vull, vbll);2897  // CHECK: @llvm.ppc.altivec.vcmpgtud.p2898  // CHECK-LE: @llvm.ppc.altivec.vcmpgtud.p2899 2900  res_i = vec_all_lt(vbll, vsll);2901  // CHECK: @llvm.ppc.altivec.vcmpgtsd.p2902  // CHECK-LE: @llvm.ppc.altivec.vcmpgtsd.p2903 2904  res_i = vec_all_lt(vbll, vull);2905  // CHECK: @llvm.ppc.altivec.vcmpgtud.p2906  // CHECK-LE: @llvm.ppc.altivec.vcmpgtud.p2907 2908  res_i = vec_all_lt(vbll, vbll);2909  // CHECK: @llvm.ppc.altivec.vcmpgtud.p2910  // CHECK-LE: @llvm.ppc.altivec.vcmpgtud.p2911 2912  /* vec_any_ge */2913  res_i = vec_any_ge(vsll, vsll);2914  // CHECK: @llvm.ppc.altivec.vcmpgtsd.p2915  // CHECK-LE: @llvm.ppc.altivec.vcmpgtsd.p2916 2917  res_i = vec_any_ge(vsll, vbll);2918  // CHECK: @llvm.ppc.altivec.vcmpgtsd.p2919  // CHECK-LE: @llvm.ppc.altivec.vcmpgtsd.p2920 2921  res_i = vec_any_ge(vull, vull);2922  // CHECK: @llvm.ppc.altivec.vcmpgtud.p2923  // CHECK-LE: @llvm.ppc.altivec.vcmpgtud.p2924 2925  res_i = vec_any_ge(vull, vbll);2926  // CHECK: @llvm.ppc.altivec.vcmpgtud.p2927  // CHECK-LE: @llvm.ppc.altivec.vcmpgtud.p2928 2929  res_i = vec_any_ge(vbll, vsll);2930  // CHECK: @llvm.ppc.altivec.vcmpgtsd.p2931  // CHECK-LE: @llvm.ppc.altivec.vcmpgtsd.p2932 2933  res_i = vec_any_ge(vbll, vull);2934  // CHECK: @llvm.ppc.altivec.vcmpgtud.p2935  // CHECK-LE: @llvm.ppc.altivec.vcmpgtud.p2936 2937  res_i = vec_any_ge(vbll, vbll);2938  // CHECK: @llvm.ppc.altivec.vcmpgtud.p2939  // CHECK-LE: @llvm.ppc.altivec.vcmpgtud.p2940 2941  /* vec_any_gt */2942  res_i = vec_any_gt(vsll, vsll);2943  // CHECK: @llvm.ppc.altivec.vcmpgtsd.p2944  // CHECK-LE: @llvm.ppc.altivec.vcmpgtsd.p2945 2946  res_i = vec_any_gt(vsll, vbll);2947  // CHECK: @llvm.ppc.altivec.vcmpgtsd.p2948  // CHECK-LE: @llvm.ppc.altivec.vcmpgtsd.p2949 2950  res_i = vec_any_gt(vull, vull);2951  // CHECK: @llvm.ppc.altivec.vcmpgtud.p2952  // CHECK-LE: @llvm.ppc.altivec.vcmpgtud.p2953 2954  res_i = vec_any_gt(vull, vbll);2955  // CHECK: @llvm.ppc.altivec.vcmpgtud.p2956  // CHECK-LE: @llvm.ppc.altivec.vcmpgtud.p2957 2958  res_i = vec_any_gt(vbll, vsll);2959  // CHECK: @llvm.ppc.altivec.vcmpgtsd.p2960  // CHECK-LE: @llvm.ppc.altivec.vcmpgtsd.p2961 2962  res_i = vec_any_gt(vbll, vull);2963  // CHECK: @llvm.ppc.altivec.vcmpgtud.p2964  // CHECK-LE: @llvm.ppc.altivec.vcmpgtud.p2965 2966  res_i = vec_any_gt(vbll, vbll);2967  // CHECK: @llvm.ppc.altivec.vcmpgtud.p2968  // CHECK-LE: @llvm.ppc.altivec.vcmpgtud.p2969 2970  /* vec_any_le */2971  res_i = vec_any_le(vsll, vsll);2972  // CHECK: @llvm.ppc.altivec.vcmpgtsd.p2973  // CHECK-LE: @llvm.ppc.altivec.vcmpgtsd.p2974 2975  res_i = vec_any_le(vsll, vbll);2976  // CHECK: @llvm.ppc.altivec.vcmpgtsd.p2977  // CHECK-LE: @llvm.ppc.altivec.vcmpgtsd.p2978 2979  res_i = vec_any_le(vull, vull);2980  // CHECK: @llvm.ppc.altivec.vcmpgtud.p2981  // CHECK-LE: @llvm.ppc.altivec.vcmpgtud.p2982 2983  res_i = vec_any_le(vull, vbll);2984  // CHECK: @llvm.ppc.altivec.vcmpgtud.p2985  // CHECK-LE: @llvm.ppc.altivec.vcmpgtud.p2986 2987  res_i = vec_any_le(vbll, vsll);2988  // CHECK: @llvm.ppc.altivec.vcmpgtsd.p2989  // CHECK-LE: @llvm.ppc.altivec.vcmpgtsd.p2990 2991  res_i = vec_any_le(vbll, vull);2992  // CHECK: @llvm.ppc.altivec.vcmpgtud.p2993  // CHECK-LE: @llvm.ppc.altivec.vcmpgtud.p2994 2995  res_i = vec_any_le(vbll, vbll);2996  // CHECK: @llvm.ppc.altivec.vcmpgtud.p2997  // CHECK-LE: @llvm.ppc.altivec.vcmpgtud.p2998 2999  /* vec_any_lt */3000  res_i = vec_any_lt(vsll, vsll);3001  // CHECK: @llvm.ppc.altivec.vcmpgtsd.p3002  // CHECK-LE: @llvm.ppc.altivec.vcmpgtsd.p3003 3004  res_i = vec_any_lt(vsll, vbll);3005  // CHECK: @llvm.ppc.altivec.vcmpgtsd.p3006  // CHECK-LE: @llvm.ppc.altivec.vcmpgtsd.p3007 3008  res_i = vec_any_lt(vull, vull);3009  // CHECK: @llvm.ppc.altivec.vcmpgtud.p3010  // CHECK-LE: @llvm.ppc.altivec.vcmpgtud.p3011 3012  res_i = vec_any_lt(vull, vbll);3013  // CHECK: @llvm.ppc.altivec.vcmpgtud.p3014  // CHECK-LE: @llvm.ppc.altivec.vcmpgtud.p3015 3016  res_i = vec_any_lt(vbll, vsll);3017  // CHECK: @llvm.ppc.altivec.vcmpgtsd.p3018  // CHECK-LE: @llvm.ppc.altivec.vcmpgtsd.p3019 3020  res_i = vec_any_lt(vbll, vull);3021  // CHECK: @llvm.ppc.altivec.vcmpgtud.p3022  // CHECK-LE: @llvm.ppc.altivec.vcmpgtud.p3023 3024  res_i = vec_any_lt(vbll, vbll);3025  // CHECK: @llvm.ppc.altivec.vcmpgtud.p3026  // CHECK-LE: @llvm.ppc.altivec.vcmpgtud.p3027}3028