476 lines · c
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py2// REQUIRES: powerpc-registered-target3// RUN: %clang_cc1 -flax-vector-conversions=none -target-feature +altivec -target-feature +vsx \4// RUN: -triple powerpc64-unknown-unknown -emit-llvm %s -o - | FileCheck %s5// RUN: %clang_cc1 -flax-vector-conversions=none -target-feature +altivec -target-feature +vsx \6// RUN: -target-feature +power8-vector -triple powerpc64le-unknown-unknown \7// RUN: -emit-llvm %s -o - | FileCheck %s -check-prefixes=CHECK,CHECK-P88#include <altivec.h>9 10// CHECK-LABEL: @test1(11// CHECK-NEXT: entry:12// CHECK-NEXT: [[__VEC_ADDR_I:%.*]] = alloca <8 x i16>, align 1613// CHECK-NEXT: [[__OFFSET_ADDR_I1:%.*]] = alloca i64, align 814// CHECK-NEXT: [[__PTR_ADDR_I2:%.*]] = alloca ptr, align 815// CHECK-NEXT: [[__ADDR_I3:%.*]] = alloca ptr, align 816// CHECK-NEXT: [[__OFFSET_ADDR_I:%.*]] = alloca i64, align 817// CHECK-NEXT: [[__PTR_ADDR_I:%.*]] = alloca ptr, align 818// CHECK-NEXT: [[__ADDR_I:%.*]] = alloca ptr, align 819// CHECK-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 820// CHECK-NEXT: [[ST_ADDR:%.*]] = alloca ptr, align 821// CHECK-NEXT: [[LD_ADDR:%.*]] = alloca ptr, align 822// CHECK-NEXT: store ptr [[C:%.*]], ptr [[C_ADDR]], align 823// CHECK-NEXT: store ptr [[ST:%.*]], ptr [[ST_ADDR]], align 824// CHECK-NEXT: store ptr [[LD:%.*]], ptr [[LD_ADDR]], align 825// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[LD_ADDR]], align 826// CHECK-NEXT: store i64 3, ptr [[__OFFSET_ADDR_I]], align 827// CHECK-NEXT: store ptr [[TMP0]], ptr [[__PTR_ADDR_I]], align 828// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__PTR_ADDR_I]], align 829// CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr [[__OFFSET_ADDR_I]], align 830// CHECK-NEXT: [[ADD_PTR_I:%.*]] = getelementptr inbounds i8, ptr [[TMP1]], i64 [[TMP3]]31// CHECK-NEXT: store ptr [[ADD_PTR_I]], ptr [[__ADDR_I]], align 832// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[__ADDR_I]], align 833// CHECK-NEXT: [[TMP6:%.*]] = load <8 x i16>, ptr [[TMP4]], align 134// CHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[C_ADDR]], align 835// CHECK-NEXT: store <8 x i16> [[TMP6]], ptr [[TMP7]], align 1636// CHECK-NEXT: [[TMP8:%.*]] = load ptr, ptr [[C_ADDR]], align 837// CHECK-NEXT: [[TMP9:%.*]] = load <8 x i16>, ptr [[TMP8]], align 1638// CHECK-NEXT: [[TMP10:%.*]] = load ptr, ptr [[ST_ADDR]], align 839// CHECK-NEXT: store <8 x i16> [[TMP9]], ptr [[__VEC_ADDR_I]], align 1640// CHECK-NEXT: store i64 7, ptr [[__OFFSET_ADDR_I1]], align 841// CHECK-NEXT: store ptr [[TMP10]], ptr [[__PTR_ADDR_I2]], align 842// CHECK-NEXT: [[TMP11:%.*]] = load ptr, ptr [[__PTR_ADDR_I2]], align 843// CHECK-NEXT: [[TMP13:%.*]] = load i64, ptr [[__OFFSET_ADDR_I1]], align 844// CHECK-NEXT: [[ADD_PTR_I4:%.*]] = getelementptr inbounds i8, ptr [[TMP11]], i64 [[TMP13]]45// CHECK-NEXT: store ptr [[ADD_PTR_I4]], ptr [[__ADDR_I3]], align 846// CHECK-NEXT: [[TMP14:%.*]] = load <8 x i16>, ptr [[__VEC_ADDR_I]], align 1647// CHECK-NEXT: [[TMP15:%.*]] = load ptr, ptr [[__ADDR_I3]], align 848// CHECK-NEXT: store <8 x i16> [[TMP14]], ptr [[TMP15]], align 149// CHECK-NEXT: ret void50//51void test1(vector signed short *c, signed short *st, const signed short *ld) {52 *c = vec_xl(3ll, ld);53 vec_xst(*c, 7ll, st);54}55 56// CHECK-LABEL: @test2(57// CHECK-NEXT: entry:58// CHECK-NEXT: [[__VEC_ADDR_I:%.*]] = alloca <8 x i16>, align 1659// CHECK-NEXT: [[__OFFSET_ADDR_I1:%.*]] = alloca i64, align 860// CHECK-NEXT: [[__PTR_ADDR_I2:%.*]] = alloca ptr, align 861// CHECK-NEXT: [[__ADDR_I3:%.*]] = alloca ptr, align 862// CHECK-NEXT: [[__OFFSET_ADDR_I:%.*]] = alloca i64, align 863// CHECK-NEXT: [[__PTR_ADDR_I:%.*]] = alloca ptr, align 864// CHECK-NEXT: [[__ADDR_I:%.*]] = alloca ptr, align 865// CHECK-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 866// CHECK-NEXT: [[ST_ADDR:%.*]] = alloca ptr, align 867// CHECK-NEXT: [[LD_ADDR:%.*]] = alloca ptr, align 868// CHECK-NEXT: store ptr [[C:%.*]], ptr [[C_ADDR]], align 869// CHECK-NEXT: store ptr [[ST:%.*]], ptr [[ST_ADDR]], align 870// CHECK-NEXT: store ptr [[LD:%.*]], ptr [[LD_ADDR]], align 871// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[LD_ADDR]], align 872// CHECK-NEXT: store i64 3, ptr [[__OFFSET_ADDR_I]], align 873// CHECK-NEXT: store ptr [[TMP0]], ptr [[__PTR_ADDR_I]], align 874// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__PTR_ADDR_I]], align 875// CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr [[__OFFSET_ADDR_I]], align 876// CHECK-NEXT: [[ADD_PTR_I:%.*]] = getelementptr inbounds i8, ptr [[TMP1]], i64 [[TMP3]]77// CHECK-NEXT: store ptr [[ADD_PTR_I]], ptr [[__ADDR_I]], align 878// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[__ADDR_I]], align 879// CHECK-NEXT: [[TMP6:%.*]] = load <8 x i16>, ptr [[TMP4]], align 180// CHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[C_ADDR]], align 881// CHECK-NEXT: store <8 x i16> [[TMP6]], ptr [[TMP7]], align 1682// CHECK-NEXT: [[TMP8:%.*]] = load ptr, ptr [[C_ADDR]], align 883// CHECK-NEXT: [[TMP9:%.*]] = load <8 x i16>, ptr [[TMP8]], align 1684// CHECK-NEXT: [[TMP10:%.*]] = load ptr, ptr [[ST_ADDR]], align 885// CHECK-NEXT: store <8 x i16> [[TMP9]], ptr [[__VEC_ADDR_I]], align 1686// CHECK-NEXT: store i64 7, ptr [[__OFFSET_ADDR_I1]], align 887// CHECK-NEXT: store ptr [[TMP10]], ptr [[__PTR_ADDR_I2]], align 888// CHECK-NEXT: [[TMP11:%.*]] = load ptr, ptr [[__PTR_ADDR_I2]], align 889// CHECK-NEXT: [[TMP13:%.*]] = load i64, ptr [[__OFFSET_ADDR_I1]], align 890// CHECK-NEXT: [[ADD_PTR_I4:%.*]] = getelementptr inbounds i8, ptr [[TMP11]], i64 [[TMP13]]91// CHECK-NEXT: store ptr [[ADD_PTR_I4]], ptr [[__ADDR_I3]], align 892// CHECK-NEXT: [[TMP14:%.*]] = load <8 x i16>, ptr [[__VEC_ADDR_I]], align 1693// CHECK-NEXT: [[TMP15:%.*]] = load ptr, ptr [[__ADDR_I3]], align 894// CHECK-NEXT: store <8 x i16> [[TMP14]], ptr [[TMP15]], align 195// CHECK-NEXT: ret void96//97void test2(vector unsigned short *c, unsigned short *st,98 const unsigned short *ld) {99 *c = vec_xl(3ll, ld);100 vec_xst(*c, 7ll, st);101}102 103// CHECK-LABEL: @test3(104// CHECK-NEXT: entry:105// CHECK-NEXT: [[__VEC_ADDR_I:%.*]] = alloca <4 x i32>, align 16106// CHECK-NEXT: [[__OFFSET_ADDR_I1:%.*]] = alloca i64, align 8107// CHECK-NEXT: [[__PTR_ADDR_I2:%.*]] = alloca ptr, align 8108// CHECK-NEXT: [[__ADDR_I3:%.*]] = alloca ptr, align 8109// CHECK-NEXT: [[__OFFSET_ADDR_I:%.*]] = alloca i64, align 8110// CHECK-NEXT: [[__PTR_ADDR_I:%.*]] = alloca ptr, align 8111// CHECK-NEXT: [[__ADDR_I:%.*]] = alloca ptr, align 8112// CHECK-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8113// CHECK-NEXT: [[ST_ADDR:%.*]] = alloca ptr, align 8114// CHECK-NEXT: [[LD_ADDR:%.*]] = alloca ptr, align 8115// CHECK-NEXT: store ptr [[C:%.*]], ptr [[C_ADDR]], align 8116// CHECK-NEXT: store ptr [[ST:%.*]], ptr [[ST_ADDR]], align 8117// CHECK-NEXT: store ptr [[LD:%.*]], ptr [[LD_ADDR]], align 8118// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[LD_ADDR]], align 8119// CHECK-NEXT: store i64 3, ptr [[__OFFSET_ADDR_I]], align 8120// CHECK-NEXT: store ptr [[TMP0]], ptr [[__PTR_ADDR_I]], align 8121// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__PTR_ADDR_I]], align 8122// CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr [[__OFFSET_ADDR_I]], align 8123// CHECK-NEXT: [[ADD_PTR_I:%.*]] = getelementptr inbounds i8, ptr [[TMP1]], i64 [[TMP3]]124// CHECK-NEXT: store ptr [[ADD_PTR_I]], ptr [[__ADDR_I]], align 8125// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[__ADDR_I]], align 8126// CHECK-NEXT: [[TMP6:%.*]] = load <4 x i32>, ptr [[TMP4]], align 1127// CHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[C_ADDR]], align 8128// CHECK-NEXT: store <4 x i32> [[TMP6]], ptr [[TMP7]], align 16129// CHECK-NEXT: [[TMP8:%.*]] = load ptr, ptr [[C_ADDR]], align 8130// CHECK-NEXT: [[TMP9:%.*]] = load <4 x i32>, ptr [[TMP8]], align 16131// CHECK-NEXT: [[TMP10:%.*]] = load ptr, ptr [[ST_ADDR]], align 8132// CHECK-NEXT: store <4 x i32> [[TMP9]], ptr [[__VEC_ADDR_I]], align 16133// CHECK-NEXT: store i64 7, ptr [[__OFFSET_ADDR_I1]], align 8134// CHECK-NEXT: store ptr [[TMP10]], ptr [[__PTR_ADDR_I2]], align 8135// CHECK-NEXT: [[TMP11:%.*]] = load ptr, ptr [[__PTR_ADDR_I2]], align 8136// CHECK-NEXT: [[TMP13:%.*]] = load i64, ptr [[__OFFSET_ADDR_I1]], align 8137// CHECK-NEXT: [[ADD_PTR_I4:%.*]] = getelementptr inbounds i8, ptr [[TMP11]], i64 [[TMP13]]138// CHECK-NEXT: store ptr [[ADD_PTR_I4]], ptr [[__ADDR_I3]], align 8139// CHECK-NEXT: [[TMP14:%.*]] = load <4 x i32>, ptr [[__VEC_ADDR_I]], align 16140// CHECK-NEXT: [[TMP15:%.*]] = load ptr, ptr [[__ADDR_I3]], align 8141// CHECK-NEXT: store <4 x i32> [[TMP14]], ptr [[TMP15]], align 1142// CHECK-NEXT: ret void143//144void test3(vector signed int *c, signed int *st, const signed int *ld) {145 *c = vec_xl(3ll, ld);146 vec_xst(*c, 7ll, st);147}148 149// CHECK-LABEL: @test4(150// CHECK-NEXT: entry:151// CHECK-NEXT: [[__VEC_ADDR_I:%.*]] = alloca <4 x i32>, align 16152// CHECK-NEXT: [[__OFFSET_ADDR_I1:%.*]] = alloca i64, align 8153// CHECK-NEXT: [[__PTR_ADDR_I2:%.*]] = alloca ptr, align 8154// CHECK-NEXT: [[__ADDR_I3:%.*]] = alloca ptr, align 8155// CHECK-NEXT: [[__OFFSET_ADDR_I:%.*]] = alloca i64, align 8156// CHECK-NEXT: [[__PTR_ADDR_I:%.*]] = alloca ptr, align 8157// CHECK-NEXT: [[__ADDR_I:%.*]] = alloca ptr, align 8158// CHECK-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8159// CHECK-NEXT: [[ST_ADDR:%.*]] = alloca ptr, align 8160// CHECK-NEXT: [[LD_ADDR:%.*]] = alloca ptr, align 8161// CHECK-NEXT: store ptr [[C:%.*]], ptr [[C_ADDR]], align 8162// CHECK-NEXT: store ptr [[ST:%.*]], ptr [[ST_ADDR]], align 8163// CHECK-NEXT: store ptr [[LD:%.*]], ptr [[LD_ADDR]], align 8164// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[LD_ADDR]], align 8165// CHECK-NEXT: store i64 3, ptr [[__OFFSET_ADDR_I]], align 8166// CHECK-NEXT: store ptr [[TMP0]], ptr [[__PTR_ADDR_I]], align 8167// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__PTR_ADDR_I]], align 8168// CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr [[__OFFSET_ADDR_I]], align 8169// CHECK-NEXT: [[ADD_PTR_I:%.*]] = getelementptr inbounds i8, ptr [[TMP1]], i64 [[TMP3]]170// CHECK-NEXT: store ptr [[ADD_PTR_I]], ptr [[__ADDR_I]], align 8171// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[__ADDR_I]], align 8172// CHECK-NEXT: [[TMP6:%.*]] = load <4 x i32>, ptr [[TMP4]], align 1173// CHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[C_ADDR]], align 8174// CHECK-NEXT: store <4 x i32> [[TMP6]], ptr [[TMP7]], align 16175// CHECK-NEXT: [[TMP8:%.*]] = load ptr, ptr [[C_ADDR]], align 8176// CHECK-NEXT: [[TMP9:%.*]] = load <4 x i32>, ptr [[TMP8]], align 16177// CHECK-NEXT: [[TMP10:%.*]] = load ptr, ptr [[ST_ADDR]], align 8178// CHECK-NEXT: store <4 x i32> [[TMP9]], ptr [[__VEC_ADDR_I]], align 16179// CHECK-NEXT: store i64 7, ptr [[__OFFSET_ADDR_I1]], align 8180// CHECK-NEXT: store ptr [[TMP10]], ptr [[__PTR_ADDR_I2]], align 8181// CHECK-NEXT: [[TMP11:%.*]] = load ptr, ptr [[__PTR_ADDR_I2]], align 8182// CHECK-NEXT: [[TMP13:%.*]] = load i64, ptr [[__OFFSET_ADDR_I1]], align 8183// CHECK-NEXT: [[ADD_PTR_I4:%.*]] = getelementptr inbounds i8, ptr [[TMP11]], i64 [[TMP13]]184// CHECK-NEXT: store ptr [[ADD_PTR_I4]], ptr [[__ADDR_I3]], align 8185// CHECK-NEXT: [[TMP14:%.*]] = load <4 x i32>, ptr [[__VEC_ADDR_I]], align 16186// CHECK-NEXT: [[TMP15:%.*]] = load ptr, ptr [[__ADDR_I3]], align 8187// CHECK-NEXT: store <4 x i32> [[TMP14]], ptr [[TMP15]], align 1188// CHECK-NEXT: ret void189//190void test4(vector unsigned int *c, unsigned int *st, const unsigned int *ld) {191 *c = vec_xl(3ll, ld);192 vec_xst(*c, 7ll, st);193}194 195// CHECK-LABEL: @test5(196// CHECK-NEXT: entry:197// CHECK-NEXT: [[__VEC_ADDR_I:%.*]] = alloca <2 x i64>, align 16198// CHECK-NEXT: [[__OFFSET_ADDR_I1:%.*]] = alloca i64, align 8199// CHECK-NEXT: [[__PTR_ADDR_I2:%.*]] = alloca ptr, align 8200// CHECK-NEXT: [[__ADDR_I3:%.*]] = alloca ptr, align 8201// CHECK-NEXT: [[__OFFSET_ADDR_I:%.*]] = alloca i64, align 8202// CHECK-NEXT: [[__PTR_ADDR_I:%.*]] = alloca ptr, align 8203// CHECK-NEXT: [[__ADDR_I:%.*]] = alloca ptr, align 8204// CHECK-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8205// CHECK-NEXT: [[ST_ADDR:%.*]] = alloca ptr, align 8206// CHECK-NEXT: [[LD_ADDR:%.*]] = alloca ptr, align 8207// CHECK-NEXT: store ptr [[C:%.*]], ptr [[C_ADDR]], align 8208// CHECK-NEXT: store ptr [[ST:%.*]], ptr [[ST_ADDR]], align 8209// CHECK-NEXT: store ptr [[LD:%.*]], ptr [[LD_ADDR]], align 8210// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[LD_ADDR]], align 8211// CHECK-NEXT: store i64 3, ptr [[__OFFSET_ADDR_I]], align 8212// CHECK-NEXT: store ptr [[TMP0]], ptr [[__PTR_ADDR_I]], align 8213// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__PTR_ADDR_I]], align 8214// CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr [[__OFFSET_ADDR_I]], align 8215// CHECK-NEXT: [[ADD_PTR_I:%.*]] = getelementptr inbounds i8, ptr [[TMP1]], i64 [[TMP3]]216// CHECK-NEXT: store ptr [[ADD_PTR_I]], ptr [[__ADDR_I]], align 8217// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[__ADDR_I]], align 8218// CHECK-NEXT: [[TMP6:%.*]] = load <2 x i64>, ptr [[TMP4]], align 1219// CHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[C_ADDR]], align 8220// CHECK-NEXT: store <2 x i64> [[TMP6]], ptr [[TMP7]], align 16221// CHECK-NEXT: [[TMP8:%.*]] = load ptr, ptr [[C_ADDR]], align 8222// CHECK-NEXT: [[TMP9:%.*]] = load <2 x i64>, ptr [[TMP8]], align 16223// CHECK-NEXT: [[TMP10:%.*]] = load ptr, ptr [[ST_ADDR]], align 8224// CHECK-NEXT: store <2 x i64> [[TMP9]], ptr [[__VEC_ADDR_I]], align 16225// CHECK-NEXT: store i64 7, ptr [[__OFFSET_ADDR_I1]], align 8226// CHECK-NEXT: store ptr [[TMP10]], ptr [[__PTR_ADDR_I2]], align 8227// CHECK-NEXT: [[TMP11:%.*]] = load ptr, ptr [[__PTR_ADDR_I2]], align 8228// CHECK-NEXT: [[TMP13:%.*]] = load i64, ptr [[__OFFSET_ADDR_I1]], align 8229// CHECK-NEXT: [[ADD_PTR_I4:%.*]] = getelementptr inbounds i8, ptr [[TMP11]], i64 [[TMP13]]230// CHECK-NEXT: store ptr [[ADD_PTR_I4]], ptr [[__ADDR_I3]], align 8231// CHECK-NEXT: [[TMP14:%.*]] = load <2 x i64>, ptr [[__VEC_ADDR_I]], align 16232// CHECK-NEXT: [[TMP15:%.*]] = load ptr, ptr [[__ADDR_I3]], align 8233// CHECK-NEXT: store <2 x i64> [[TMP14]], ptr [[TMP15]], align 1234// CHECK-NEXT: ret void235//236void test5(vector signed long long *c, signed long long *st,237 const signed long long *ld) {238 *c = vec_xl(3ll, ld);239 vec_xst(*c, 7ll, st);240}241 242// CHECK-LABEL: @test6(243// CHECK-NEXT: entry:244// CHECK-NEXT: [[__VEC_ADDR_I:%.*]] = alloca <2 x i64>, align 16245// CHECK-NEXT: [[__OFFSET_ADDR_I1:%.*]] = alloca i64, align 8246// CHECK-NEXT: [[__PTR_ADDR_I2:%.*]] = alloca ptr, align 8247// CHECK-NEXT: [[__ADDR_I3:%.*]] = alloca ptr, align 8248// CHECK-NEXT: [[__OFFSET_ADDR_I:%.*]] = alloca i64, align 8249// CHECK-NEXT: [[__PTR_ADDR_I:%.*]] = alloca ptr, align 8250// CHECK-NEXT: [[__ADDR_I:%.*]] = alloca ptr, align 8251// CHECK-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8252// CHECK-NEXT: [[ST_ADDR:%.*]] = alloca ptr, align 8253// CHECK-NEXT: [[LD_ADDR:%.*]] = alloca ptr, align 8254// CHECK-NEXT: store ptr [[C:%.*]], ptr [[C_ADDR]], align 8255// CHECK-NEXT: store ptr [[ST:%.*]], ptr [[ST_ADDR]], align 8256// CHECK-NEXT: store ptr [[LD:%.*]], ptr [[LD_ADDR]], align 8257// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[LD_ADDR]], align 8258// CHECK-NEXT: store i64 3, ptr [[__OFFSET_ADDR_I]], align 8259// CHECK-NEXT: store ptr [[TMP0]], ptr [[__PTR_ADDR_I]], align 8260// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__PTR_ADDR_I]], align 8261// CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr [[__OFFSET_ADDR_I]], align 8262// CHECK-NEXT: [[ADD_PTR_I:%.*]] = getelementptr inbounds i8, ptr [[TMP1]], i64 [[TMP3]]263// CHECK-NEXT: store ptr [[ADD_PTR_I]], ptr [[__ADDR_I]], align 8264// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[__ADDR_I]], align 8265// CHECK-NEXT: [[TMP6:%.*]] = load <2 x i64>, ptr [[TMP4]], align 1266// CHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[C_ADDR]], align 8267// CHECK-NEXT: store <2 x i64> [[TMP6]], ptr [[TMP7]], align 16268// CHECK-NEXT: [[TMP8:%.*]] = load ptr, ptr [[C_ADDR]], align 8269// CHECK-NEXT: [[TMP9:%.*]] = load <2 x i64>, ptr [[TMP8]], align 16270// CHECK-NEXT: [[TMP10:%.*]] = load ptr, ptr [[ST_ADDR]], align 8271// CHECK-NEXT: store <2 x i64> [[TMP9]], ptr [[__VEC_ADDR_I]], align 16272// CHECK-NEXT: store i64 7, ptr [[__OFFSET_ADDR_I1]], align 8273// CHECK-NEXT: store ptr [[TMP10]], ptr [[__PTR_ADDR_I2]], align 8274// CHECK-NEXT: [[TMP11:%.*]] = load ptr, ptr [[__PTR_ADDR_I2]], align 8275// CHECK-NEXT: [[TMP13:%.*]] = load i64, ptr [[__OFFSET_ADDR_I1]], align 8276// CHECK-NEXT: [[ADD_PTR_I4:%.*]] = getelementptr inbounds i8, ptr [[TMP11]], i64 [[TMP13]]277// CHECK-NEXT: store ptr [[ADD_PTR_I4]], ptr [[__ADDR_I3]], align 8278// CHECK-NEXT: [[TMP14:%.*]] = load <2 x i64>, ptr [[__VEC_ADDR_I]], align 16279// CHECK-NEXT: [[TMP15:%.*]] = load ptr, ptr [[__ADDR_I3]], align 8280// CHECK-NEXT: store <2 x i64> [[TMP14]], ptr [[TMP15]], align 1281// CHECK-NEXT: ret void282//283void test6(vector unsigned long long *c, unsigned long long *st,284 const unsigned long long *ld) {285 *c = vec_xl(3ll, ld);286 vec_xst(*c, 7ll, st);287}288 289// CHECK-LABEL: @test7(290// CHECK-NEXT: entry:291// CHECK-NEXT: [[__VEC_ADDR_I:%.*]] = alloca <4 x float>, align 16292// CHECK-NEXT: [[__OFFSET_ADDR_I1:%.*]] = alloca i64, align 8293// CHECK-NEXT: [[__PTR_ADDR_I2:%.*]] = alloca ptr, align 8294// CHECK-NEXT: [[__ADDR_I3:%.*]] = alloca ptr, align 8295// CHECK-NEXT: [[__OFFSET_ADDR_I:%.*]] = alloca i64, align 8296// CHECK-NEXT: [[__PTR_ADDR_I:%.*]] = alloca ptr, align 8297// CHECK-NEXT: [[__ADDR_I:%.*]] = alloca ptr, align 8298// CHECK-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8299// CHECK-NEXT: [[ST_ADDR:%.*]] = alloca ptr, align 8300// CHECK-NEXT: [[LD_ADDR:%.*]] = alloca ptr, align 8301// CHECK-NEXT: store ptr [[C:%.*]], ptr [[C_ADDR]], align 8302// CHECK-NEXT: store ptr [[ST:%.*]], ptr [[ST_ADDR]], align 8303// CHECK-NEXT: store ptr [[LD:%.*]], ptr [[LD_ADDR]], align 8304// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[LD_ADDR]], align 8305// CHECK-NEXT: store i64 3, ptr [[__OFFSET_ADDR_I]], align 8306// CHECK-NEXT: store ptr [[TMP0]], ptr [[__PTR_ADDR_I]], align 8307// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__PTR_ADDR_I]], align 8308// CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr [[__OFFSET_ADDR_I]], align 8309// CHECK-NEXT: [[ADD_PTR_I:%.*]] = getelementptr inbounds i8, ptr [[TMP1]], i64 [[TMP3]]310// CHECK-NEXT: store ptr [[ADD_PTR_I]], ptr [[__ADDR_I]], align 8311// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[__ADDR_I]], align 8312// CHECK-NEXT: [[TMP6:%.*]] = load <4 x float>, ptr [[TMP4]], align 1313// CHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[C_ADDR]], align 8314// CHECK-NEXT: store <4 x float> [[TMP6]], ptr [[TMP7]], align 16315// CHECK-NEXT: [[TMP8:%.*]] = load ptr, ptr [[C_ADDR]], align 8316// CHECK-NEXT: [[TMP9:%.*]] = load <4 x float>, ptr [[TMP8]], align 16317// CHECK-NEXT: [[TMP10:%.*]] = load ptr, ptr [[ST_ADDR]], align 8318// CHECK-NEXT: store <4 x float> [[TMP9]], ptr [[__VEC_ADDR_I]], align 16319// CHECK-NEXT: store i64 7, ptr [[__OFFSET_ADDR_I1]], align 8320// CHECK-NEXT: store ptr [[TMP10]], ptr [[__PTR_ADDR_I2]], align 8321// CHECK-NEXT: [[TMP11:%.*]] = load ptr, ptr [[__PTR_ADDR_I2]], align 8322// CHECK-NEXT: [[TMP13:%.*]] = load i64, ptr [[__OFFSET_ADDR_I1]], align 8323// CHECK-NEXT: [[ADD_PTR_I4:%.*]] = getelementptr inbounds i8, ptr [[TMP11]], i64 [[TMP13]]324// CHECK-NEXT: store ptr [[ADD_PTR_I4]], ptr [[__ADDR_I3]], align 8325// CHECK-NEXT: [[TMP14:%.*]] = load <4 x float>, ptr [[__VEC_ADDR_I]], align 16326// CHECK-NEXT: [[TMP15:%.*]] = load ptr, ptr [[__ADDR_I3]], align 8327// CHECK-NEXT: store <4 x float> [[TMP14]], ptr [[TMP15]], align 1328// CHECK-NEXT: ret void329//330void test7(vector float *c, float *st, const float *ld) {331 *c = vec_xl(3ll, ld);332 vec_xst(*c, 7ll, st);333}334 335// CHECK-LABEL: @test8(336// CHECK-NEXT: entry:337// CHECK-NEXT: [[__VEC_ADDR_I:%.*]] = alloca <2 x double>, align 16338// CHECK-NEXT: [[__OFFSET_ADDR_I1:%.*]] = alloca i64, align 8339// CHECK-NEXT: [[__PTR_ADDR_I2:%.*]] = alloca ptr, align 8340// CHECK-NEXT: [[__ADDR_I3:%.*]] = alloca ptr, align 8341// CHECK-NEXT: [[__OFFSET_ADDR_I:%.*]] = alloca i64, align 8342// CHECK-NEXT: [[__PTR_ADDR_I:%.*]] = alloca ptr, align 8343// CHECK-NEXT: [[__ADDR_I:%.*]] = alloca ptr, align 8344// CHECK-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8345// CHECK-NEXT: [[ST_ADDR:%.*]] = alloca ptr, align 8346// CHECK-NEXT: [[LD_ADDR:%.*]] = alloca ptr, align 8347// CHECK-NEXT: store ptr [[C:%.*]], ptr [[C_ADDR]], align 8348// CHECK-NEXT: store ptr [[ST:%.*]], ptr [[ST_ADDR]], align 8349// CHECK-NEXT: store ptr [[LD:%.*]], ptr [[LD_ADDR]], align 8350// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[LD_ADDR]], align 8351// CHECK-NEXT: store i64 3, ptr [[__OFFSET_ADDR_I]], align 8352// CHECK-NEXT: store ptr [[TMP0]], ptr [[__PTR_ADDR_I]], align 8353// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__PTR_ADDR_I]], align 8354// CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr [[__OFFSET_ADDR_I]], align 8355// CHECK-NEXT: [[ADD_PTR_I:%.*]] = getelementptr inbounds i8, ptr [[TMP1]], i64 [[TMP3]]356// CHECK-NEXT: store ptr [[ADD_PTR_I]], ptr [[__ADDR_I]], align 8357// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[__ADDR_I]], align 8358// CHECK-NEXT: [[TMP6:%.*]] = load <2 x double>, ptr [[TMP4]], align 1359// CHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[C_ADDR]], align 8360// CHECK-NEXT: store <2 x double> [[TMP6]], ptr [[TMP7]], align 16361// CHECK-NEXT: [[TMP8:%.*]] = load ptr, ptr [[C_ADDR]], align 8362// CHECK-NEXT: [[TMP9:%.*]] = load <2 x double>, ptr [[TMP8]], align 16363// CHECK-NEXT: [[TMP10:%.*]] = load ptr, ptr [[ST_ADDR]], align 8364// CHECK-NEXT: store <2 x double> [[TMP9]], ptr [[__VEC_ADDR_I]], align 16365// CHECK-NEXT: store i64 7, ptr [[__OFFSET_ADDR_I1]], align 8366// CHECK-NEXT: store ptr [[TMP10]], ptr [[__PTR_ADDR_I2]], align 8367// CHECK-NEXT: [[TMP11:%.*]] = load ptr, ptr [[__PTR_ADDR_I2]], align 8368// CHECK-NEXT: [[TMP13:%.*]] = load i64, ptr [[__OFFSET_ADDR_I1]], align 8369// CHECK-NEXT: [[ADD_PTR_I4:%.*]] = getelementptr inbounds i8, ptr [[TMP11]], i64 [[TMP13]]370// CHECK-NEXT: store ptr [[ADD_PTR_I4]], ptr [[__ADDR_I3]], align 8371// CHECK-NEXT: [[TMP14:%.*]] = load <2 x double>, ptr [[__VEC_ADDR_I]], align 16372// CHECK-NEXT: [[TMP15:%.*]] = load ptr, ptr [[__ADDR_I3]], align 8373// CHECK-NEXT: store <2 x double> [[TMP14]], ptr [[TMP15]], align 1374// CHECK-NEXT: ret void375//376void test8(vector double *c, double *st, const double *ld) {377 *c = vec_xl(3ll, ld);378 vec_xst(*c, 7ll, st);379}380 381#ifdef __POWER8_VECTOR__382// CHECK-P8-LABEL: @test9(383// CHECK-P8-NEXT: entry:384// CHECK-P8-NEXT: [[__VEC_ADDR_I:%.*]] = alloca <1 x i128>, align 16385// CHECK-P8-NEXT: [[__OFFSET_ADDR_I1:%.*]] = alloca i64, align 8386// CHECK-P8-NEXT: [[__PTR_ADDR_I2:%.*]] = alloca ptr, align 8387// CHECK-P8-NEXT: [[__ADDR_I3:%.*]] = alloca ptr, align 8388// CHECK-P8-NEXT: [[__OFFSET_ADDR_I:%.*]] = alloca i64, align 8389// CHECK-P8-NEXT: [[__PTR_ADDR_I:%.*]] = alloca ptr, align 8390// CHECK-P8-NEXT: [[__ADDR_I:%.*]] = alloca ptr, align 8391// CHECK-P8-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8392// CHECK-P8-NEXT: [[ST_ADDR:%.*]] = alloca ptr, align 8393// CHECK-P8-NEXT: [[LD_ADDR:%.*]] = alloca ptr, align 8394// CHECK-P8-NEXT: store ptr [[C:%.*]], ptr [[C_ADDR]], align 8395// CHECK-P8-NEXT: store ptr [[ST:%.*]], ptr [[ST_ADDR]], align 8396// CHECK-P8-NEXT: store ptr [[LD:%.*]], ptr [[LD_ADDR]], align 8397// CHECK-P8-NEXT: [[TMP0:%.*]] = load ptr, ptr [[LD_ADDR]], align 8398// CHECK-P8-NEXT: store i64 3, ptr [[__OFFSET_ADDR_I]], align 8399// CHECK-P8-NEXT: store ptr [[TMP0]], ptr [[__PTR_ADDR_I]], align 8400// CHECK-P8-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__PTR_ADDR_I]], align 8401// CHECK-P8-NEXT: [[TMP3:%.*]] = load i64, ptr [[__OFFSET_ADDR_I]], align 8402// CHECK-P8-NEXT: [[ADD_PTR_I:%.*]] = getelementptr inbounds i8, ptr [[TMP1]], i64 [[TMP3]]403// CHECK-P8-NEXT: store ptr [[ADD_PTR_I]], ptr [[__ADDR_I]], align 8404// CHECK-P8-NEXT: [[TMP4:%.*]] = load ptr, ptr [[__ADDR_I]], align 8405// CHECK-P8-NEXT: [[TMP6:%.*]] = load <1 x i128>, ptr [[TMP4]], align 1406// CHECK-P8-NEXT: [[TMP7:%.*]] = load ptr, ptr [[C_ADDR]], align 8407// CHECK-P8-NEXT: store <1 x i128> [[TMP6]], ptr [[TMP7]], align 16408// CHECK-P8-NEXT: [[TMP8:%.*]] = load ptr, ptr [[C_ADDR]], align 8409// CHECK-P8-NEXT: [[TMP9:%.*]] = load <1 x i128>, ptr [[TMP8]], align 16410// CHECK-P8-NEXT: [[TMP10:%.*]] = load ptr, ptr [[ST_ADDR]], align 8411// CHECK-P8-NEXT: store <1 x i128> [[TMP9]], ptr [[__VEC_ADDR_I]], align 16412// CHECK-P8-NEXT: store i64 7, ptr [[__OFFSET_ADDR_I1]], align 8413// CHECK-P8-NEXT: store ptr [[TMP10]], ptr [[__PTR_ADDR_I2]], align 8414// CHECK-P8-NEXT: [[TMP11:%.*]] = load ptr, ptr [[__PTR_ADDR_I2]], align 8415// CHECK-P8-NEXT: [[TMP13:%.*]] = load i64, ptr [[__OFFSET_ADDR_I1]], align 8416// CHECK-P8-NEXT: [[ADD_PTR_I4:%.*]] = getelementptr inbounds i8, ptr [[TMP11]], i64 [[TMP13]]417// CHECK-P8-NEXT: store ptr [[ADD_PTR_I4]], ptr [[__ADDR_I3]], align 8418// CHECK-P8-NEXT: [[TMP14:%.*]] = load <1 x i128>, ptr [[__VEC_ADDR_I]], align 16419// CHECK-P8-NEXT: [[TMP15:%.*]] = load ptr, ptr [[__ADDR_I3]], align 8420// CHECK-P8-NEXT: store <1 x i128> [[TMP14]], ptr [[TMP15]], align 1421// CHECK-P8-NEXT: ret void422//423void test9(vector signed __int128 *c, signed __int128 *st,424 const signed __int128 *ld) {425 *c = vec_xl(3ll, ld);426 vec_xst(*c, 7ll, st);427}428 429// CHECK-P8-LABEL: @test10(430// CHECK-P8-NEXT: entry:431// CHECK-P8-NEXT: [[__VEC_ADDR_I:%.*]] = alloca <1 x i128>, align 16432// CHECK-P8-NEXT: [[__OFFSET_ADDR_I1:%.*]] = alloca i64, align 8433// CHECK-P8-NEXT: [[__PTR_ADDR_I2:%.*]] = alloca ptr, align 8434// CHECK-P8-NEXT: [[__ADDR_I3:%.*]] = alloca ptr, align 8435// CHECK-P8-NEXT: [[__OFFSET_ADDR_I:%.*]] = alloca i64, align 8436// CHECK-P8-NEXT: [[__PTR_ADDR_I:%.*]] = alloca ptr, align 8437// CHECK-P8-NEXT: [[__ADDR_I:%.*]] = alloca ptr, align 8438// CHECK-P8-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8439// CHECK-P8-NEXT: [[ST_ADDR:%.*]] = alloca ptr, align 8440// CHECK-P8-NEXT: [[LD_ADDR:%.*]] = alloca ptr, align 8441// CHECK-P8-NEXT: store ptr [[C:%.*]], ptr [[C_ADDR]], align 8442// CHECK-P8-NEXT: store ptr [[ST:%.*]], ptr [[ST_ADDR]], align 8443// CHECK-P8-NEXT: store ptr [[LD:%.*]], ptr [[LD_ADDR]], align 8444// CHECK-P8-NEXT: [[TMP0:%.*]] = load ptr, ptr [[LD_ADDR]], align 8445// CHECK-P8-NEXT: store i64 3, ptr [[__OFFSET_ADDR_I]], align 8446// CHECK-P8-NEXT: store ptr [[TMP0]], ptr [[__PTR_ADDR_I]], align 8447// CHECK-P8-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__PTR_ADDR_I]], align 8448// CHECK-P8-NEXT: [[TMP3:%.*]] = load i64, ptr [[__OFFSET_ADDR_I]], align 8449// CHECK-P8-NEXT: [[ADD_PTR_I:%.*]] = getelementptr inbounds i8, ptr [[TMP1]], i64 [[TMP3]]450// CHECK-P8-NEXT: store ptr [[ADD_PTR_I]], ptr [[__ADDR_I]], align 8451// CHECK-P8-NEXT: [[TMP4:%.*]] = load ptr, ptr [[__ADDR_I]], align 8452// CHECK-P8-NEXT: [[TMP6:%.*]] = load <1 x i128>, ptr [[TMP4]], align 1453// CHECK-P8-NEXT: [[TMP7:%.*]] = load ptr, ptr [[C_ADDR]], align 8454// CHECK-P8-NEXT: store <1 x i128> [[TMP6]], ptr [[TMP7]], align 16455// CHECK-P8-NEXT: [[TMP8:%.*]] = load ptr, ptr [[C_ADDR]], align 8456// CHECK-P8-NEXT: [[TMP9:%.*]] = load <1 x i128>, ptr [[TMP8]], align 16457// CHECK-P8-NEXT: [[TMP10:%.*]] = load ptr, ptr [[ST_ADDR]], align 8458// CHECK-P8-NEXT: store <1 x i128> [[TMP9]], ptr [[__VEC_ADDR_I]], align 16459// CHECK-P8-NEXT: store i64 7, ptr [[__OFFSET_ADDR_I1]], align 8460// CHECK-P8-NEXT: store ptr [[TMP10]], ptr [[__PTR_ADDR_I2]], align 8461// CHECK-P8-NEXT: [[TMP11:%.*]] = load ptr, ptr [[__PTR_ADDR_I2]], align 8462// CHECK-P8-NEXT: [[TMP13:%.*]] = load i64, ptr [[__OFFSET_ADDR_I1]], align 8463// CHECK-P8-NEXT: [[ADD_PTR_I4:%.*]] = getelementptr inbounds i8, ptr [[TMP11]], i64 [[TMP13]]464// CHECK-P8-NEXT: store ptr [[ADD_PTR_I4]], ptr [[__ADDR_I3]], align 8465// CHECK-P8-NEXT: [[TMP14:%.*]] = load <1 x i128>, ptr [[__VEC_ADDR_I]], align 16466// CHECK-P8-NEXT: [[TMP15:%.*]] = load ptr, ptr [[__ADDR_I3]], align 8467// CHECK-P8-NEXT: store <1 x i128> [[TMP14]], ptr [[TMP15]], align 1468// CHECK-P8-NEXT: ret void469//470void test10(vector unsigned __int128 *c, unsigned __int128 *st,471 const unsigned __int128 *ld) {472 *c = vec_xl(3ll, ld);473 vec_xst(*c, 7ll, st);474}475#endif476