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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py2// REQUIRES: powerpc-registered-target3// RUN: %clang_cc1 -triple powerpc64-unknown-linux-gnu \4// RUN: -emit-llvm %s -o - -target-cpu pwr8 | FileCheck %s5// RUN: %clang_cc1 -triple powerpc64le-unknown-linux-gnu \6// RUN: -emit-llvm %s -o - -target-cpu pwr8 | FileCheck %s7 8 9// CHECK-LABEL: @test_builtin_ppc_compare_and_swap(10// CHECK-NEXT: entry:11// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 412// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i32, align 413// CHECK-NEXT: [[C_ADDR:%.*]] = alloca i32, align 414// CHECK-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 415// CHECK-NEXT: store i32 [[B:%.*]], ptr [[B_ADDR]], align 416// CHECK-NEXT: store i32 [[C:%.*]], ptr [[C_ADDR]], align 417// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[B_ADDR]], align 418// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[C_ADDR]], align 419// CHECK-NEXT: [[TMP2:%.*]] = cmpxchg weak volatile ptr [[A_ADDR]], i32 [[TMP0]], i32 [[TMP1]] monotonic monotonic, align 420// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { i32, i1 } [[TMP2]], 021// CHECK-NEXT: [[TMP4:%.*]] = extractvalue { i32, i1 } [[TMP2]], 122// CHECK-NEXT: store i32 [[TMP3]], ptr [[B_ADDR]], align 423// CHECK-NEXT: [[TMP5:%.*]] = zext i1 [[TMP4]] to i3224// CHECK-NEXT: ret i32 [[TMP5]]25//26int test_builtin_ppc_compare_and_swap(int a, int b, int c) {27 return __compare_and_swap(&a, &b, c);28}29 30 31// CHECK-LABEL: @test_builtin_ppc_compare_and_swaplp(32// CHECK-NEXT: entry:33// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i64, align 834// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i64, align 835// CHECK-NEXT: [[C_ADDR:%.*]] = alloca i64, align 836// CHECK-NEXT: store i64 [[A:%.*]], ptr [[A_ADDR]], align 837// CHECK-NEXT: store i64 [[B:%.*]], ptr [[B_ADDR]], align 838// CHECK-NEXT: store i64 [[C:%.*]], ptr [[C_ADDR]], align 839// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[B_ADDR]], align 840// CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr [[C_ADDR]], align 841// CHECK-NEXT: [[TMP2:%.*]] = cmpxchg weak volatile ptr [[A_ADDR]], i64 [[TMP0]], i64 [[TMP1]] monotonic monotonic, align 842// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { i64, i1 } [[TMP2]], 043// CHECK-NEXT: [[TMP4:%.*]] = extractvalue { i64, i1 } [[TMP2]], 144// CHECK-NEXT: store i64 [[TMP3]], ptr [[B_ADDR]], align 845// CHECK-NEXT: [[TMP5:%.*]] = zext i1 [[TMP4]] to i3246// CHECK-NEXT: ret i32 [[TMP5]]47//48int test_builtin_ppc_compare_and_swaplp(long a, long b, long c) {49 return __compare_and_swaplp(&a, &b, c);50}51 52