113 lines · c
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py2// REQUIRES: powerpc-registered-target3// RUN: %clang_cc1 -triple powerpc64-unknown-linux-gnu \4// RUN: -emit-llvm %s -o - -target-cpu pwr8 | FileCheck %s5// RUN: %clang_cc1 -triple powerpc64le-unknown-linux-gnu \6// RUN: -emit-llvm %s -o - -target-cpu pwr8 | FileCheck %s7 8// CHECK-LABEL: @test_builtin_ppc_fetch_and_add(9// CHECK-NEXT: entry:10// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 411// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i32, align 412// CHECK-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 413// CHECK-NEXT: store i32 [[B:%.*]], ptr [[B_ADDR]], align 414// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[B_ADDR]], align 415// CHECK-NEXT: [[TMP1:%.*]] = atomicrmw add ptr [[A_ADDR]], i32 [[TMP0]] monotonic, align 416// CHECK-NEXT: ret void17//18void test_builtin_ppc_fetch_and_add(int a, int b) {19 __fetch_and_add(&a, b);20}21 22// CHECK-LABEL: @test_builtin_ppc_fetch_and_addlp(23// CHECK-NEXT: entry:24// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i64, align 825// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i64, align 826// CHECK-NEXT: store i64 [[A:%.*]], ptr [[A_ADDR]], align 827// CHECK-NEXT: store i64 [[B:%.*]], ptr [[B_ADDR]], align 828// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[B_ADDR]], align 829// CHECK-NEXT: [[TMP1:%.*]] = atomicrmw add ptr [[A_ADDR]], i64 [[TMP0]] monotonic, align 830// CHECK-NEXT: ret void31//32void test_builtin_ppc_fetch_and_addlp(long a, long b) {33 __fetch_and_addlp(&a, b);34}35// CHECK-LABEL: @test_builtin_ppc_fetch_and_and(36// CHECK-NEXT: entry:37// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 438// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i32, align 439// CHECK-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 440// CHECK-NEXT: store i32 [[B:%.*]], ptr [[B_ADDR]], align 441// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[B_ADDR]], align 442// CHECK-NEXT: [[TMP1:%.*]] = atomicrmw and ptr [[A_ADDR]], i32 [[TMP0]] monotonic, align 443// CHECK-NEXT: ret void44//45void test_builtin_ppc_fetch_and_and(unsigned int a, unsigned int b) {46 __fetch_and_and(&a, b);47}48// CHECK-LABEL: @test_builtin_ppc_fetch_and_andlp(49// CHECK-NEXT: entry:50// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i64, align 851// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i64, align 852// CHECK-NEXT: store i64 [[A:%.*]], ptr [[A_ADDR]], align 853// CHECK-NEXT: store i64 [[B:%.*]], ptr [[B_ADDR]], align 854// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[B_ADDR]], align 855// CHECK-NEXT: [[TMP1:%.*]] = atomicrmw and ptr [[A_ADDR]], i64 [[TMP0]] monotonic, align 856// CHECK-NEXT: ret void57//58void test_builtin_ppc_fetch_and_andlp(unsigned long a, unsigned long b) {59 __fetch_and_andlp(&a, b);60}61// CHECK-LABEL: @test_builtin_ppc_fetch_and_or(62// CHECK-NEXT: entry:63// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 464// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i32, align 465// CHECK-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 466// CHECK-NEXT: store i32 [[B:%.*]], ptr [[B_ADDR]], align 467// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[B_ADDR]], align 468// CHECK-NEXT: [[TMP1:%.*]] = atomicrmw or ptr [[A_ADDR]], i32 [[TMP0]] monotonic, align 469// CHECK-NEXT: ret void70//71void test_builtin_ppc_fetch_and_or(unsigned int a, unsigned int b) {72 __fetch_and_or(&a, b);73}74// CHECK-LABEL: @test_builtin_ppc_fetch_and_orlp(75// CHECK-NEXT: entry:76// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i64, align 877// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i64, align 878// CHECK-NEXT: store i64 [[A:%.*]], ptr [[A_ADDR]], align 879// CHECK-NEXT: store i64 [[B:%.*]], ptr [[B_ADDR]], align 880// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[B_ADDR]], align 881// CHECK-NEXT: [[TMP1:%.*]] = atomicrmw or ptr [[A_ADDR]], i64 [[TMP0]] monotonic, align 882// CHECK-NEXT: ret void83//84void test_builtin_ppc_fetch_and_orlp(unsigned long a, unsigned long b) {85 __fetch_and_orlp(&a, b);86}87// CHECK-LABEL: @test_builtin_ppc_fetch_and_swap(88// CHECK-NEXT: entry:89// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 490// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i32, align 491// CHECK-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 492// CHECK-NEXT: store i32 [[B:%.*]], ptr [[B_ADDR]], align 493// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[B_ADDR]], align 494// CHECK-NEXT: [[TMP1:%.*]] = atomicrmw xchg ptr [[A_ADDR]], i32 [[TMP0]] monotonic, align 495// CHECK-NEXT: ret void96//97void test_builtin_ppc_fetch_and_swap(unsigned int a, unsigned int b) {98 __fetch_and_swap(&a, b);99}100// CHECK-LABEL: @test_builtin_ppc_fetch_and_swaplp(101// CHECK-NEXT: entry:102// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8103// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8104// CHECK-NEXT: store i64 [[A:%.*]], ptr [[A_ADDR]], align 8105// CHECK-NEXT: store i64 [[B:%.*]], ptr [[B_ADDR]], align 8106// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[B_ADDR]], align 8107// CHECK-NEXT: [[TMP1:%.*]] = atomicrmw xchg ptr [[A_ADDR]], i64 [[TMP0]] monotonic, align 8108// CHECK-NEXT: ret void109//110void test_builtin_ppc_fetch_and_swaplp(unsigned long a, unsigned long b) {111 __fetch_and_swaplp(&a, b);112}113