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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 22// REQUIRES: riscv-registered-target3// RUN: %clang_cc1 -triple riscv64 -target-feature +v \4// RUN: -target-feature +xandesvbfhcvt -disable-O0-optnone \5// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \6// RUN: FileCheck --check-prefix=CHECK-RV64 %s7 8#include <andes_vector.h>9 10// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_nds_vfwcvt_s_bf16_f32mf211// CHECK-RV64-SAME: (<vscale x 1 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {12// CHECK-RV64-NEXT: entry:13// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> [[VS2]], i64 [[VL]])14// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]15//16vfloat32mf2_t test_nds_vfwcvt_s_bf16_f32mf2(vbfloat16mf4_t vs2, size_t vl) {17 return __riscv_nds_vfwcvt_s_bf16_f32mf2(vs2, vl);18}19 20// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_nds_vfwcvt_s_bf16_f32m121// CHECK-RV64-SAME: (<vscale x 2 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {22// CHECK-RV64-NEXT: entry:23// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> [[VS2]], i64 [[VL]])24// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]25//26vfloat32m1_t test_nds_vfwcvt_s_bf16_f32m1(vbfloat16mf2_t vs2, size_t vl) {27 return __riscv_nds_vfwcvt_s_bf16_f32m1(vs2, vl);28}29 30// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_nds_vfwcvt_s_bf16_f32m231// CHECK-RV64-SAME: (<vscale x 4 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {32// CHECK-RV64-NEXT: entry:33// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv4f32.nxv4bf16.i64(<vscale x 4 x float> poison, <vscale x 4 x bfloat> [[VS2]], i64 [[VL]])34// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]35//36vfloat32m2_t test_nds_vfwcvt_s_bf16_f32m2(vbfloat16m1_t vs2, size_t vl) {37 return __riscv_nds_vfwcvt_s_bf16_f32m2(vs2, vl);38}39 40// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_nds_vfwcvt_s_bf16_f32m441// CHECK-RV64-SAME: (<vscale x 8 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {42// CHECK-RV64-NEXT: entry:43// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv8f32.nxv8bf16.i64(<vscale x 8 x float> poison, <vscale x 8 x bfloat> [[VS2]], i64 [[VL]])44// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]45//46vfloat32m4_t test_nds_vfwcvt_s_bf16_f32m4(vbfloat16m2_t vs2, size_t vl) {47 return __riscv_nds_vfwcvt_s_bf16_f32m4(vs2, vl);48}49 50// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_nds_vfwcvt_s_bf16_f32m851// CHECK-RV64-SAME: (<vscale x 16 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {52// CHECK-RV64-NEXT: entry:53// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv16f32.nxv16bf16.i64(<vscale x 16 x float> poison, <vscale x 16 x bfloat> [[VS2]], i64 [[VL]])54// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]55//56vfloat32m8_t test_nds_vfwcvt_s_bf16_f32m8(vbfloat16m4_t vs2, size_t vl) {57 return __riscv_nds_vfwcvt_s_bf16_f32m8(vs2, vl);58}59