225 lines · c
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py2// REQUIRES: riscv-registered-target3// RUN: %clang_cc1 -triple riscv64 -target-feature +zve64x \4// RUN: -target-feature +xandesvpackfph -disable-O0-optnone \5// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \6// RUN: FileCheck --check-prefix=CHECK-RV64 %s7 8#include <andes_vector.h>9 10// CHECK-RV64-LABEL: @test_nds_vfpmadb_vf_f16mf4(11// CHECK-RV64-NEXT: entry:12// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.nxv1f16.f32.i64(<vscale x 1 x half> poison, <vscale x 1 x half> [[OP1:%.*]], float [[OP2:%.*]], i64 7, i64 [[VL:%.*]])13// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]14//15vfloat16mf4_t test_nds_vfpmadb_vf_f16mf4(vfloat16mf4_t op1, float op2, size_t vl) {16 return __riscv_nds_vfpmadb(op1, op2, vl);17}18 19// CHECK-RV64-LABEL: @test_nds_vfpmadb_vf_f16mf2(20// CHECK-RV64-NEXT: entry:21// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadb.nxv2f16.f32.i64(<vscale x 2 x half> poison, <vscale x 2 x half> [[OP1:%.*]], float [[OP2:%.*]], i64 7, i64 [[VL:%.*]])22// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]23//24vfloat16mf2_t test_nds_vfpmadb_vf_f16mf2(vfloat16mf2_t op1, float op2, size_t vl) {25 return __riscv_nds_vfpmadb(op1, op2, vl);26}27 28// CHECK-RV64-LABEL: @test_nds_vfpmadb_vf_f16m1(29// CHECK-RV64-NEXT: entry:30// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.nds.vfpmadb.nxv4f16.f32.i64(<vscale x 4 x half> poison, <vscale x 4 x half> [[OP1:%.*]], float [[OP2:%.*]], i64 7, i64 [[VL:%.*]])31// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]32//33vfloat16m1_t test_nds_vfpmadb_vf_f16m1(vfloat16m1_t op1, float op2, size_t vl) {34 return __riscv_nds_vfpmadb(op1, op2, vl);35}36 37// CHECK-RV64-LABEL: @test_nds_vfpmadb_vf_f16m2(38// CHECK-RV64-NEXT: entry:39// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.nds.vfpmadb.nxv8f16.f32.i64(<vscale x 8 x half> poison, <vscale x 8 x half> [[OP1:%.*]], float [[OP2:%.*]], i64 7, i64 [[VL:%.*]])40// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]41//42vfloat16m2_t test_nds_vfpmadb_vf_f16m2(vfloat16m2_t op1, float op2, size_t vl) {43 return __riscv_nds_vfpmadb(op1, op2, vl);44}45 46// CHECK-RV64-LABEL: @test_nds_vfpmadb_vf_f16m4(47// CHECK-RV64-NEXT: entry:48// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.nds.vfpmadb.nxv16f16.f32.i64(<vscale x 16 x half> poison, <vscale x 16 x half> [[OP1:%.*]], float [[OP2:%.*]], i64 7, i64 [[VL:%.*]])49// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]50//51vfloat16m4_t test_nds_vfpmadb_vf_f16m4(vfloat16m4_t op1, float op2, size_t vl) {52 return __riscv_nds_vfpmadb(op1, op2, vl);53}54 55// CHECK-RV64-LABEL: @test_nds_vfpmadb_vf_f16m8(56// CHECK-RV64-NEXT: entry:57// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.nds.vfpmadb.nxv32f16.f32.i64(<vscale x 32 x half> poison, <vscale x 32 x half> [[OP1:%.*]], float [[OP2:%.*]], i64 7, i64 [[VL:%.*]])58// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]59//60vfloat16m8_t test_nds_vfpmadb_vf_f16m8(vfloat16m8_t op1, float op2, size_t vl) {61 return __riscv_nds_vfpmadb(op1, op2, vl);62}63 64// CHECK-RV64-LABEL: @test_nds_vfpmadb_vf_f16mf4_m(65// CHECK-RV64-NEXT: entry:66// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.mask.nxv1f16.f32.i64(<vscale x 1 x half> poison, <vscale x 1 x half> [[OP1:%.*]], float [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 7, i64 [[VL:%.*]], i64 3)67// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]68//69vfloat16mf4_t test_nds_vfpmadb_vf_f16mf4_m(vbool64_t mask, vfloat16mf4_t op1, float op2, size_t vl) {70 return __riscv_nds_vfpmadb(mask, op1, op2, vl);71}72 73// CHECK-RV64-LABEL: @test_nds_vfpmadb_vf_f16mf2_m(74// CHECK-RV64-NEXT: entry:75// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadb.mask.nxv2f16.f32.i64(<vscale x 2 x half> poison, <vscale x 2 x half> [[OP1:%.*]], float [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 7, i64 [[VL:%.*]], i64 3)76// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]77//78vfloat16mf2_t test_nds_vfpmadb_vf_f16mf2_m(vbool32_t mask, vfloat16mf2_t op1, float op2, size_t vl) {79 return __riscv_nds_vfpmadb(mask, op1, op2, vl);80}81 82// CHECK-RV64-LABEL: @test_nds_vfpmadb_vf_f16m1_m(83// CHECK-RV64-NEXT: entry:84// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.nds.vfpmadb.mask.nxv4f16.f32.i64(<vscale x 4 x half> poison, <vscale x 4 x half> [[OP1:%.*]], float [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 7, i64 [[VL:%.*]], i64 3)85// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]86//87vfloat16m1_t test_nds_vfpmadb_vf_f16m1_m(vbool16_t mask, vfloat16m1_t op1, float op2, size_t vl) {88 return __riscv_nds_vfpmadb(mask, op1, op2, vl);89}90 91// CHECK-RV64-LABEL: @test_nds_vfpmadb_vf_f16m2_m(92// CHECK-RV64-NEXT: entry:93// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.nds.vfpmadb.mask.nxv8f16.f32.i64(<vscale x 8 x half> poison, <vscale x 8 x half> [[OP1:%.*]], float [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 7, i64 [[VL:%.*]], i64 3)94// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]95//96vfloat16m2_t test_nds_vfpmadb_vf_f16m2_m(vbool8_t mask, vfloat16m2_t op1, float op2, size_t vl) {97 return __riscv_nds_vfpmadb(mask, op1, op2, vl);98}99 100// CHECK-RV64-LABEL: @test_nds_vfpmadb_vf_f16m4_m(101// CHECK-RV64-NEXT: entry:102// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.nds.vfpmadb.mask.nxv16f16.f32.i64(<vscale x 16 x half> poison, <vscale x 16 x half> [[OP1:%.*]], float [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 7, i64 [[VL:%.*]], i64 3)103// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]104//105vfloat16m4_t test_nds_vfpmadb_vf_f16m4_m(vbool4_t mask, vfloat16m4_t op1, float op2, size_t vl) {106 return __riscv_nds_vfpmadb(mask, op1, op2, vl);107}108 109// CHECK-RV64-LABEL: @test_nds_vfpmadb_vf_f16m8_m(110// CHECK-RV64-NEXT: entry:111// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.nds.vfpmadb.mask.nxv32f16.f32.i64(<vscale x 32 x half> poison, <vscale x 32 x half> [[OP1:%.*]], float [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 7, i64 [[VL:%.*]], i64 3)112// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]113//114vfloat16m8_t test_nds_vfpmadb_vf_f16m8_m(vbool2_t mask, vfloat16m8_t op1, float op2, size_t vl) {115 return __riscv_nds_vfpmadb(mask, op1, op2, vl);116}117 118// CHECK-RV64-LABEL: @test_nds_vfpmadb_vf_f16mf4_rm(119// CHECK-RV64-NEXT: entry:120// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.nxv1f16.f32.i64(<vscale x 1 x half> poison, <vscale x 1 x half> [[OP1:%.*]], float [[OP2:%.*]], i64 0, i64 [[VL:%.*]])121// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]122//123vfloat16mf4_t test_nds_vfpmadb_vf_f16mf4_rm(vfloat16mf4_t op1, float op2, size_t vl) {124 return __riscv_nds_vfpmadb(op1, op2, __RISCV_FRM_RNE, vl);125}126 127// CHECK-RV64-LABEL: @test_nds_vfpmadb_vf_f16mf2_rm(128// CHECK-RV64-NEXT: entry:129// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadb.nxv2f16.f32.i64(<vscale x 2 x half> poison, <vscale x 2 x half> [[OP1:%.*]], float [[OP2:%.*]], i64 0, i64 [[VL:%.*]])130// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]131//132vfloat16mf2_t test_nds_vfpmadb_vf_f16mf2_rm(vfloat16mf2_t op1, float op2, size_t vl) {133 return __riscv_nds_vfpmadb(op1, op2, __RISCV_FRM_RNE, vl);134}135 136// CHECK-RV64-LABEL: @test_nds_vfpmadb_vf_f16m1_rm(137// CHECK-RV64-NEXT: entry:138// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.nds.vfpmadb.nxv4f16.f32.i64(<vscale x 4 x half> poison, <vscale x 4 x half> [[OP1:%.*]], float [[OP2:%.*]], i64 0, i64 [[VL:%.*]])139// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]140//141vfloat16m1_t test_nds_vfpmadb_vf_f16m1_rm(vfloat16m1_t op1, float op2, size_t vl) {142 return __riscv_nds_vfpmadb(op1, op2, __RISCV_FRM_RNE, vl);143}144 145// CHECK-RV64-LABEL: @test_nds_vfpmadb_vf_f16m2_rm(146// CHECK-RV64-NEXT: entry:147// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.nds.vfpmadb.nxv8f16.f32.i64(<vscale x 8 x half> poison, <vscale x 8 x half> [[OP1:%.*]], float [[OP2:%.*]], i64 0, i64 [[VL:%.*]])148// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]149//150vfloat16m2_t test_nds_vfpmadb_vf_f16m2_rm(vfloat16m2_t op1, float op2, size_t vl) {151 return __riscv_nds_vfpmadb(op1, op2, __RISCV_FRM_RNE, vl);152}153 154// CHECK-RV64-LABEL: @test_nds_vfpmadb_vf_f16m4_rm(155// CHECK-RV64-NEXT: entry:156// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.nds.vfpmadb.nxv16f16.f32.i64(<vscale x 16 x half> poison, <vscale x 16 x half> [[OP1:%.*]], float [[OP2:%.*]], i64 0, i64 [[VL:%.*]])157// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]158//159vfloat16m4_t test_nds_vfpmadb_vf_f16m4_rm(vfloat16m4_t op1, float op2, size_t vl) {160 return __riscv_nds_vfpmadb(op1, op2, __RISCV_FRM_RNE, vl);161}162 163// CHECK-RV64-LABEL: @test_nds_vfpmadb_vf_f16m8_rm(164// CHECK-RV64-NEXT: entry:165// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.nds.vfpmadb.nxv32f16.f32.i64(<vscale x 32 x half> poison, <vscale x 32 x half> [[OP1:%.*]], float [[OP2:%.*]], i64 0, i64 [[VL:%.*]])166// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]167//168vfloat16m8_t test_nds_vfpmadb_vf_f16m8_rm(vfloat16m8_t op1, float op2, size_t vl) {169 return __riscv_nds_vfpmadb(op1, op2, __RISCV_FRM_RNE, vl);170}171 172// CHECK-RV64-LABEL: @test_nds_vfpmadb_vf_f16mf4_rm_m(173// CHECK-RV64-NEXT: entry:174// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.mask.nxv1f16.f32.i64(<vscale x 1 x half> poison, <vscale x 1 x half> [[OP1:%.*]], float [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 0, i64 [[VL:%.*]], i64 3)175// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]176//177vfloat16mf4_t test_nds_vfpmadb_vf_f16mf4_rm_m(vbool64_t mask, vfloat16mf4_t op1, float op2, size_t vl) {178 return __riscv_nds_vfpmadb(mask, op1, op2, __RISCV_FRM_RNE, vl);179}180 181// CHECK-RV64-LABEL: @test_nds_vfpmadb_vf_f16mf2_rm_m(182// CHECK-RV64-NEXT: entry:183// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadb.mask.nxv2f16.f32.i64(<vscale x 2 x half> poison, <vscale x 2 x half> [[OP1:%.*]], float [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 0, i64 [[VL:%.*]], i64 3)184// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]185//186vfloat16mf2_t test_nds_vfpmadb_vf_f16mf2_rm_m(vbool32_t mask, vfloat16mf2_t op1, float op2, size_t vl) {187 return __riscv_nds_vfpmadb(mask, op1, op2, __RISCV_FRM_RNE, vl);188}189 190// CHECK-RV64-LABEL: @test_nds_vfpmadb_vf_f16m1_rm_m(191// CHECK-RV64-NEXT: entry:192// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.nds.vfpmadb.mask.nxv4f16.f32.i64(<vscale x 4 x half> poison, <vscale x 4 x half> [[OP1:%.*]], float [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 0, i64 [[VL:%.*]], i64 3)193// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]194//195vfloat16m1_t test_nds_vfpmadb_vf_f16m1_rm_m(vbool16_t mask, vfloat16m1_t op1, float op2, size_t vl) {196 return __riscv_nds_vfpmadb(mask, op1, op2, __RISCV_FRM_RNE, vl);197}198 199// CHECK-RV64-LABEL: @test_nds_vfpmadb_vf_f16m2_rm_m(200// CHECK-RV64-NEXT: entry:201// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.nds.vfpmadb.mask.nxv8f16.f32.i64(<vscale x 8 x half> poison, <vscale x 8 x half> [[OP1:%.*]], float [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 0, i64 [[VL:%.*]], i64 3)202// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]203//204vfloat16m2_t test_nds_vfpmadb_vf_f16m2_rm_m(vbool8_t mask, vfloat16m2_t op1, float op2, size_t vl) {205 return __riscv_nds_vfpmadb(mask, op1, op2, __RISCV_FRM_RNE, vl);206}207 208// CHECK-RV64-LABEL: @test_nds_vfpmadb_vf_f16m4_rm_m(209// CHECK-RV64-NEXT: entry:210// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.nds.vfpmadb.mask.nxv16f16.f32.i64(<vscale x 16 x half> poison, <vscale x 16 x half> [[OP1:%.*]], float [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 0, i64 [[VL:%.*]], i64 3)211// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]212//213vfloat16m4_t test_nds_vfpmadb_vf_f16m4_rm_m(vbool4_t mask, vfloat16m4_t op1, float op2, size_t vl) {214 return __riscv_nds_vfpmadb(mask, op1, op2, __RISCV_FRM_RNE, vl);215}216 217// CHECK-RV64-LABEL: @test_nds_vfpmadb_vf_f16m8_rm_m(218// CHECK-RV64-NEXT: entry:219// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.nds.vfpmadb.mask.nxv32f16.f32.i64(<vscale x 32 x half> poison, <vscale x 32 x half> [[OP1:%.*]], float [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 0, i64 [[VL:%.*]], i64 3)220// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]221//222vfloat16m8_t test_nds_vfpmadb_vf_f16m8_rm_m(vbool2_t mask, vfloat16m8_t op1, float op2, size_t vl) {223 return __riscv_nds_vfpmadb(mask, op1, op2, __RISCV_FRM_RNE, vl);224}225