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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 22// REQUIRES: riscv-registered-target3// RUN: %clang_cc1 -triple riscv64 -target-feature +zve64x \4// RUN: -target-feature +xandesvsintload -disable-O0-optnone \5// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \6// RUN: FileCheck --check-prefix=CHECK-RV64 %s7 8#include <andes_vector.h>9 10// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_nds_vln8_v_i8mf8_m11// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {12// CHECK-RV64-NEXT: entry:13// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.nds.vln.mask.nxv1i8.p0.i64(<vscale x 1 x i8> poison, ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3)14// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]15//16vint8mf8_t test_nds_vln8_v_i8mf8_m(vbool64_t mask, const void *base, size_t vl) {17 return __riscv_nds_vln8(mask, base, vl);18}19 20// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_nds_vln8_v_i8mf4_m21// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {22// CHECK-RV64-NEXT: entry:23// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.nds.vln.mask.nxv2i8.p0.i64(<vscale x 2 x i8> poison, ptr [[BASE]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3)24// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]25//26vint8mf4_t test_nds_vln8_v_i8mf4_m(vbool32_t mask, const void *base, size_t vl) {27 return __riscv_nds_vln8(mask, base, vl);28}29 30// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_nds_vln8_v_i8mf2_m31// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {32// CHECK-RV64-NEXT: entry:33// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.nds.vln.mask.nxv4i8.p0.i64(<vscale x 4 x i8> poison, ptr [[BASE]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3)34// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]35//36vint8mf2_t test_nds_vln8_v_i8mf2_m(vbool16_t mask, const void *base, size_t vl) {37 return __riscv_nds_vln8(mask, base, vl);38}39 40// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_nds_vln8_v_i8m1_m41// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {42// CHECK-RV64-NEXT: entry:43// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.nds.vln.mask.nxv8i8.p0.i64(<vscale x 8 x i8> poison, ptr [[BASE]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3)44// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]45//46vint8m1_t test_nds_vln8_v_i8m1_m(vbool8_t mask, const void *base, size_t vl) {47 return __riscv_nds_vln8(mask, base, vl);48}49 50// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_nds_vln8_v_i8m2_m51// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {52// CHECK-RV64-NEXT: entry:53// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.nds.vln.mask.nxv16i8.p0.i64(<vscale x 16 x i8> poison, ptr [[BASE]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3)54// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]55//56vint8m2_t test_nds_vln8_v_i8m2_m(vbool4_t mask, const void *base, size_t vl) {57 return __riscv_nds_vln8(mask, base, vl);58}59 60// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_nds_vln8_v_i8m4_m61// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {62// CHECK-RV64-NEXT: entry:63// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.nds.vln.mask.nxv32i8.p0.i64(<vscale x 32 x i8> poison, ptr [[BASE]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 3)64// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]65//66vint8m4_t test_nds_vln8_v_i8m4_m(vbool2_t mask, const void *base, size_t vl) {67 return __riscv_nds_vln8(mask, base, vl);68}69 70// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_nds_vln8_v_i8m8_m71// CHECK-RV64-SAME: (<vscale x 64 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {72// CHECK-RV64-NEXT: entry:73// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.nds.vln.mask.nxv64i8.p0.i64(<vscale x 64 x i8> poison, ptr [[BASE]], <vscale x 64 x i1> [[MASK]], i64 [[VL]], i64 3)74// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]75//76vint8m8_t test_nds_vln8_v_i8m8_m(vbool1_t mask, const void *base, size_t vl) {77 return __riscv_nds_vln8(mask, base, vl);78}79