289 lines · c
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 22// REQUIRES: riscv-registered-target3// RUN: %clang_cc1 -triple riscv64 -target-feature +zve64x \4// RUN: -target-feature +xandesvsintload -disable-O0-optnone \5// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \6// RUN: FileCheck --check-prefix=CHECK-RV64 %s7 8#include <andes_vector.h>9 10// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_nds_vlnu8_v_u8mf8_tu11// CHECK-RV64-SAME: (<vscale x 1 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {12// CHECK-RV64-NEXT: entry:13// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.nds.vlnu.nxv1i8.p0.i64(<vscale x 1 x i8> [[MASKEDOFF]], ptr [[BASE]], i64 [[VL]])14// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]15//16vuint8mf8_t test_nds_vlnu8_v_u8mf8_tu(vuint8mf8_t maskedoff, const void *base, size_t vl) {17 return __riscv_nds_vlnu8_v_u8mf8_tu(maskedoff, base, vl);18}19 20// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_nds_vlnu8_v_u8mf4_tu21// CHECK-RV64-SAME: (<vscale x 2 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {22// CHECK-RV64-NEXT: entry:23// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.nds.vlnu.nxv2i8.p0.i64(<vscale x 2 x i8> [[MASKEDOFF]], ptr [[BASE]], i64 [[VL]])24// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]25//26vuint8mf4_t test_nds_vlnu8_v_u8mf4_tu(vuint8mf4_t maskedoff, const void *base, size_t vl) {27 return __riscv_nds_vlnu8_v_u8mf4_tu(maskedoff, base, vl);28}29 30// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_nds_vlnu8_v_u8mf2_tu31// CHECK-RV64-SAME: (<vscale x 4 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {32// CHECK-RV64-NEXT: entry:33// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.nds.vlnu.nxv4i8.p0.i64(<vscale x 4 x i8> [[MASKEDOFF]], ptr [[BASE]], i64 [[VL]])34// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]35//36vuint8mf2_t test_nds_vlnu8_v_u8mf2_tu(vuint8mf2_t maskedoff, const void *base, size_t vl) {37 return __riscv_nds_vlnu8_v_u8mf2_tu(maskedoff, base, vl);38}39 40// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_nds_vlnu8_v_u8m1_tu41// CHECK-RV64-SAME: (<vscale x 8 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {42// CHECK-RV64-NEXT: entry:43// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.nds.vlnu.nxv8i8.p0.i64(<vscale x 8 x i8> [[MASKEDOFF]], ptr [[BASE]], i64 [[VL]])44// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]45//46vuint8m1_t test_nds_vlnu8_v_u8m1_tu(vuint8m1_t maskedoff, const void *base, size_t vl) {47 return __riscv_nds_vlnu8_v_u8m1_tu(maskedoff, base, vl);48}49 50// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_nds_vlnu8_v_u8m2_tu51// CHECK-RV64-SAME: (<vscale x 16 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {52// CHECK-RV64-NEXT: entry:53// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.nds.vlnu.nxv16i8.p0.i64(<vscale x 16 x i8> [[MASKEDOFF]], ptr [[BASE]], i64 [[VL]])54// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]55//56vuint8m2_t test_nds_vlnu8_v_u8m2_tu(vuint8m2_t maskedoff, const void *base, size_t vl) {57 return __riscv_nds_vlnu8_v_u8m2_tu(maskedoff, base, vl);58}59 60// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_nds_vlnu8_v_u8m4_tu61// CHECK-RV64-SAME: (<vscale x 32 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {62// CHECK-RV64-NEXT: entry:63// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.nds.vlnu.nxv32i8.p0.i64(<vscale x 32 x i8> [[MASKEDOFF]], ptr [[BASE]], i64 [[VL]])64// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]65//66vuint8m4_t test_nds_vlnu8_v_u8m4_tu(vuint8m4_t maskedoff, const void *base, size_t vl) {67 return __riscv_nds_vlnu8_v_u8m4_tu(maskedoff, base, vl);68}69 70// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_nds_vlnu8_v_u8m8_tu71// CHECK-RV64-SAME: (<vscale x 64 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {72// CHECK-RV64-NEXT: entry:73// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.nds.vlnu.nxv64i8.p0.i64(<vscale x 64 x i8> [[MASKEDOFF]], ptr [[BASE]], i64 [[VL]])74// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]75//76vuint8m8_t test_nds_vlnu8_v_u8m8_tu(vuint8m8_t maskedoff, const void *base, size_t vl) {77 return __riscv_nds_vlnu8_v_u8m8_tu(maskedoff, base, vl);78}79 80// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_nds_vlnu8_v_u8mf8_tum81// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {82// CHECK-RV64-NEXT: entry:83// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.nds.vlnu.mask.nxv1i8.p0.i64(<vscale x 1 x i8> [[MASKEDOFF]], ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)84// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]85//86vuint8mf8_t test_nds_vlnu8_v_u8mf8_tum(vbool64_t mask, vuint8mf8_t maskedoff, const void *base, size_t vl) {87 return __riscv_nds_vlnu8_v_u8mf8_tum(mask, maskedoff, base, vl);88}89 90// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_nds_vlnu8_v_u8mf4_tum91// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {92// CHECK-RV64-NEXT: entry:93// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.nds.vlnu.mask.nxv2i8.p0.i64(<vscale x 2 x i8> [[MASKEDOFF]], ptr [[BASE]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)94// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]95//96vuint8mf4_t test_nds_vlnu8_v_u8mf4_tum(vbool32_t mask, vuint8mf4_t maskedoff, const void *base, size_t vl) {97 return __riscv_nds_vlnu8_v_u8mf4_tum(mask, maskedoff, base, vl);98}99 100// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_nds_vlnu8_v_u8mf2_tum101// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {102// CHECK-RV64-NEXT: entry:103// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.nds.vlnu.mask.nxv4i8.p0.i64(<vscale x 4 x i8> [[MASKEDOFF]], ptr [[BASE]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)104// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]105//106vuint8mf2_t test_nds_vlnu8_v_u8mf2_tum(vbool16_t mask, vuint8mf2_t maskedoff, const void *base, size_t vl) {107 return __riscv_nds_vlnu8_v_u8mf2_tum(mask, maskedoff, base, vl);108}109 110// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_nds_vlnu8_v_u8m1_tum111// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {112// CHECK-RV64-NEXT: entry:113// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.nds.vlnu.mask.nxv8i8.p0.i64(<vscale x 8 x i8> [[MASKEDOFF]], ptr [[BASE]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)114// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]115//116vuint8m1_t test_nds_vlnu8_v_u8m1_tum(vbool8_t mask, vuint8m1_t maskedoff, const void *base, size_t vl) {117 return __riscv_nds_vlnu8_v_u8m1_tum(mask, maskedoff, base, vl);118}119 120// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_nds_vlnu8_v_u8m2_tum121// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {122// CHECK-RV64-NEXT: entry:123// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.nds.vlnu.mask.nxv16i8.p0.i64(<vscale x 16 x i8> [[MASKEDOFF]], ptr [[BASE]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2)124// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]125//126vuint8m2_t test_nds_vlnu8_v_u8m2_tum(vbool4_t mask, vuint8m2_t maskedoff, const void *base, size_t vl) {127 return __riscv_nds_vlnu8_v_u8m2_tum(mask, maskedoff, base, vl);128}129 130// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_nds_vlnu8_v_u8m4_tum131// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {132// CHECK-RV64-NEXT: entry:133// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.nds.vlnu.mask.nxv32i8.p0.i64(<vscale x 32 x i8> [[MASKEDOFF]], ptr [[BASE]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 2)134// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]135//136vuint8m4_t test_nds_vlnu8_v_u8m4_tum(vbool2_t mask, vuint8m4_t maskedoff, const void *base, size_t vl) {137 return __riscv_nds_vlnu8_v_u8m4_tum(mask, maskedoff, base, vl);138}139 140// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_nds_vlnu8_v_u8m8_tum141// CHECK-RV64-SAME: (<vscale x 64 x i1> [[MASK:%.*]], <vscale x 64 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {142// CHECK-RV64-NEXT: entry:143// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.nds.vlnu.mask.nxv64i8.p0.i64(<vscale x 64 x i8> [[MASKEDOFF]], ptr [[BASE]], <vscale x 64 x i1> [[MASK]], i64 [[VL]], i64 2)144// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]145//146vuint8m8_t test_nds_vlnu8_v_u8m8_tum(vbool1_t mask, vuint8m8_t maskedoff, const void *base, size_t vl) {147 return __riscv_nds_vlnu8_v_u8m8_tum(mask, maskedoff, base, vl);148}149 150// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_nds_vlnu8_v_u8mf8_tumu151// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {152// CHECK-RV64-NEXT: entry:153// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.nds.vlnu.mask.nxv1i8.p0.i64(<vscale x 1 x i8> [[MASKEDOFF]], ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)154// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]155//156vuint8mf8_t test_nds_vlnu8_v_u8mf8_tumu(vbool64_t mask, vuint8mf8_t maskedoff, const void *base, size_t vl) {157 return __riscv_nds_vlnu8_v_u8mf8_tumu(mask, maskedoff, base, vl);158}159 160// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_nds_vlnu8_v_u8mf4_tumu161// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {162// CHECK-RV64-NEXT: entry:163// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.nds.vlnu.mask.nxv2i8.p0.i64(<vscale x 2 x i8> [[MASKEDOFF]], ptr [[BASE]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)164// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]165//166vuint8mf4_t test_nds_vlnu8_v_u8mf4_tumu(vbool32_t mask, vuint8mf4_t maskedoff, const void *base, size_t vl) {167 return __riscv_nds_vlnu8_v_u8mf4_tumu(mask, maskedoff, base, vl);168}169 170// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_nds_vlnu8_v_u8mf2_tumu171// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {172// CHECK-RV64-NEXT: entry:173// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.nds.vlnu.mask.nxv4i8.p0.i64(<vscale x 4 x i8> [[MASKEDOFF]], ptr [[BASE]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)174// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]175//176vuint8mf2_t test_nds_vlnu8_v_u8mf2_tumu(vbool16_t mask, vuint8mf2_t maskedoff, const void *base, size_t vl) {177 return __riscv_nds_vlnu8_v_u8mf2_tumu(mask, maskedoff, base, vl);178}179 180// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_nds_vlnu8_v_u8m1_tumu181// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {182// CHECK-RV64-NEXT: entry:183// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.nds.vlnu.mask.nxv8i8.p0.i64(<vscale x 8 x i8> [[MASKEDOFF]], ptr [[BASE]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)184// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]185//186vuint8m1_t test_nds_vlnu8_v_u8m1_tumu(vbool8_t mask, vuint8m1_t maskedoff, const void *base, size_t vl) {187 return __riscv_nds_vlnu8_v_u8m1_tumu(mask, maskedoff, base, vl);188}189 190// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_nds_vlnu8_v_u8m2_tumu191// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {192// CHECK-RV64-NEXT: entry:193// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.nds.vlnu.mask.nxv16i8.p0.i64(<vscale x 16 x i8> [[MASKEDOFF]], ptr [[BASE]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0)194// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]195//196vuint8m2_t test_nds_vlnu8_v_u8m2_tumu(vbool4_t mask, vuint8m2_t maskedoff, const void *base, size_t vl) {197 return __riscv_nds_vlnu8_v_u8m2_tumu(mask, maskedoff, base, vl);198}199 200// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_nds_vlnu8_v_u8m4_tumu201// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {202// CHECK-RV64-NEXT: entry:203// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.nds.vlnu.mask.nxv32i8.p0.i64(<vscale x 32 x i8> [[MASKEDOFF]], ptr [[BASE]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 0)204// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]205//206vuint8m4_t test_nds_vlnu8_v_u8m4_tumu(vbool2_t mask, vuint8m4_t maskedoff, const void *base, size_t vl) {207 return __riscv_nds_vlnu8_v_u8m4_tumu(mask, maskedoff, base, vl);208}209 210// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_nds_vlnu8_v_u8m8_tumu211// CHECK-RV64-SAME: (<vscale x 64 x i1> [[MASK:%.*]], <vscale x 64 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {212// CHECK-RV64-NEXT: entry:213// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.nds.vlnu.mask.nxv64i8.p0.i64(<vscale x 64 x i8> [[MASKEDOFF]], ptr [[BASE]], <vscale x 64 x i1> [[MASK]], i64 [[VL]], i64 0)214// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]215//216vuint8m8_t test_nds_vlnu8_v_u8m8_tumu(vbool1_t mask, vuint8m8_t maskedoff, const void *base, size_t vl) {217 return __riscv_nds_vlnu8_v_u8m8_tumu(mask, maskedoff, base, vl);218}219 220// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_nds_vlnu8_v_u8mf8_mu221// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {222// CHECK-RV64-NEXT: entry:223// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.nds.vlnu.mask.nxv1i8.p0.i64(<vscale x 1 x i8> [[MASKEDOFF]], ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)224// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]225//226vuint8mf8_t test_nds_vlnu8_v_u8mf8_mu(vbool64_t mask, vuint8mf8_t maskedoff, const void *base, size_t vl) {227 return __riscv_nds_vlnu8_v_u8mf8_mu(mask, maskedoff, base, vl);228}229 230// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_nds_vlnu8_v_u8mf4_mu231// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {232// CHECK-RV64-NEXT: entry:233// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.nds.vlnu.mask.nxv2i8.p0.i64(<vscale x 2 x i8> [[MASKEDOFF]], ptr [[BASE]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)234// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]235//236vuint8mf4_t test_nds_vlnu8_v_u8mf4_mu(vbool32_t mask, vuint8mf4_t maskedoff, const void *base, size_t vl) {237 return __riscv_nds_vlnu8_v_u8mf4_mu(mask, maskedoff, base, vl);238}239 240// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_nds_vlnu8_v_u8mf2_mu241// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {242// CHECK-RV64-NEXT: entry:243// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.nds.vlnu.mask.nxv4i8.p0.i64(<vscale x 4 x i8> [[MASKEDOFF]], ptr [[BASE]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)244// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]245//246vuint8mf2_t test_nds_vlnu8_v_u8mf2_mu(vbool16_t mask, vuint8mf2_t maskedoff, const void *base, size_t vl) {247 return __riscv_nds_vlnu8_v_u8mf2_mu(mask, maskedoff, base, vl);248}249 250// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_nds_vlnu8_v_u8m1_mu251// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {252// CHECK-RV64-NEXT: entry:253// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.nds.vlnu.mask.nxv8i8.p0.i64(<vscale x 8 x i8> [[MASKEDOFF]], ptr [[BASE]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)254// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]255//256vuint8m1_t test_nds_vlnu8_v_u8m1_mu(vbool8_t mask, vuint8m1_t maskedoff, const void *base, size_t vl) {257 return __riscv_nds_vlnu8_v_u8m1_mu(mask, maskedoff, base, vl);258}259 260// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_nds_vlnu8_v_u8m2_mu261// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {262// CHECK-RV64-NEXT: entry:263// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.nds.vlnu.mask.nxv16i8.p0.i64(<vscale x 16 x i8> [[MASKEDOFF]], ptr [[BASE]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1)264// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]265//266vuint8m2_t test_nds_vlnu8_v_u8m2_mu(vbool4_t mask, vuint8m2_t maskedoff, const void *base, size_t vl) {267 return __riscv_nds_vlnu8_v_u8m2_mu(mask, maskedoff, base, vl);268}269 270// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_nds_vlnu8_v_u8m4_mu271// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {272// CHECK-RV64-NEXT: entry:273// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.nds.vlnu.mask.nxv32i8.p0.i64(<vscale x 32 x i8> [[MASKEDOFF]], ptr [[BASE]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 1)274// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]275//276vuint8m4_t test_nds_vlnu8_v_u8m4_mu(vbool2_t mask, vuint8m4_t maskedoff, const void *base, size_t vl) {277 return __riscv_nds_vlnu8_v_u8m4_mu(mask, maskedoff, base, vl);278}279 280// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_nds_vlnu8_v_u8m8_mu281// CHECK-RV64-SAME: (<vscale x 64 x i1> [[MASK:%.*]], <vscale x 64 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {282// CHECK-RV64-NEXT: entry:283// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.nds.vlnu.mask.nxv64i8.p0.i64(<vscale x 64 x i8> [[MASKEDOFF]], ptr [[BASE]], <vscale x 64 x i1> [[MASK]], i64 [[VL]], i64 1)284// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]285//286vuint8m8_t test_nds_vlnu8_v_u8m8_mu(vbool1_t mask, vuint8m8_t maskedoff, const void *base, size_t vl) {287 return __riscv_nds_vlnu8_v_u8m8_mu(mask, maskedoff, base, vl);288}289