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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 22// REQUIRES: riscv-registered-target3// RUN: %clang_cc1 -triple riscv64 -target-feature +v \4// RUN: -target-feature +xandesvbfhcvt -disable-O0-optnone \5// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \6// RUN: FileCheck --check-prefix=CHECK-RV64 %s7 8#include <andes_vector.h>9 10// CHECK-RV64-LABEL: define dso_local <vscale x 1 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf4_tu11// CHECK-RV64-SAME: (<vscale x 1 x bfloat> [[VD:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {12// CHECK-RV64-NEXT: entry:13// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> [[VD]], <vscale x 1 x float> [[VS2]], i64 7, i64 [[VL]])14// CHECK-RV64-NEXT: ret <vscale x 1 x bfloat> [[TMP0]]15//16vbfloat16mf4_t test_nds_vfncvt_bf16_s_bf16mf4_tu(vbfloat16mf4_t vd,17 vfloat32mf2_t vs2, size_t vl) {18 return __riscv_nds_vfncvt_bf16_tu(vd, vs2, vl);19}20 21// CHECK-RV64-LABEL: define dso_local <vscale x 2 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf2_tu22// CHECK-RV64-SAME: (<vscale x 2 x bfloat> [[VD:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {23// CHECK-RV64-NEXT: entry:24// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> [[VD]], <vscale x 2 x float> [[VS2]], i64 7, i64 [[VL]])25// CHECK-RV64-NEXT: ret <vscale x 2 x bfloat> [[TMP0]]26//27vbfloat16mf2_t test_nds_vfncvt_bf16_s_bf16mf2_tu(vbfloat16mf2_t vd,28 vfloat32m1_t vs2, size_t vl) {29 return __riscv_nds_vfncvt_bf16_tu(vd, vs2, vl);30}31 32// CHECK-RV64-LABEL: define dso_local <vscale x 4 x bfloat> @test_nds_vfncvt_bf16_s_bf16m1_tu33// CHECK-RV64-SAME: (<vscale x 4 x bfloat> [[VD:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {34// CHECK-RV64-NEXT: entry:35// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> [[VD]], <vscale x 4 x float> [[VS2]], i64 7, i64 [[VL]])36// CHECK-RV64-NEXT: ret <vscale x 4 x bfloat> [[TMP0]]37//38vbfloat16m1_t test_nds_vfncvt_bf16_s_bf16m1_tu(vbfloat16m1_t vd,39 vfloat32m2_t vs2, size_t vl) {40 return __riscv_nds_vfncvt_bf16_tu(vd, vs2, vl);41}42 43// CHECK-RV64-LABEL: define dso_local <vscale x 8 x bfloat> @test_nds_vfncvt_bf16_s_bf16m2_tu44// CHECK-RV64-SAME: (<vscale x 8 x bfloat> [[VD:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {45// CHECK-RV64-NEXT: entry:46// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> [[VD]], <vscale x 8 x float> [[VS2]], i64 7, i64 [[VL]])47// CHECK-RV64-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]48//49vbfloat16m2_t test_nds_vfncvt_bf16_s_bf16m2_tu(vbfloat16m2_t vd,50 vfloat32m4_t vs2, size_t vl) {51 return __riscv_nds_vfncvt_bf16_tu(vd, vs2, vl);52}53 54// CHECK-RV64-LABEL: define dso_local <vscale x 16 x bfloat> @test_nds_vfncvt_bf16_s_bf16m4_tu55// CHECK-RV64-SAME: (<vscale x 16 x bfloat> [[VD:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {56// CHECK-RV64-NEXT: entry:57// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> [[VD]], <vscale x 16 x float> [[VS2]], i64 7, i64 [[VL]])58// CHECK-RV64-NEXT: ret <vscale x 16 x bfloat> [[TMP0]]59//60vbfloat16m4_t test_nds_vfncvt_bf16_s_bf16m4_tu(vbfloat16m4_t vd,61 vfloat32m8_t vs2, size_t vl) {62 return __riscv_nds_vfncvt_bf16_tu(vd, vs2, vl);63}64 65// CHECK-RV64-LABEL: define dso_local <vscale x 1 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf4_rm_tu66// CHECK-RV64-SAME: (<vscale x 1 x bfloat> [[VD:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {67// CHECK-RV64-NEXT: entry:68// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> [[VD]], <vscale x 1 x float> [[VS2]], i64 0, i64 [[VL]])69// CHECK-RV64-NEXT: ret <vscale x 1 x bfloat> [[TMP0]]70//71vbfloat16mf4_t test_nds_vfncvt_bf16_s_bf16mf4_rm_tu(vbfloat16mf4_t vd,72 vfloat32mf2_t vs2,73 size_t vl) {74 return __riscv_nds_vfncvt_bf16_tu(vd, vs2, __RISCV_FRM_RNE, vl);75}76 77// CHECK-RV64-LABEL: define dso_local <vscale x 2 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf2_rm_tu78// CHECK-RV64-SAME: (<vscale x 2 x bfloat> [[VD:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {79// CHECK-RV64-NEXT: entry:80// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> [[VD]], <vscale x 2 x float> [[VS2]], i64 0, i64 [[VL]])81// CHECK-RV64-NEXT: ret <vscale x 2 x bfloat> [[TMP0]]82//83vbfloat16mf2_t test_nds_vfncvt_bf16_s_bf16mf2_rm_tu(vbfloat16mf2_t vd,84 vfloat32m1_t vs2,85 size_t vl) {86 return __riscv_nds_vfncvt_bf16_tu(vd, vs2, __RISCV_FRM_RNE, vl);87}88 89// CHECK-RV64-LABEL: define dso_local <vscale x 4 x bfloat> @test_nds_vfncvt_bf16_s_bf16m1_rm_tu90// CHECK-RV64-SAME: (<vscale x 4 x bfloat> [[VD:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {91// CHECK-RV64-NEXT: entry:92// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> [[VD]], <vscale x 4 x float> [[VS2]], i64 0, i64 [[VL]])93// CHECK-RV64-NEXT: ret <vscale x 4 x bfloat> [[TMP0]]94//95vbfloat16m1_t test_nds_vfncvt_bf16_s_bf16m1_rm_tu(vbfloat16m1_t vd,96 vfloat32m2_t vs2, size_t vl) {97 return __riscv_nds_vfncvt_bf16_tu(vd, vs2, __RISCV_FRM_RNE, vl);98}99 100// CHECK-RV64-LABEL: define dso_local <vscale x 8 x bfloat> @test_nds_vfncvt_bf16_s_bf16m2_rm_tu101// CHECK-RV64-SAME: (<vscale x 8 x bfloat> [[VD:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {102// CHECK-RV64-NEXT: entry:103// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> [[VD]], <vscale x 8 x float> [[VS2]], i64 0, i64 [[VL]])104// CHECK-RV64-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]105//106vbfloat16m2_t test_nds_vfncvt_bf16_s_bf16m2_rm_tu(vbfloat16m2_t vd,107 vfloat32m4_t vs2, size_t vl) {108 return __riscv_nds_vfncvt_bf16_tu(vd, vs2, __RISCV_FRM_RNE, vl);109}110 111// CHECK-RV64-LABEL: define dso_local <vscale x 16 x bfloat> @test_nds_vfncvt_bf16_s_bf16m4_rm_tu112// CHECK-RV64-SAME: (<vscale x 16 x bfloat> [[VD:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {113// CHECK-RV64-NEXT: entry:114// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> [[VD]], <vscale x 16 x float> [[VS2]], i64 0, i64 [[VL]])115// CHECK-RV64-NEXT: ret <vscale x 16 x bfloat> [[TMP0]]116//117vbfloat16m4_t test_nds_vfncvt_bf16_s_bf16m4_rm_tu(vbfloat16m4_t vd,118 vfloat32m8_t vs2, size_t vl) {119 return __riscv_nds_vfncvt_bf16_tu(vd, vs2, __RISCV_FRM_RNE, vl);120}121