319 lines · c
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py2// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +f -target-feature +d -target-feature +zve64d -mvscale-min=4 -mvscale-max=4 -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s3 4// REQUIRES: riscv-registered-target5 6#include <riscv_vector.h>7 8typedef __rvv_int8m1_t vint8m1_t;9typedef __rvv_uint8m1_t vuint8m1_t;10typedef __rvv_int16m1_t vint16m1_t;11typedef __rvv_uint16m1_t vuint16m1_t;12typedef __rvv_int32m1_t vint32m1_t;13typedef __rvv_uint32m1_t vuint32m1_t;14typedef __rvv_int64m1_t vint64m1_t;15typedef __rvv_uint64m1_t vuint64m1_t;16typedef __rvv_float32m1_t vfloat32m1_t;17typedef __rvv_float64m1_t vfloat64m1_t;18 19typedef __rvv_int8m2_t vint8m2_t;20typedef __rvv_uint8m2_t vuint8m2_t;21typedef __rvv_int16m2_t vint16m2_t;22typedef __rvv_uint16m2_t vuint16m2_t;23typedef __rvv_int32m2_t vint32m2_t;24typedef __rvv_uint32m2_t vuint32m2_t;25typedef __rvv_int64m2_t vint64m2_t;26typedef __rvv_uint64m2_t vuint64m2_t;27typedef __rvv_float32m2_t vfloat32m2_t;28typedef __rvv_float64m2_t vfloat64m2_t;29 30typedef __rvv_bool1_t vbool1_t;31typedef __rvv_bool4_t vbool4_t;32typedef __rvv_bool32_t vbool32_t;33 34typedef vint32m1_t fixed_int32m1_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen)));35typedef vint32m2_t fixed_int32m2_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen * 2)));36typedef vint16m4_t fixed_int16m4_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen * 4)));37typedef vint8m8_t fixed_int8m8_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen * 8)));38typedef vbool1_t fixed_bool1_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen)));39typedef vbool4_t fixed_bool4_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen/4)));40typedef vbool32_t fixed_bool32_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen/32)));41 42fixed_int32m1_t global_vec;43fixed_int32m2_t global_vec_m2;44fixed_int8m8_t global_vec_int8m8;45fixed_int16m4_t global_vec_int16m4;46fixed_bool1_t global_bool1;47fixed_bool4_t global_bool4;48fixed_bool32_t global_bool32;49 50// CHECK-LABEL: @test_bool1(51// CHECK-NEXT: entry:52// CHECK-NEXT: [[RETVAL:%.*]] = alloca <256 x i8>, align 853// CHECK-NEXT: [[M_ADDR:%.*]] = alloca <vscale x 64 x i1>, align 154// CHECK-NEXT: [[VEC_ADDR:%.*]] = alloca <vscale x 64 x i8>, align 155// CHECK-NEXT: [[MASK:%.*]] = alloca <vscale x 64 x i1>, align 156// CHECK-NEXT: store <vscale x 64 x i1> [[M:%.*]], ptr [[M_ADDR]], align 157// CHECK-NEXT: store <vscale x 64 x i8> [[VEC:%.*]], ptr [[VEC_ADDR]], align 158// CHECK-NEXT: [[TMP0:%.*]] = load <vscale x 64 x i1>, ptr [[M_ADDR]], align 159// CHECK-NEXT: [[TMP1:%.*]] = load <32 x i8>, ptr @global_bool1, align 860// CHECK-NEXT: [[CAST_SCALABLE:%.*]] = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v32i8(<vscale x 8 x i8> poison, <32 x i8> [[TMP1]], i64 0)61// CHECK-NEXT: [[TMP2:%.*]] = bitcast <vscale x 8 x i8> [[CAST_SCALABLE]] to <vscale x 64 x i1>62// CHECK-NEXT: [[TMP3:%.*]] = call <vscale x 64 x i1> @llvm.riscv.vmand.nxv64i1.i64(<vscale x 64 x i1> [[TMP0]], <vscale x 64 x i1> [[TMP2]], i64 256)63// CHECK-NEXT: store <vscale x 64 x i1> [[TMP3]], ptr [[MASK]], align 164// CHECK-NEXT: [[TMP4:%.*]] = load <vscale x 64 x i1>, ptr [[MASK]], align 165// CHECK-NEXT: [[TMP5:%.*]] = load <vscale x 64 x i8>, ptr [[VEC_ADDR]], align 166// CHECK-NEXT: [[TMP6:%.*]] = load <256 x i8>, ptr @global_vec_int8m8, align 867// CHECK-NEXT: [[CAST_SCALABLE1:%.*]] = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.v256i8(<vscale x 64 x i8> poison, <256 x i8> [[TMP6]], i64 0)68// CHECK-NEXT: [[TMP7:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vadd.mask.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> [[TMP5]], <vscale x 64 x i8> [[CAST_SCALABLE1]], <vscale x 64 x i1> [[TMP4]], i64 256, i64 3)69// CHECK-NEXT: [[CAST_FIXED:%.*]] = call <256 x i8> @llvm.vector.extract.v256i8.nxv64i8(<vscale x 64 x i8> [[TMP7]], i64 0)70// CHECK-NEXT: store <256 x i8> [[CAST_FIXED]], ptr [[RETVAL]], align 871// CHECK-NEXT: [[TMP8:%.*]] = load <256 x i8>, ptr [[RETVAL]], align 872// CHECK-NEXT: [[CAST_SCALABLE2:%.*]] = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.v256i8(<vscale x 64 x i8> poison, <256 x i8> [[TMP8]], i64 0)73// CHECK-NEXT: ret <vscale x 64 x i8> [[CAST_SCALABLE2]]74//75fixed_int8m8_t test_bool1(vbool1_t m, vint8m8_t vec) {76 vbool1_t mask = __riscv_vmand(m, global_bool1, __riscv_v_fixed_vlen);77 return __riscv_vadd(mask, vec, global_vec_int8m8, __riscv_v_fixed_vlen);78}79 80// CHECK-LABEL: @test_bool4(81// CHECK-NEXT: entry:82// CHECK-NEXT: [[RETVAL:%.*]] = alloca <64 x i16>, align 883// CHECK-NEXT: [[M_ADDR:%.*]] = alloca <vscale x 16 x i1>, align 184// CHECK-NEXT: [[VEC_ADDR:%.*]] = alloca <vscale x 16 x i16>, align 285// CHECK-NEXT: [[MASK:%.*]] = alloca <vscale x 16 x i1>, align 186// CHECK-NEXT: store <vscale x 16 x i1> [[M:%.*]], ptr [[M_ADDR]], align 187// CHECK-NEXT: store <vscale x 16 x i16> [[VEC:%.*]], ptr [[VEC_ADDR]], align 288// CHECK-NEXT: [[TMP0:%.*]] = load <vscale x 16 x i1>, ptr [[M_ADDR]], align 189// CHECK-NEXT: [[TMP1:%.*]] = load <8 x i8>, ptr @global_bool4, align 890// CHECK-NEXT: [[CAST_SCALABLE:%.*]] = call <vscale x 2 x i8> @llvm.vector.insert.nxv2i8.v8i8(<vscale x 2 x i8> poison, <8 x i8> [[TMP1]], i64 0)91// CHECK-NEXT: [[TMP2:%.*]] = bitcast <vscale x 2 x i8> [[CAST_SCALABLE]] to <vscale x 16 x i1>92// CHECK-NEXT: [[TMP3:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmand.nxv16i1.i64(<vscale x 16 x i1> [[TMP0]], <vscale x 16 x i1> [[TMP2]], i64 64)93// CHECK-NEXT: store <vscale x 16 x i1> [[TMP3]], ptr [[MASK]], align 194// CHECK-NEXT: [[TMP4:%.*]] = load <vscale x 16 x i1>, ptr [[MASK]], align 195// CHECK-NEXT: [[TMP5:%.*]] = load <vscale x 16 x i16>, ptr [[VEC_ADDR]], align 296// CHECK-NEXT: [[TMP6:%.*]] = load <64 x i16>, ptr @global_vec_int16m4, align 897// CHECK-NEXT: [[CAST_SCALABLE1:%.*]] = call <vscale x 16 x i16> @llvm.vector.insert.nxv16i16.v64i16(<vscale x 16 x i16> poison, <64 x i16> [[TMP6]], i64 0)98// CHECK-NEXT: [[TMP7:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vadd.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> [[TMP5]], <vscale x 16 x i16> [[CAST_SCALABLE1]], <vscale x 16 x i1> [[TMP4]], i64 64, i64 3)99// CHECK-NEXT: [[CAST_FIXED:%.*]] = call <64 x i16> @llvm.vector.extract.v64i16.nxv16i16(<vscale x 16 x i16> [[TMP7]], i64 0)100// CHECK-NEXT: store <64 x i16> [[CAST_FIXED]], ptr [[RETVAL]], align 8101// CHECK-NEXT: [[TMP8:%.*]] = load <64 x i16>, ptr [[RETVAL]], align 8102// CHECK-NEXT: [[CAST_SCALABLE2:%.*]] = call <vscale x 16 x i16> @llvm.vector.insert.nxv16i16.v64i16(<vscale x 16 x i16> poison, <64 x i16> [[TMP8]], i64 0)103// CHECK-NEXT: ret <vscale x 16 x i16> [[CAST_SCALABLE2]]104//105fixed_int16m4_t test_bool4(vbool4_t m, vint16m4_t vec) {106 vbool4_t mask = __riscv_vmand(m, global_bool4, __riscv_v_fixed_vlen/4);107 return __riscv_vadd(mask, vec, global_vec_int16m4, __riscv_v_fixed_vlen/4);108}109 110// CHECK-LABEL: @test_bool32(111// CHECK-NEXT: entry:112// CHECK-NEXT: [[RETVAL:%.*]] = alloca <8 x i32>, align 8113// CHECK-NEXT: [[M_ADDR:%.*]] = alloca <vscale x 2 x i1>, align 1114// CHECK-NEXT: [[VEC_ADDR:%.*]] = alloca <vscale x 2 x i32>, align 4115// CHECK-NEXT: [[MASK:%.*]] = alloca <vscale x 2 x i1>, align 1116// CHECK-NEXT: store <vscale x 2 x i1> [[M:%.*]], ptr [[M_ADDR]], align 1117// CHECK-NEXT: store <vscale x 2 x i32> [[VEC:%.*]], ptr [[VEC_ADDR]], align 4118// CHECK-NEXT: [[TMP0:%.*]] = load <vscale x 2 x i1>, ptr [[M_ADDR]], align 1119// CHECK-NEXT: [[TMP1:%.*]] = load <1 x i8>, ptr @global_bool32, align 1120// CHECK-NEXT: [[CAST_SCALABLE:%.*]] = call <vscale x 1 x i8> @llvm.vector.insert.nxv1i8.v1i8(<vscale x 1 x i8> poison, <1 x i8> [[TMP1]], i64 0)121// CHECK-NEXT: [[TMP2:%.*]] = bitcast <vscale x 1 x i8> [[CAST_SCALABLE]] to <vscale x 8 x i1>122// CHECK-NEXT: [[TMP3:%.*]] = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv8i1(<vscale x 8 x i1> [[TMP2]], i64 0)123// CHECK-NEXT: [[TMP4:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmand.nxv2i1.i64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x i1> [[TMP3]], i64 8)124// CHECK-NEXT: store <vscale x 2 x i1> [[TMP4]], ptr [[MASK]], align 1125// CHECK-NEXT: [[TMP5:%.*]] = load <vscale x 2 x i1>, ptr [[MASK]], align 1126// CHECK-NEXT: [[TMP6:%.*]] = load <vscale x 2 x i32>, ptr [[VEC_ADDR]], align 4127// CHECK-NEXT: [[TMP7:%.*]] = load <8 x i32>, ptr @global_vec, align 8128// CHECK-NEXT: [[CAST_SCALABLE1:%.*]] = call <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32> poison, <8 x i32> [[TMP7]], i64 0)129// CHECK-NEXT: [[TMP8:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vadd.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> [[TMP6]], <vscale x 2 x i32> [[CAST_SCALABLE1]], <vscale x 2 x i1> [[TMP5]], i64 8, i64 3)130// CHECK-NEXT: [[CAST_FIXED:%.*]] = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> [[TMP8]], i64 0)131// CHECK-NEXT: store <8 x i32> [[CAST_FIXED]], ptr [[RETVAL]], align 8132// CHECK-NEXT: [[TMP9:%.*]] = load <8 x i32>, ptr [[RETVAL]], align 8133// CHECK-NEXT: [[CAST_SCALABLE2:%.*]] = call <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32> poison, <8 x i32> [[TMP9]], i64 0)134// CHECK-NEXT: ret <vscale x 2 x i32> [[CAST_SCALABLE2]]135//136fixed_int32m1_t test_bool32(vbool32_t m, vint32m1_t vec) {137 vbool32_t mask = __riscv_vmand(m, global_bool32, __riscv_v_fixed_vlen/32);138 return __riscv_vadd(mask, vec, global_vec, __riscv_v_fixed_vlen/32);139}140 141// CHECK-LABEL: @test_ptr_to_global(142// CHECK-NEXT: entry:143// CHECK-NEXT: [[RETVAL:%.*]] = alloca <8 x i32>, align 8144// CHECK-NEXT: [[GLOBAL_VEC_PTR:%.*]] = alloca ptr, align 8145// CHECK-NEXT: store ptr @global_vec, ptr [[GLOBAL_VEC_PTR]], align 8146// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[GLOBAL_VEC_PTR]], align 8147// CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr [[TMP0]], align 8148// CHECK-NEXT: store <8 x i32> [[TMP1]], ptr [[RETVAL]], align 8149// CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr [[RETVAL]], align 8150// CHECK-NEXT: [[CAST_SCALABLE:%.*]] = call <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32> poison, <8 x i32> [[TMP2]], i64 0)151// CHECK-NEXT: ret <vscale x 2 x i32> [[CAST_SCALABLE]]152//153fixed_int32m1_t test_ptr_to_global() {154 fixed_int32m1_t *global_vec_ptr;155 global_vec_ptr = &global_vec;156 return *global_vec_ptr;157}158 159//160// Test casting pointer from fixed-length array to scalable vector.161// CHECK-LABEL: @array_arg(162// CHECK-NEXT: entry:163// CHECK-NEXT: [[RETVAL:%.*]] = alloca <8 x i32>, align 8164// CHECK-NEXT: [[ARR_ADDR:%.*]] = alloca ptr, align 8165// CHECK-NEXT: store ptr [[ARR:%.*]], ptr [[ARR_ADDR]], align 8166// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARR_ADDR]], align 8167// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds <8 x i32>, ptr [[TMP0]], i64 0168// CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr [[ARRAYIDX]], align 8169// CHECK-NEXT: store <8 x i32> [[TMP1]], ptr [[RETVAL]], align 8170// CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr [[RETVAL]], align 8171// CHECK-NEXT: [[CAST_SCALABLE:%.*]] = call <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32> poison, <8 x i32> [[TMP2]], i64 0)172// CHECK-NEXT: ret <vscale x 2 x i32> [[CAST_SCALABLE]]173//174fixed_int32m1_t array_arg(fixed_int32m1_t arr[]) {175 return arr[0];176}177 178// CHECK-LABEL: @address_of_array_idx_bool1(179// CHECK-NEXT: entry:180// CHECK-NEXT: [[RETVAL:%.*]] = alloca <32 x i8>, align 8181// CHECK-NEXT: [[ARR:%.*]] = alloca [3 x <32 x i8>], align 8182// CHECK-NEXT: [[PARR:%.*]] = alloca ptr, align 8183// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [3 x <32 x i8>], ptr [[ARR]], i64 0, i64 0184// CHECK-NEXT: store ptr [[ARRAYIDX]], ptr [[PARR]], align 8185// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PARR]], align 8186// CHECK-NEXT: [[TMP1:%.*]] = load <32 x i8>, ptr [[TMP0]], align 8187// CHECK-NEXT: store <32 x i8> [[TMP1]], ptr [[RETVAL]], align 8188// CHECK-NEXT: [[TMP2:%.*]] = load <32 x i8>, ptr [[RETVAL]], align 8189// CHECK-NEXT: [[CAST_SCALABLE:%.*]] = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v32i8(<vscale x 8 x i8> poison, <32 x i8> [[TMP2]], i64 0)190// CHECK-NEXT: [[TMP3:%.*]] = bitcast <vscale x 8 x i8> [[CAST_SCALABLE]] to <vscale x 64 x i1>191// CHECK-NEXT: ret <vscale x 64 x i1> [[TMP3]]192//193fixed_bool1_t address_of_array_idx_bool1() {194 fixed_bool1_t arr[3];195 fixed_bool1_t *parr;196 parr = &arr[0];197 return *parr;198}199 200// CHECK-LABEL: @address_of_array_idx_bool4(201// CHECK-NEXT: entry:202// CHECK-NEXT: [[RETVAL:%.*]] = alloca <8 x i8>, align 8203// CHECK-NEXT: [[ARR:%.*]] = alloca [3 x <8 x i8>], align 8204// CHECK-NEXT: [[PARR:%.*]] = alloca ptr, align 8205// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [3 x <8 x i8>], ptr [[ARR]], i64 0, i64 0206// CHECK-NEXT: store ptr [[ARRAYIDX]], ptr [[PARR]], align 8207// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PARR]], align 8208// CHECK-NEXT: [[TMP1:%.*]] = load <8 x i8>, ptr [[TMP0]], align 8209// CHECK-NEXT: store <8 x i8> [[TMP1]], ptr [[RETVAL]], align 8210// CHECK-NEXT: [[TMP2:%.*]] = load <8 x i8>, ptr [[RETVAL]], align 8211// CHECK-NEXT: [[CAST_SCALABLE:%.*]] = call <vscale x 2 x i8> @llvm.vector.insert.nxv2i8.v8i8(<vscale x 2 x i8> poison, <8 x i8> [[TMP2]], i64 0)212// CHECK-NEXT: [[TMP3:%.*]] = bitcast <vscale x 2 x i8> [[CAST_SCALABLE]] to <vscale x 16 x i1>213// CHECK-NEXT: ret <vscale x 16 x i1> [[TMP3]]214//215fixed_bool4_t address_of_array_idx_bool4() {216 fixed_bool4_t arr[3];217 fixed_bool4_t *parr;218 parr = &arr[0];219 return *parr;220}221 222// CHECK-LABEL: @address_of_array_idx_bool32(223// CHECK-NEXT: entry:224// CHECK-NEXT: [[RETVAL:%.*]] = alloca <1 x i8>, align 1225// CHECK-NEXT: [[ARR:%.*]] = alloca [3 x <1 x i8>], align 1226// CHECK-NEXT: [[PARR:%.*]] = alloca ptr, align 8227// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [3 x <1 x i8>], ptr [[ARR]], i64 0, i64 0228// CHECK-NEXT: store ptr [[ARRAYIDX]], ptr [[PARR]], align 8229// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PARR]], align 8230// CHECK-NEXT: [[TMP1:%.*]] = load <1 x i8>, ptr [[TMP0]], align 1231// CHECK-NEXT: store <1 x i8> [[TMP1]], ptr [[RETVAL]], align 1232// CHECK-NEXT: [[TMP2:%.*]] = load <1 x i8>, ptr [[RETVAL]], align 1233// CHECK-NEXT: [[CAST_SCALABLE:%.*]] = call <vscale x 1 x i8> @llvm.vector.insert.nxv1i8.v1i8(<vscale x 1 x i8> poison, <1 x i8> [[TMP2]], i64 0)234// CHECK-NEXT: [[TMP3:%.*]] = bitcast <vscale x 1 x i8> [[CAST_SCALABLE]] to <vscale x 8 x i1>235// CHECK-NEXT: [[TMP4:%.*]] = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv8i1(<vscale x 8 x i1> [[TMP3]], i64 0)236// CHECK-NEXT: ret <vscale x 2 x i1> [[TMP4]]237//238fixed_bool32_t address_of_array_idx_bool32() {239 fixed_bool32_t arr[3];240 fixed_bool32_t *parr;241 parr = &arr[0];242 return *parr;243}244 245// CHECK-LABEL: @test_cast(246// CHECK-NEXT: entry:247// CHECK-NEXT: [[RETVAL:%.*]] = alloca <8 x i32>, align 8248// CHECK-NEXT: [[VEC_ADDR:%.*]] = alloca <vscale x 2 x i32>, align 4249// CHECK-NEXT: store <vscale x 2 x i32> [[VEC:%.*]], ptr [[VEC_ADDR]], align 4250// CHECK-NEXT: [[TMP0:%.*]] = load <8 x i32>, ptr @global_vec, align 8251// CHECK-NEXT: [[CAST_SCALABLE:%.*]] = call <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32> poison, <8 x i32> [[TMP0]], i64 0)252// CHECK-NEXT: [[TMP1:%.*]] = load <vscale x 2 x i32>, ptr [[VEC_ADDR]], align 4253// CHECK-NEXT: [[TMP2:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vadd.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> [[CAST_SCALABLE]], <vscale x 2 x i32> [[TMP1]], i64 8)254// CHECK-NEXT: [[CAST_FIXED:%.*]] = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> [[TMP2]], i64 0)255// CHECK-NEXT: store <8 x i32> [[CAST_FIXED]], ptr [[RETVAL]], align 8256// CHECK-NEXT: [[TMP3:%.*]] = load <8 x i32>, ptr [[RETVAL]], align 8257// CHECK-NEXT: [[CAST_SCALABLE1:%.*]] = call <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32> poison, <8 x i32> [[TMP3]], i64 0)258// CHECK-NEXT: ret <vscale x 2 x i32> [[CAST_SCALABLE1]]259//260fixed_int32m1_t test_cast(vint32m1_t vec) {261 return __riscv_vadd(global_vec, vec, __riscv_v_fixed_vlen/32);262}263 264// CHECK-LABEL: @test_ptr_to_global_m2(265// CHECK-NEXT: entry:266// CHECK-NEXT: [[RETVAL:%.*]] = alloca <16 x i32>, align 8267// CHECK-NEXT: [[GLOBAL_VEC_PTR:%.*]] = alloca ptr, align 8268// CHECK-NEXT: store ptr @global_vec_m2, ptr [[GLOBAL_VEC_PTR]], align 8269// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[GLOBAL_VEC_PTR]], align 8270// CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr [[TMP0]], align 8271// CHECK-NEXT: store <16 x i32> [[TMP1]], ptr [[RETVAL]], align 8272// CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr [[RETVAL]], align 8273// CHECK-NEXT: [[CAST_SCALABLE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> poison, <16 x i32> [[TMP2]], i64 0)274// CHECK-NEXT: ret <vscale x 4 x i32> [[CAST_SCALABLE]]275//276fixed_int32m2_t test_ptr_to_global_m2() {277 fixed_int32m2_t *global_vec_ptr;278 global_vec_ptr = &global_vec_m2;279 return *global_vec_ptr;280}281 282//283// Test casting pointer from fixed-length array to scalable vector.284// CHECK-LABEL: @array_arg_m2(285// CHECK-NEXT: entry:286// CHECK-NEXT: [[RETVAL:%.*]] = alloca <16 x i32>, align 8287// CHECK-NEXT: [[ARR_ADDR:%.*]] = alloca ptr, align 8288// CHECK-NEXT: store ptr [[ARR:%.*]], ptr [[ARR_ADDR]], align 8289// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARR_ADDR]], align 8290// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds <16 x i32>, ptr [[TMP0]], i64 0291// CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr [[ARRAYIDX]], align 8292// CHECK-NEXT: store <16 x i32> [[TMP1]], ptr [[RETVAL]], align 8293// CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr [[RETVAL]], align 8294// CHECK-NEXT: [[CAST_SCALABLE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> poison, <16 x i32> [[TMP2]], i64 0)295// CHECK-NEXT: ret <vscale x 4 x i32> [[CAST_SCALABLE]]296//297fixed_int32m2_t array_arg_m2(fixed_int32m2_t arr[]) {298 return arr[0];299}300 301// CHECK-LABEL: @test_cast_m2(302// CHECK-NEXT: entry:303// CHECK-NEXT: [[RETVAL:%.*]] = alloca <16 x i32>, align 8304// CHECK-NEXT: [[VEC_ADDR:%.*]] = alloca <vscale x 4 x i32>, align 4305// CHECK-NEXT: store <vscale x 4 x i32> [[VEC:%.*]], ptr [[VEC_ADDR]], align 4306// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i32>, ptr @global_vec_m2, align 8307// CHECK-NEXT: [[CAST_SCALABLE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> poison, <16 x i32> [[TMP0]], i64 0)308// CHECK-NEXT: [[TMP1:%.*]] = load <vscale x 4 x i32>, ptr [[VEC_ADDR]], align 4309// CHECK-NEXT: [[TMP2:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> poison, <vscale x 4 x i32> [[CAST_SCALABLE]], <vscale x 4 x i32> [[TMP1]], i64 16)310// CHECK-NEXT: [[CAST_FIXED:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[TMP2]], i64 0)311// CHECK-NEXT: store <16 x i32> [[CAST_FIXED]], ptr [[RETVAL]], align 8312// CHECK-NEXT: [[TMP3:%.*]] = load <16 x i32>, ptr [[RETVAL]], align 8313// CHECK-NEXT: [[CAST_SCALABLE1:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> poison, <16 x i32> [[TMP3]], i64 0)314// CHECK-NEXT: ret <vscale x 4 x i32> [[CAST_SCALABLE1]]315//316fixed_int32m2_t test_cast_m2(vint32m2_t vec) {317 return __riscv_vadd(global_vec_m2, vec, __riscv_v_fixed_vlen/16);318}319