343 lines · c
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature2// RUN: %clang_cc1 -triple riscv64 -O2 -emit-llvm -o - %s | FileCheck %s --check-prefix=RISCV643// RUN: %clang_cc1 -triple riscv32 -O2 -emit-llvm -o - %s | FileCheck %s --check-prefix=RISCV324// RUN: %clang_cc1 -triple riscv32 -fforce-enable-int128 -O2 -emit-llvm -o - %s | FileCheck %s --check-prefix=RISCV32_INT1285 6// RISCV64-LABEL: define {{[^@]+}}@test_bitint_17_add_unsigned7// RISCV64-SAME: (i17 noundef zeroext [[A:%.*]], i17 noundef zeroext [[B:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] {8// RISCV64-NEXT: entry:9// RISCV64-NEXT: [[ADD:%.*]] = add i17 [[B]], [[A]]10// RISCV64-NEXT: ret i17 [[ADD]]11//12// RISCV32-LABEL: define {{[^@]+}}@test_bitint_17_add_unsigned13// RISCV32-SAME: (i17 noundef zeroext [[A:%.*]], i17 noundef zeroext [[B:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] {14// RISCV32-NEXT: entry:15// RISCV32-NEXT: [[ADD:%.*]] = add i17 [[B]], [[A]]16// RISCV32-NEXT: ret i17 [[ADD]]17//18// RISCV32_INT128-LABEL: define {{[^@]+}}@test_bitint_17_add_unsigned19// RISCV32_INT128-SAME: (i17 noundef zeroext [[A:%.*]], i17 noundef zeroext [[B:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] {20// RISCV32_INT128-NEXT: entry:21// RISCV32_INT128-NEXT: [[ADD:%.*]] = add i17 [[B]], [[A]]22// RISCV32_INT128-NEXT: ret i17 [[ADD]]23//24unsigned _BitInt(17) test_bitint_17_add_unsigned(unsigned _BitInt(17) a, unsigned _BitInt(17) b) {25 return a + b;26}27 28// RISCV64-LABEL: define {{[^@]+}}@test_bitint_17_add_signed29// RISCV64-SAME: (i17 noundef signext [[A:%.*]], i17 noundef signext [[B:%.*]]) local_unnamed_addr #[[ATTR0]] {30// RISCV64-NEXT: entry:31// RISCV64-NEXT: [[ADD:%.*]] = add nsw i17 [[B]], [[A]]32// RISCV64-NEXT: ret i17 [[ADD]]33//34// RISCV32-LABEL: define {{[^@]+}}@test_bitint_17_add_signed35// RISCV32-SAME: (i17 noundef signext [[A:%.*]], i17 noundef signext [[B:%.*]]) local_unnamed_addr #[[ATTR0]] {36// RISCV32-NEXT: entry:37// RISCV32-NEXT: [[ADD:%.*]] = add nsw i17 [[B]], [[A]]38// RISCV32-NEXT: ret i17 [[ADD]]39//40// RISCV32_INT128-LABEL: define {{[^@]+}}@test_bitint_17_add_signed41// RISCV32_INT128-SAME: (i17 noundef signext [[A:%.*]], i17 noundef signext [[B:%.*]]) local_unnamed_addr #[[ATTR0]] {42// RISCV32_INT128-NEXT: entry:43// RISCV32_INT128-NEXT: [[ADD:%.*]] = add nsw i17 [[B]], [[A]]44// RISCV32_INT128-NEXT: ret i17 [[ADD]]45//46signed _BitInt(17) test_bitint_17_add_signed(signed _BitInt(17) a, signed _BitInt(17) b) {47 return a + b;48}49 50// RISCV64-LABEL: define {{[^@]+}}@test_bitint_17_add_default51// RISCV64-SAME: (i17 noundef signext [[A:%.*]], i17 noundef signext [[B:%.*]]) local_unnamed_addr #[[ATTR0]] {52// RISCV64-NEXT: entry:53// RISCV64-NEXT: [[ADD:%.*]] = add nsw i17 [[B]], [[A]]54// RISCV64-NEXT: ret i17 [[ADD]]55//56// RISCV32-LABEL: define {{[^@]+}}@test_bitint_17_add_default57// RISCV32-SAME: (i17 noundef signext [[A:%.*]], i17 noundef signext [[B:%.*]]) local_unnamed_addr #[[ATTR0]] {58// RISCV32-NEXT: entry:59// RISCV32-NEXT: [[ADD:%.*]] = add nsw i17 [[B]], [[A]]60// RISCV32-NEXT: ret i17 [[ADD]]61//62// RISCV32_INT128-LABEL: define {{[^@]+}}@test_bitint_17_add_default63// RISCV32_INT128-SAME: (i17 noundef signext [[A:%.*]], i17 noundef signext [[B:%.*]]) local_unnamed_addr #[[ATTR0]] {64// RISCV32_INT128-NEXT: entry:65// RISCV32_INT128-NEXT: [[ADD:%.*]] = add nsw i17 [[B]], [[A]]66// RISCV32_INT128-NEXT: ret i17 [[ADD]]67//68_BitInt(17) test_bitint_17_add_default(_BitInt(17) a, _BitInt(17) b) {69 return a + b;70}71 72// RISCV64-LABEL: define {{[^@]+}}@test_bitint_32_add_unsigned73// RISCV64-SAME: (i32 noundef signext [[A:%.*]], i32 noundef signext [[B:%.*]]) local_unnamed_addr #[[ATTR0]] {74// RISCV64-NEXT: entry:75// RISCV64-NEXT: [[ADD:%.*]] = add i32 [[B]], [[A]]76// RISCV64-NEXT: ret i32 [[ADD]]77//78// RISCV32-LABEL: define {{[^@]+}}@test_bitint_32_add_unsigned79// RISCV32-SAME: (i32 noundef zeroext [[A:%.*]], i32 noundef zeroext [[B:%.*]]) local_unnamed_addr #[[ATTR0]] {80// RISCV32-NEXT: entry:81// RISCV32-NEXT: [[ADD:%.*]] = add i32 [[B]], [[A]]82// RISCV32-NEXT: ret i32 [[ADD]]83//84// RISCV32_INT128-LABEL: define {{[^@]+}}@test_bitint_32_add_unsigned85// RISCV32_INT128-SAME: (i32 noundef zeroext [[A:%.*]], i32 noundef zeroext [[B:%.*]]) local_unnamed_addr #[[ATTR0]] {86// RISCV32_INT128-NEXT: entry:87// RISCV32_INT128-NEXT: [[ADD:%.*]] = add i32 [[B]], [[A]]88// RISCV32_INT128-NEXT: ret i32 [[ADD]]89//90unsigned _BitInt(32) test_bitint_32_add_unsigned(unsigned _BitInt(32) a, unsigned _BitInt(32) b) {91 return a + b;92}93 94// RISCV64-LABEL: define {{[^@]+}}@test_bitint_32_add_signed95// RISCV64-SAME: (i32 noundef signext [[A:%.*]], i32 noundef signext [[B:%.*]]) local_unnamed_addr #[[ATTR0]] {96// RISCV64-NEXT: entry:97// RISCV64-NEXT: [[ADD:%.*]] = add nsw i32 [[B]], [[A]]98// RISCV64-NEXT: ret i32 [[ADD]]99//100// RISCV32-LABEL: define {{[^@]+}}@test_bitint_32_add_signed101// RISCV32-SAME: (i32 noundef signext [[A:%.*]], i32 noundef signext [[B:%.*]]) local_unnamed_addr #[[ATTR0]] {102// RISCV32-NEXT: entry:103// RISCV32-NEXT: [[ADD:%.*]] = add nsw i32 [[B]], [[A]]104// RISCV32-NEXT: ret i32 [[ADD]]105//106// RISCV32_INT128-LABEL: define {{[^@]+}}@test_bitint_32_add_signed107// RISCV32_INT128-SAME: (i32 noundef signext [[A:%.*]], i32 noundef signext [[B:%.*]]) local_unnamed_addr #[[ATTR0]] {108// RISCV32_INT128-NEXT: entry:109// RISCV32_INT128-NEXT: [[ADD:%.*]] = add nsw i32 [[B]], [[A]]110// RISCV32_INT128-NEXT: ret i32 [[ADD]]111//112signed _BitInt(32) test_bitint_32_add_signed(signed _BitInt(32) a, signed _BitInt(32) b) {113 return a + b;114}115 116// RISCV64-LABEL: define {{[^@]+}}@test_bitint_32_add_default117// RISCV64-SAME: (i32 noundef signext [[A:%.*]], i32 noundef signext [[B:%.*]]) local_unnamed_addr #[[ATTR0]] {118// RISCV64-NEXT: entry:119// RISCV64-NEXT: [[ADD:%.*]] = add nsw i32 [[B]], [[A]]120// RISCV64-NEXT: ret i32 [[ADD]]121//122// RISCV32-LABEL: define {{[^@]+}}@test_bitint_32_add_default123// RISCV32-SAME: (i32 noundef signext [[A:%.*]], i32 noundef signext [[B:%.*]]) local_unnamed_addr #[[ATTR0]] {124// RISCV32-NEXT: entry:125// RISCV32-NEXT: [[ADD:%.*]] = add nsw i32 [[B]], [[A]]126// RISCV32-NEXT: ret i32 [[ADD]]127//128// RISCV32_INT128-LABEL: define {{[^@]+}}@test_bitint_32_add_default129// RISCV32_INT128-SAME: (i32 noundef signext [[A:%.*]], i32 noundef signext [[B:%.*]]) local_unnamed_addr #[[ATTR0]] {130// RISCV32_INT128-NEXT: entry:131// RISCV32_INT128-NEXT: [[ADD:%.*]] = add nsw i32 [[B]], [[A]]132// RISCV32_INT128-NEXT: ret i32 [[ADD]]133//134_BitInt(32) test_bitint_32_add_default(_BitInt(32) a, _BitInt(32) b) {135 return a + b;136}137 138 139// RISCV64-LABEL: define {{[^@]+}}@test_bitint_65_add_unsigned140// RISCV64-SAME: (i65 noundef zeroext [[A:%.*]], i65 noundef zeroext [[B:%.*]]) local_unnamed_addr #[[ATTR0]] {141// RISCV64-NEXT: entry:142// RISCV64-NEXT: [[ADD:%.*]] = add i65 [[B]], [[A]]143// RISCV64-NEXT: ret i65 [[ADD]]144//145// RISCV32-LABEL: define {{[^@]+}}@test_bitint_65_add_unsigned146// RISCV32-SAME: (ptr dead_on_unwind noalias writable writeonly sret(i128) align 8 captures(none) initializes((0, 16)) [[AGG_RESULT:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP0:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP1:%.*]]) local_unnamed_addr #[[ATTR1:[0-9]+]] {147// RISCV32-NEXT: entry:148// RISCV32-NEXT: [[TMP2:%.*]] = load i128, ptr [[TMP0]], align 8, !tbaa [[TBAA6:![0-9]+]]149// RISCV32-NEXT: [[A:%.*]] = trunc i128 [[TMP2]] to i65150// RISCV32-NEXT: [[TMP3:%.*]] = load i128, ptr [[TMP1]], align 8, !tbaa [[TBAA6]]151// RISCV32-NEXT: [[B:%.*]] = trunc i128 [[TMP3]] to i65152// RISCV32-NEXT: [[ADD:%.*]] = add i65 [[B]], [[A]]153// RISCV32-NEXT: [[STOREDV4:%.*]] = zext i65 [[ADD]] to i128154// RISCV32-NEXT: store i128 [[STOREDV4]], ptr [[AGG_RESULT]], align 8, !tbaa [[TBAA6]]155// RISCV32-NEXT: ret void156//157// RISCV32_INT128-LABEL: define {{[^@]+}}@test_bitint_65_add_unsigned158// RISCV32_INT128-SAME: (ptr dead_on_unwind noalias writable writeonly sret(i128) align 8 captures(none) initializes((0, 16)) [[AGG_RESULT:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP0:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP1:%.*]]) local_unnamed_addr #[[ATTR1:[0-9]+]] {159// RISCV32_INT128-NEXT: entry:160// RISCV32_INT128-NEXT: [[TMP2:%.*]] = load i128, ptr [[TMP0]], align 8, !tbaa [[TBAA6:![0-9]+]]161// RISCV32_INT128-NEXT: [[A:%.*]] = trunc i128 [[TMP2]] to i65162// RISCV32_INT128-NEXT: [[TMP3:%.*]] = load i128, ptr [[TMP1]], align 8, !tbaa [[TBAA6]]163// RISCV32_INT128-NEXT: [[B:%.*]] = trunc i128 [[TMP3]] to i65164// RISCV32_INT128-NEXT: [[ADD:%.*]] = add i65 [[B]], [[A]]165// RISCV32_INT128-NEXT: [[STOREDV4:%.*]] = zext i65 [[ADD]] to i128166// RISCV32_INT128-NEXT: store i128 [[STOREDV4]], ptr [[AGG_RESULT]], align 8, !tbaa [[TBAA6]]167// RISCV32_INT128-NEXT: ret void168//169unsigned _BitInt(65) test_bitint_65_add_unsigned(unsigned _BitInt(65) a, unsigned _BitInt(65) b) {170 return a + b;171}172 173// RISCV64-LABEL: define {{[^@]+}}@test_bitint_65_add_signed174// RISCV64-SAME: (i65 noundef signext [[A:%.*]], i65 noundef signext [[B:%.*]]) local_unnamed_addr #[[ATTR0]] {175// RISCV64-NEXT: entry:176// RISCV64-NEXT: [[ADD:%.*]] = add nsw i65 [[B]], [[A]]177// RISCV64-NEXT: ret i65 [[ADD]]178//179// RISCV32-LABEL: define {{[^@]+}}@test_bitint_65_add_signed180// RISCV32-SAME: (ptr dead_on_unwind noalias writable writeonly sret(i128) align 8 captures(none) initializes((0, 16)) [[AGG_RESULT:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP0:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP1:%.*]]) local_unnamed_addr #[[ATTR1]] {181// RISCV32-NEXT: entry:182// RISCV32-NEXT: [[TMP2:%.*]] = load i128, ptr [[TMP0]], align 8, !tbaa [[TBAA6]]183// RISCV32-NEXT: [[A:%.*]] = trunc i128 [[TMP2]] to i65184// RISCV32-NEXT: [[TMP3:%.*]] = load i128, ptr [[TMP1]], align 8, !tbaa [[TBAA6]]185// RISCV32-NEXT: [[B:%.*]] = trunc i128 [[TMP3]] to i65186// RISCV32-NEXT: [[ADD:%.*]] = add nsw i65 [[B]], [[A]]187// RISCV32-NEXT: [[STOREDV4:%.*]] = sext i65 [[ADD]] to i128188// RISCV32-NEXT: store i128 [[STOREDV4]], ptr [[AGG_RESULT]], align 8, !tbaa [[TBAA6]]189// RISCV32-NEXT: ret void190//191// RISCV32_INT128-LABEL: define {{[^@]+}}@test_bitint_65_add_signed192// RISCV32_INT128-SAME: (ptr dead_on_unwind noalias writable writeonly sret(i128) align 8 captures(none) initializes((0, 16)) [[AGG_RESULT:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP0:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP1:%.*]]) local_unnamed_addr #[[ATTR1]] {193// RISCV32_INT128-NEXT: entry:194// RISCV32_INT128-NEXT: [[TMP2:%.*]] = load i128, ptr [[TMP0]], align 8, !tbaa [[TBAA6]]195// RISCV32_INT128-NEXT: [[A:%.*]] = trunc i128 [[TMP2]] to i65196// RISCV32_INT128-NEXT: [[TMP3:%.*]] = load i128, ptr [[TMP1]], align 8, !tbaa [[TBAA6]]197// RISCV32_INT128-NEXT: [[B:%.*]] = trunc i128 [[TMP3]] to i65198// RISCV32_INT128-NEXT: [[ADD:%.*]] = add nsw i65 [[B]], [[A]]199// RISCV32_INT128-NEXT: [[STOREDV4:%.*]] = sext i65 [[ADD]] to i128200// RISCV32_INT128-NEXT: store i128 [[STOREDV4]], ptr [[AGG_RESULT]], align 8, !tbaa [[TBAA6]]201// RISCV32_INT128-NEXT: ret void202//203signed _BitInt(65) test_bitint_65_add_signed(signed _BitInt(65) a, signed _BitInt(65) b) {204 return a + b;205}206 207// RISCV64-LABEL: define {{[^@]+}}@test_bitint_65_add_default208// RISCV64-SAME: (i65 noundef signext [[A:%.*]], i65 noundef signext [[B:%.*]]) local_unnamed_addr #[[ATTR0]] {209// RISCV64-NEXT: entry:210// RISCV64-NEXT: [[ADD:%.*]] = add nsw i65 [[B]], [[A]]211// RISCV64-NEXT: ret i65 [[ADD]]212//213// RISCV32-LABEL: define {{[^@]+}}@test_bitint_65_add_default214// RISCV32-SAME: (ptr dead_on_unwind noalias writable writeonly sret(i128) align 8 captures(none) initializes((0, 16)) [[AGG_RESULT:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP0:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP1:%.*]]) local_unnamed_addr #[[ATTR1]] {215// RISCV32-NEXT: entry:216// RISCV32-NEXT: [[TMP2:%.*]] = load i128, ptr [[TMP0]], align 8, !tbaa [[TBAA6]]217// RISCV32-NEXT: [[A:%.*]] = trunc i128 [[TMP2]] to i65218// RISCV32-NEXT: [[TMP3:%.*]] = load i128, ptr [[TMP1]], align 8, !tbaa [[TBAA6]]219// RISCV32-NEXT: [[B:%.*]] = trunc i128 [[TMP3]] to i65220// RISCV32-NEXT: [[ADD:%.*]] = add nsw i65 [[B]], [[A]]221// RISCV32-NEXT: [[STOREDV4:%.*]] = sext i65 [[ADD]] to i128222// RISCV32-NEXT: store i128 [[STOREDV4]], ptr [[AGG_RESULT]], align 8, !tbaa [[TBAA6]]223// RISCV32-NEXT: ret void224//225// RISCV32_INT128-LABEL: define {{[^@]+}}@test_bitint_65_add_default226// RISCV32_INT128-SAME: (ptr dead_on_unwind noalias writable writeonly sret(i128) align 8 captures(none) initializes((0, 16)) [[AGG_RESULT:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP0:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP1:%.*]]) local_unnamed_addr #[[ATTR1]] {227// RISCV32_INT128-NEXT: entry:228// RISCV32_INT128-NEXT: [[TMP2:%.*]] = load i128, ptr [[TMP0]], align 8, !tbaa [[TBAA6]]229// RISCV32_INT128-NEXT: [[A:%.*]] = trunc i128 [[TMP2]] to i65230// RISCV32_INT128-NEXT: [[TMP3:%.*]] = load i128, ptr [[TMP1]], align 8, !tbaa [[TBAA6]]231// RISCV32_INT128-NEXT: [[B:%.*]] = trunc i128 [[TMP3]] to i65232// RISCV32_INT128-NEXT: [[ADD:%.*]] = add nsw i65 [[B]], [[A]]233// RISCV32_INT128-NEXT: [[STOREDV4:%.*]] = sext i65 [[ADD]] to i128234// RISCV32_INT128-NEXT: store i128 [[STOREDV4]], ptr [[AGG_RESULT]], align 8, !tbaa [[TBAA6]]235// RISCV32_INT128-NEXT: ret void236//237_BitInt(65) test_bitint_65_add_default(_BitInt(65) a, _BitInt(65) b) {238 return a + b;239}240 241 242// RISCV64-LABEL: define {{[^@]+}}@test_bitint_77_add_unsigned243// RISCV64-SAME: (i77 noundef zeroext [[A:%.*]], i77 noundef zeroext [[B:%.*]]) local_unnamed_addr #[[ATTR0]] {244// RISCV64-NEXT: entry:245// RISCV64-NEXT: [[ADD:%.*]] = add i77 [[B]], [[A]]246// RISCV64-NEXT: ret i77 [[ADD]]247//248// RISCV32-LABEL: define {{[^@]+}}@test_bitint_77_add_unsigned249// RISCV32-SAME: (ptr dead_on_unwind noalias writable writeonly sret(i128) align 8 captures(none) initializes((0, 16)) [[AGG_RESULT:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP0:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP1:%.*]]) local_unnamed_addr #[[ATTR1]] {250// RISCV32-NEXT: entry:251// RISCV32-NEXT: [[TMP2:%.*]] = load i128, ptr [[TMP0]], align 8, !tbaa [[TBAA10:![0-9]+]]252// RISCV32-NEXT: [[A:%.*]] = trunc i128 [[TMP2]] to i77253// RISCV32-NEXT: [[TMP3:%.*]] = load i128, ptr [[TMP1]], align 8, !tbaa [[TBAA10]]254// RISCV32-NEXT: [[B:%.*]] = trunc i128 [[TMP3]] to i77255// RISCV32-NEXT: [[ADD:%.*]] = add i77 [[B]], [[A]]256// RISCV32-NEXT: [[STOREDV4:%.*]] = zext i77 [[ADD]] to i128257// RISCV32-NEXT: store i128 [[STOREDV4]], ptr [[AGG_RESULT]], align 8, !tbaa [[TBAA10]]258// RISCV32-NEXT: ret void259//260// RISCV32_INT128-LABEL: define {{[^@]+}}@test_bitint_77_add_unsigned261// RISCV32_INT128-SAME: (ptr dead_on_unwind noalias writable writeonly sret(i128) align 8 captures(none) initializes((0, 16)) [[AGG_RESULT:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP0:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP1:%.*]]) local_unnamed_addr #[[ATTR1]] {262// RISCV32_INT128-NEXT: entry:263// RISCV32_INT128-NEXT: [[TMP2:%.*]] = load i128, ptr [[TMP0]], align 8, !tbaa [[TBAA10:![0-9]+]]264// RISCV32_INT128-NEXT: [[A:%.*]] = trunc i128 [[TMP2]] to i77265// RISCV32_INT128-NEXT: [[TMP3:%.*]] = load i128, ptr [[TMP1]], align 8, !tbaa [[TBAA10]]266// RISCV32_INT128-NEXT: [[B:%.*]] = trunc i128 [[TMP3]] to i77267// RISCV32_INT128-NEXT: [[ADD:%.*]] = add i77 [[B]], [[A]]268// RISCV32_INT128-NEXT: [[STOREDV4:%.*]] = zext i77 [[ADD]] to i128269// RISCV32_INT128-NEXT: store i128 [[STOREDV4]], ptr [[AGG_RESULT]], align 8, !tbaa [[TBAA10]]270// RISCV32_INT128-NEXT: ret void271//272unsigned _BitInt(77) test_bitint_77_add_unsigned(unsigned _BitInt(77) a, unsigned _BitInt(77) b) {273 return a + b;274}275 276// RISCV64-LABEL: define {{[^@]+}}@test_bitint_77_add_signed277// RISCV64-SAME: (i77 noundef signext [[A:%.*]], i77 noundef signext [[B:%.*]]) local_unnamed_addr #[[ATTR0]] {278// RISCV64-NEXT: entry:279// RISCV64-NEXT: [[ADD:%.*]] = add nsw i77 [[B]], [[A]]280// RISCV64-NEXT: ret i77 [[ADD]]281//282// RISCV32-LABEL: define {{[^@]+}}@test_bitint_77_add_signed283// RISCV32-SAME: (ptr dead_on_unwind noalias writable writeonly sret(i128) align 8 captures(none) initializes((0, 16)) [[AGG_RESULT:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP0:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP1:%.*]]) local_unnamed_addr #[[ATTR1]] {284// RISCV32-NEXT: entry:285// RISCV32-NEXT: [[TMP2:%.*]] = load i128, ptr [[TMP0]], align 8, !tbaa [[TBAA10]]286// RISCV32-NEXT: [[A:%.*]] = trunc i128 [[TMP2]] to i77287// RISCV32-NEXT: [[TMP3:%.*]] = load i128, ptr [[TMP1]], align 8, !tbaa [[TBAA10]]288// RISCV32-NEXT: [[B:%.*]] = trunc i128 [[TMP3]] to i77289// RISCV32-NEXT: [[ADD:%.*]] = add nsw i77 [[B]], [[A]]290// RISCV32-NEXT: [[STOREDV4:%.*]] = sext i77 [[ADD]] to i128291// RISCV32-NEXT: store i128 [[STOREDV4]], ptr [[AGG_RESULT]], align 8, !tbaa [[TBAA10]]292// RISCV32-NEXT: ret void293//294// RISCV32_INT128-LABEL: define {{[^@]+}}@test_bitint_77_add_signed295// RISCV32_INT128-SAME: (ptr dead_on_unwind noalias writable writeonly sret(i128) align 8 captures(none) initializes((0, 16)) [[AGG_RESULT:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP0:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP1:%.*]]) local_unnamed_addr #[[ATTR1]] {296// RISCV32_INT128-NEXT: entry:297// RISCV32_INT128-NEXT: [[TMP2:%.*]] = load i128, ptr [[TMP0]], align 8, !tbaa [[TBAA10]]298// RISCV32_INT128-NEXT: [[A:%.*]] = trunc i128 [[TMP2]] to i77299// RISCV32_INT128-NEXT: [[TMP3:%.*]] = load i128, ptr [[TMP1]], align 8, !tbaa [[TBAA10]]300// RISCV32_INT128-NEXT: [[B:%.*]] = trunc i128 [[TMP3]] to i77301// RISCV32_INT128-NEXT: [[ADD:%.*]] = add nsw i77 [[B]], [[A]]302// RISCV32_INT128-NEXT: [[STOREDV4:%.*]] = sext i77 [[ADD]] to i128303// RISCV32_INT128-NEXT: store i128 [[STOREDV4]], ptr [[AGG_RESULT]], align 8, !tbaa [[TBAA10]]304// RISCV32_INT128-NEXT: ret void305//306signed _BitInt(77) test_bitint_77_add_signed(signed _BitInt(77) a, signed _BitInt(77) b) {307 return a + b;308}309 310// RISCV64-LABEL: define {{[^@]+}}@test_bitint_77_add_default311// RISCV64-SAME: (i77 noundef signext [[A:%.*]], i77 noundef signext [[B:%.*]]) local_unnamed_addr #[[ATTR0]] {312// RISCV64-NEXT: entry:313// RISCV64-NEXT: [[ADD:%.*]] = add nsw i77 [[B]], [[A]]314// RISCV64-NEXT: ret i77 [[ADD]]315//316// RISCV32-LABEL: define {{[^@]+}}@test_bitint_77_add_default317// RISCV32-SAME: (ptr dead_on_unwind noalias writable writeonly sret(i128) align 8 captures(none) initializes((0, 16)) [[AGG_RESULT:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP0:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP1:%.*]]) local_unnamed_addr #[[ATTR1]] {318// RISCV32-NEXT: entry:319// RISCV32-NEXT: [[TMP2:%.*]] = load i128, ptr [[TMP0]], align 8, !tbaa [[TBAA10]]320// RISCV32-NEXT: [[A:%.*]] = trunc i128 [[TMP2]] to i77321// RISCV32-NEXT: [[TMP3:%.*]] = load i128, ptr [[TMP1]], align 8, !tbaa [[TBAA10]]322// RISCV32-NEXT: [[B:%.*]] = trunc i128 [[TMP3]] to i77323// RISCV32-NEXT: [[ADD:%.*]] = add nsw i77 [[B]], [[A]]324// RISCV32-NEXT: [[STOREDV4:%.*]] = sext i77 [[ADD]] to i128325// RISCV32-NEXT: store i128 [[STOREDV4]], ptr [[AGG_RESULT]], align 8, !tbaa [[TBAA10]]326// RISCV32-NEXT: ret void327//328// RISCV32_INT128-LABEL: define {{[^@]+}}@test_bitint_77_add_default329// RISCV32_INT128-SAME: (ptr dead_on_unwind noalias writable writeonly sret(i128) align 8 captures(none) initializes((0, 16)) [[AGG_RESULT:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP0:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP1:%.*]]) local_unnamed_addr #[[ATTR1]] {330// RISCV32_INT128-NEXT: entry:331// RISCV32_INT128-NEXT: [[TMP2:%.*]] = load i128, ptr [[TMP0]], align 8, !tbaa [[TBAA10]]332// RISCV32_INT128-NEXT: [[A:%.*]] = trunc i128 [[TMP2]] to i77333// RISCV32_INT128-NEXT: [[TMP3:%.*]] = load i128, ptr [[TMP1]], align 8, !tbaa [[TBAA10]]334// RISCV32_INT128-NEXT: [[B:%.*]] = trunc i128 [[TMP3]] to i77335// RISCV32_INT128-NEXT: [[ADD:%.*]] = add nsw i77 [[B]], [[A]]336// RISCV32_INT128-NEXT: [[STOREDV4:%.*]] = sext i77 [[ADD]] to i128337// RISCV32_INT128-NEXT: store i128 [[STOREDV4]], ptr [[AGG_RESULT]], align 8, !tbaa [[TBAA10]]338// RISCV32_INT128-NEXT: ret void339//340_BitInt(77) test_bitint_77_add_default(_BitInt(77) a, _BitInt(77) b) {341 return a + b;342}343