58 lines · c
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 52// RUN: %clang_cc1 -triple riscv64-unknown-linux-gnu -disable-O0-optnone -emit-llvm %s -o - \3// RUN: | opt -S -passes=mem2reg | FileCheck %s --check-prefix=CHECK-RV644 5// CHECK-RV64-LABEL: define dso_local signext i32 @test_cpu_is_veyron_v1(6// CHECK-RV64-SAME: ) #[[ATTR0:[0-9]+]] {7// CHECK-RV64-NEXT: [[ENTRY:.*:]]8// CHECK-RV64-NEXT: [[TMP0:%.*]] = load i32, ptr @__riscv_cpu_model, align 49// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i32 [[TMP0]], 156710// CHECK-RV64-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr inbounds nuw ({ i32, i64, i64 }, ptr @__riscv_cpu_model, i32 0, i32 1), align 811// CHECK-RV64-NEXT: [[TMP3:%.*]] = icmp eq i64 [[TMP2]], -922337203685471027212// CHECK-RV64-NEXT: [[TMP4:%.*]] = and i1 [[TMP1]], [[TMP3]]13// CHECK-RV64-NEXT: [[TMP5:%.*]] = load i64, ptr getelementptr inbounds nuw ({ i32, i64, i64 }, ptr @__riscv_cpu_model, i32 0, i32 2), align 814// CHECK-RV64-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 27315// CHECK-RV64-NEXT: [[TMP7:%.*]] = and i1 [[TMP4]], [[TMP6]]16// CHECK-RV64-NEXT: [[CONV:%.*]] = zext i1 [[TMP7]] to i3217// CHECK-RV64-NEXT: ret i32 [[CONV]]18//19int test_cpu_is_veyron_v1() {20 return __builtin_cpu_is("veyron-v1");21}22 23// CHECK-RV64-LABEL: define dso_local signext i32 @test_cpu_is_spacemit_x60(24// CHECK-RV64-SAME: ) #[[ATTR0]] {25// CHECK-RV64-NEXT: [[ENTRY:.*:]]26// CHECK-RV64-NEXT: [[TMP0:%.*]] = load i32, ptr @__riscv_cpu_model, align 427// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i32 [[TMP0]], 180828// CHECK-RV64-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr inbounds nuw ({ i32, i64, i64 }, ptr @__riscv_cpu_model, i32 0, i32 1), align 829// CHECK-RV64-NEXT: [[TMP3:%.*]] = icmp eq i64 [[TMP2]], -922337203537838079930// CHECK-RV64-NEXT: [[TMP4:%.*]] = and i1 [[TMP1]], [[TMP3]]31// CHECK-RV64-NEXT: [[TMP5:%.*]] = load i64, ptr getelementptr inbounds nuw ({ i32, i64, i64 }, ptr @__riscv_cpu_model, i32 0, i32 2), align 832// CHECK-RV64-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 115292150583939123233// CHECK-RV64-NEXT: [[TMP7:%.*]] = and i1 [[TMP4]], [[TMP6]]34// CHECK-RV64-NEXT: [[CONV:%.*]] = zext i1 [[TMP7]] to i3235// CHECK-RV64-NEXT: ret i32 [[CONV]]36//37int test_cpu_is_spacemit_x60() {38 return __builtin_cpu_is("spacemit-x60");39}40 41// CHECK-RV64-LABEL: define dso_local signext i32 @test_cpu_is_sifive_p550(42// CHECK-RV64-SAME: ) #[[ATTR0]] {43// CHECK-RV64-NEXT: [[ENTRY:.*:]]44// CHECK-RV64-NEXT: [[TMP0:%.*]] = load i32, ptr @__riscv_cpu_model, align 445// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i32 [[TMP0]], 116146// CHECK-RV64-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr inbounds nuw ({ i32, i64, i64 }, ptr @__riscv_cpu_model, i32 0, i32 1), align 847// CHECK-RV64-NEXT: [[TMP3:%.*]] = icmp eq i64 [[TMP2]], -922337203685477580048// CHECK-RV64-NEXT: [[TMP4:%.*]] = and i1 [[TMP1]], [[TMP3]]49// CHECK-RV64-NEXT: [[TMP5:%.*]] = load i64, ptr getelementptr inbounds nuw ({ i32, i64, i64 }, ptr @__riscv_cpu_model, i32 0, i32 2), align 850// CHECK-RV64-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 10289258151// CHECK-RV64-NEXT: [[TMP7:%.*]] = and i1 [[TMP4]], [[TMP6]]52// CHECK-RV64-NEXT: [[CONV:%.*]] = zext i1 [[TMP7]] to i3253// CHECK-RV64-NEXT: ret i32 [[CONV]]54//55int test_cpu_is_sifive_p550() {56 return __builtin_cpu_is("sifive-p550");57}58