96 lines · c
1// REQUIRES: riscv-registered-target2// RUN: %clang_cc1 -triple riscv64 -target-feature +zifencei -target-feature +m \3// RUN: -target-feature +a -target-feature +save-restore -target-feature -zbb \4// RUN: -target-feature -relax -target-feature -zfa \5// RUN: -emit-llvm %s -o - | FileCheck %s6 7#include <riscv_vector.h>8 9// CHECK-LABEL: define dso_local void @testDefault10// CHECK-SAME: () #0 {11void testDefault() {}12// CHECK-LABEL: define dso_local void @testMultiAttrStr13// CHECK-SAME: () #1 {14__attribute__((target("cpu=rocket-rv64;tune=generic-rv64;arch=+v"))) void15testMultiAttrStr() {}16// CHECK-LABEL: define dso_local void @testSingleExtension17// CHECK-SAME: () #2 {18__attribute__((target("arch=+zbb"))) void testSingleExtension() {}19// CHECK-LABEL: define dso_local void @testMultiExtension20// CHECK-SAME: () #3 {21__attribute__((target("arch=+zbb,+v,+zicond"))) void testMultiExtension() {}22// CHECK-LABEL: define dso_local void @testFullArch23// CHECK-SAME: () #4 {24__attribute__((target("arch=rv64gc_zbb"))) void testFullArch() {}25// CHECK-LABEL: define dso_local void @testFullArchButSmallThanCmdArch26// CHECK-SAME: () #5 {27__attribute__((target("arch=rv64im"))) void testFullArchButSmallThanCmdArch() {}28// CHECK-LABEL: define dso_local void @testAttrArchAndAttrCpu29// CHECK-SAME: () #6 {30__attribute__((target("cpu=sifive-u54;arch=+zbb"))) void31testAttrArchAndAttrCpu() {}32// CHECK-LABEL: define dso_local void @testAttrFullArchAndAttrCpu33// CHECK-SAME: () #7 {34__attribute__((target("cpu=sifive-u54;arch=rv64im"))) void35testAttrFullArchAndAttrCpu() {}36// CHECK-LABEL: define dso_local void @testAttrCpuOnly37// CHECK-SAME: () #8 {38__attribute__((target("cpu=sifive-u54"))) void testAttrCpuOnly() {}39 40__attribute__((target("arch=+zve32x")))41void test_builtin_w_zve32x() {42// CHECK-LABEL: test_builtin_w_zve32x43// CHECK-SAME: #944 __riscv_vsetvl_e8m8(1);45}46 47__attribute__((target("arch=+zve32x")))48void test_rvv_i32_type_w_zve32x() {49// CHECK-LABEL: test_rvv_i32_type_w_zve32x50// CHECK-SAME: #951 vint32m1_t v;52}53 54__attribute__((target("arch=+zve32f")))55void test_rvv_f32_type_w_zve32f() {56// CHECK-LABEL: test_rvv_f32_type_w_zve32f57// CHECK-SAME: #1158 vfloat32m1_t v;59}60 61__attribute__((target("arch=+zve64d")))62void test_rvv_f64_type_w_zve64d() {63// CHECK-LABEL: test_rvv_f64_type_w_zve64d64// CHECK-SAME: #1265 vfloat64m1_t v;66}67 68__attribute__((target("arch=+v")))69int test_vsetvl_e64m1(unsigned avl) {70// CHECK-LABEL: test_vsetvl_e64m171// CHECK-SAME: #1372 return __riscv_vsetvl_e64m1(avl);73}74 75__attribute__((target("arch=+v")))76int test_vsetvlmax_e64m1() {77// CHECK-LABEL: test_vsetvlmax_e64m178// CHECK-SAME: #1379 return __riscv_vsetvlmax_e64m1();80}81 82//.83// CHECK: attributes #0 = { {{.*}}"target-features"="+64bit,+a,+i,+m,+save-restore,+zaamo,+zalrsc,+zifencei,+zmmul,-relax,-zbb,-zfa" }84// CHECK: attributes #1 = { {{.*}}"target-cpu"="rocket-rv64" "target-features"="+64bit,+a,+d,+f,+i,+m,+save-restore,+v,+zaamo,+zalrsc,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-relax,-zbb,-zfa" "tune-cpu"="generic-rv64" }85// CHECK: attributes #2 = { {{.*}}"target-features"="+64bit,+a,+i,+m,+save-restore,+zaamo,+zalrsc,+zbb,+zifencei,+zmmul,-relax,-zfa" }86// CHECK: attributes #3 = { {{.*}}"target-features"="+64bit,+a,+d,+f,+i,+m,+save-restore,+v,+zaamo,+zalrsc,+zbb,+zicond,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-relax,-zfa" }87// Make sure we append negative features if we override the arch88// CHECK: attributes #4 = { {{.*}}"target-features"="+64bit,+a,+c,+d,+f,+i,+m,+save-restore,+zaamo,+zalrsc,+zbb,+zca,+zcd,+zicsr,+zifencei,+zmmul,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}" }89// CHECK: attributes #5 = { {{.*}}"target-features"="+64bit,+i,+m,+save-restore,+zmmul,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}" }90// CHECK: attributes #6 = { {{.*}}"target-cpu"="sifive-u54" "target-features"="+64bit,+a,+i,+m,+save-restore,+zaamo,+zalrsc,+zbb,+zifencei,+zmmul,-relax,-zfa" }91// CHECK: attributes #7 = { {{.*}}"target-cpu"="sifive-u54" "target-features"="+64bit,+i,+m,+save-restore,+zmmul,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}" }92// CHECK: attributes #8 = { {{.*}}"target-cpu"="sifive-u54" "target-features"="+64bit,+a,+c,+d,+f,+i,+m,+save-restore,+zaamo,+zalrsc,+zca,+zcd,+zicsr,+zifencei,+zmmul,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}" }93// CHECK: attributes #9 = { {{.*}}"target-features"="+64bit,+a,+i,+m,+save-restore,+zaamo,+zalrsc,+zicsr,+zifencei,+zmmul,+zve32x,+zvl32b,-relax,-zbb,-zfa" }94// CHECK: attributes #11 = { {{.*}}"target-features"="+64bit,+a,+f,+i,+m,+save-restore,+zaamo,+zalrsc,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zvl32b,-relax,-zbb,-zfa" }95// CHECK: attributes #12 = { {{.*}}"target-features"="+64bit,+a,+d,+f,+i,+m,+save-restore,+zaamo,+zalrsc,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl32b,+zvl64b,-relax,-zbb,-zfa" }96