45 lines · c
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 32// REQUIRES: riscv-registered-target3// RUN: %clang_cc1 -triple riscv32 -O2 -emit-llvm %s -o - \4// RUN: | FileCheck %s5// RUN: %clang_cc1 -triple riscv64 -O2 -emit-llvm %s -o - \6// RUN: | FileCheck %s7 8// Test RISC-V specific clobbered registers in inline assembly.9 10// CHECK-LABEL: define {{.*}} void @test_fflags11// CHECK: tail call void asm sideeffect "", "~{fflags}"()12void test_fflags(void) {13 asm volatile ("" :::"fflags");14}15 16// CHECK-LABEL: define {{.*}} void @test_frm17// CHECK: tail call void asm sideeffect "", "~{frm}"()18void test_frm(void) {19 asm volatile ("" :::"frm");20}21 22// CHECK-LABEL: define {{.*}} void @test_vtype23// CHECK: tail call void asm sideeffect "", "~{vtype}"()24void test_vtype(void) {25 asm volatile ("" :::"vtype");26}27 28// CHECK-LABEL: define {{.*}} void @test_vl29// CHECK: tail call void asm sideeffect "", "~{vl}"()30void test_vl(void) {31 asm volatile ("" :::"vl");32}33 34// CHECK-LABEL: define {{.*}} void @test_vxsat35// CHECK: tail call void asm sideeffect "", "~{vxsat}"()36void test_vxsat(void) {37 asm volatile ("" :::"vxsat");38}39 40// CHECK-LABEL: define {{.*}} void @test_vxrm41// CHECK: tail call void asm sideeffect "", "~{vxrm}"()42void test_vxrm(void) {43 asm volatile ("" :::"vxrm");44}45