22 lines · cpp
1// REQUIRES: riscv-registered-target2// RUN: %clang_cc1 -std=c++11 -triple riscv64 -target-feature +v \3// RUN: -O1 -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s4 5#include <riscv_vector.h>6 7vint32m1_t Baz();8 9// CHECK-LABEL: @_Z4Testv(10// CHECK-NEXT: entry:11// CHECK-NEXT: [[A:%.*]] = alloca ptr, align 812// CHECK-NEXT: [[REF_TMP:%.*]] = alloca <vscale x 2 x i32>, align 413// CHECK-NEXT: call void @llvm.lifetime.start.p0(ptr [[A]]) #[[ATTR3:[0-9]+]]14// CHECK-NEXT: call void @llvm.lifetime.start.p0(ptr [[REF_TMP]]) #[[ATTR3]]15// CHECK: call void @llvm.lifetime.end.p0(ptr [[REF_TMP]]) #[[ATTR3]]16// CHECK-NEXT: call void @llvm.lifetime.end.p0(ptr [[A]]) #[[ATTR3]]17//18vint32m1_t Test() {19 const vint32m1_t &a = Baz();20 return a;21}22