175 lines · cpp
1// REQUIRES: riscv-registered-target2// RUN: %clang_cc1 -std=c++11 -triple riscv64 -target-feature +v \3// RUN: -emit-llvm %s -o - | FileCheck -check-prefix=CHECK-LLVM %s4// RUN: %clang_cc1 -std=c++11 -triple riscv64 -target-feature +zve32x \5// RUN: -emit-llvm %s -o - | FileCheck -check-prefix=CHECK-LLVM-ZVE32X %s6 7#include <riscv_vector.h>8 9// CHECK-LLVM: call riscv_vector_cc <vscale x 2 x i32> @_Z3baru15__rvv_int32m1_t10vint32m1_t __attribute__((riscv_vector_cc)) bar(vint32m1_t input);11vint32m1_t test_vector_cc_attr(vint32m1_t input, int32_t *base, size_t vl) {12 vint32m1_t val = __riscv_vle32_v_i32m1(base, vl);13 vint32m1_t ret = bar(input);14 __riscv_vse32_v_i32m1(base, val, vl);15 return ret;16}17 18// CHECK-LLVM: call riscv_vector_cc <vscale x 2 x i32> @_Z3baru15__rvv_int32m1_t19[[riscv::vector_cc]] vint32m1_t bar(vint32m1_t input);20vint32m1_t test_vector_cc_attr2(vint32m1_t input, int32_t *base, size_t vl) {21 vint32m1_t val = __riscv_vle32_v_i32m1(base, vl);22 vint32m1_t ret = bar(input);23 __riscv_vse32_v_i32m1(base, val, vl);24 return ret;25}26 27// CHECK-LLVM: call <vscale x 2 x i32> @_Z3bazu15__rvv_int32m1_t28vint32m1_t baz(vint32m1_t input);29vint32m1_t test_no_vector_cc_attr(vint32m1_t input, int32_t *base, size_t vl) {30 vint32m1_t val = __riscv_vle32_v_i32m1(base, vl);31 vint32m1_t ret = baz(input);32 __riscv_vse32_v_i32m1(base, val, vl);33 return ret;34}35 36// CHECK-LLVM: define dso_local void @_Z14test_vls_no_ccDv4_i(i128 noundef %arg.coerce)37void test_vls_no_cc(__attribute__((vector_size(16))) int arg) {}38 39// CHECK-LLVM: define dso_local riscv_vls_cc(128) void @_Z25test_vls_default_abi_vlenDv4_i(<vscale x 2 x i32> noundef %arg.coerce)40[[riscv::vls_cc]] void test_vls_default_abi_vlen(__attribute__((vector_size(16))) int arg) {}41 42// CHECK-LLVM: define dso_local riscv_vls_cc(128) void @_Z45test_vls_default_abi_vlen_unsupported_featureDv8_DF16_(<vscale x 8 x i8> noundef %arg.coerce)43[[riscv::vls_cc]] void test_vls_default_abi_vlen_unsupported_feature(__attribute__((vector_size(16))) _Float16 arg) {}44 45// CHECK-LLVM-ZVE32X: define dso_local riscv_vls_cc(128) void @_Z52test_vls_default_abi_vlen_unsupported_feature_zve32xDv4_f(<vscale x 8 x i8> noundef %arg.coerce)46[[riscv::vls_cc]] void test_vls_default_abi_vlen_unsupported_feature_zve32x(__attribute__((vector_size(16))) float arg) {}47 48// CHECK-LLVM-ZVE32X: define dso_local riscv_vls_cc(128) void @_Z55test_vls_default_abi_vlen_unsupported_feature_no_zve64xDv2_m(<vscale x 8 x i8> noundef %arg.coerce)49[[riscv::vls_cc]] void test_vls_default_abi_vlen_unsupported_feature_no_zve64x(__attribute__((vector_size(16))) uint64_t arg) {}50 51// CHECK-LLVM: define dso_local riscv_vls_cc(256) void @_Z21test_vls_256_abi_vlenDv4_i(<vscale x 1 x i32> noundef %arg.coerce)52[[riscv::vls_cc(256)]] void test_vls_256_abi_vlen(__attribute__((vector_size(16))) int arg) {}53 54// CHECK-LLVM: define dso_local riscv_vls_cc(1024) void @_Z22test_vls_least_elementDv2_i(<vscale x 1 x i32> noundef %arg.coerce)55[[riscv::vls_cc(1024)]] void test_vls_least_element(__attribute__((vector_size(8))) int arg) {}56 57 58struct st_i32x4 {59 __attribute__((vector_size(16))) int i32;60};61 62struct st_i32x4_arr1 {63 __attribute__((vector_size(16))) int i32[1];64};65 66struct st_i32x4_arr4 {67 __attribute__((vector_size(16))) int i32[4];68};69 70struct st_i32x4_arr8 {71 __attribute__((vector_size(16))) int i32[8];72};73 74 75struct st_i32x4x2 {76 __attribute__((vector_size(16))) int i32_1;77 __attribute__((vector_size(16))) int i32_2;78};79 80struct st_i32x8x2 {81 __attribute__((vector_size(32))) int i32_1;82 __attribute__((vector_size(32))) int i32_2;83};84 85struct st_i32x64x2 {86 __attribute__((vector_size(256))) int i32_1;87 __attribute__((vector_size(256))) int i32_2;88};89 90struct st_i32x4x3 {91 __attribute__((vector_size(16))) int i32_1;92 __attribute__((vector_size(16))) int i32_2;93 __attribute__((vector_size(16))) int i32_3;94};95 96struct st_i32x4x8 {97 __attribute__((vector_size(16))) int i32_1;98 __attribute__((vector_size(16))) int i32_2;99 __attribute__((vector_size(16))) int i32_3;100 __attribute__((vector_size(16))) int i32_4;101 __attribute__((vector_size(16))) int i32_5;102 __attribute__((vector_size(16))) int i32_6;103 __attribute__((vector_size(16))) int i32_7;104 __attribute__((vector_size(16))) int i32_8;105};106 107struct st_i32x4x9 {108 __attribute__((vector_size(16))) int i32_1;109 __attribute__((vector_size(16))) int i32_2;110 __attribute__((vector_size(16))) int i32_3;111 __attribute__((vector_size(16))) int i32_4;112 __attribute__((vector_size(16))) int i32_5;113 __attribute__((vector_size(16))) int i32_6;114 __attribute__((vector_size(16))) int i32_7;115 __attribute__((vector_size(16))) int i32_8;116 __attribute__((vector_size(16))) int i32_9;117};118 119typedef int __attribute__((vector_size(256))) int32x64_t;120 121// CHECK-LLVM: define dso_local riscv_vls_cc(128) void @_Z14test_too_largeDv64_i(ptr dead_on_return noundef %0)122[[riscv::vls_cc]] void test_too_large(int32x64_t arg) {}123// CHECK-LLVM: define dso_local riscv_vls_cc(256) void @_Z18test_too_large_256Dv64_i(<vscale x 16 x i32> noundef %arg.coerce)124[[riscv::vls_cc(256)]] void test_too_large_256(int32x64_t arg) {}125 126// CHECK-LLVM: define dso_local riscv_vls_cc(128) void @_Z13test_st_i32x48st_i32x4(<vscale x 2 x i32> %arg.target_coerce)127[[riscv::vls_cc]] void test_st_i32x4(struct st_i32x4 arg) {}128// CHECK-LLVM: define dso_local riscv_vls_cc(256) void @_Z17test_st_i32x4_2568st_i32x4(<vscale x 1 x i32> %arg.target_coerce)129[[riscv::vls_cc(256)]] void test_st_i32x4_256(struct st_i32x4 arg) {}130 131// CHECK-LLVM: define dso_local riscv_vls_cc(128) void @_Z18test_st_i32x4_arr113st_i32x4_arr1(<vscale x 2 x i32> %arg.target_coerce)132[[riscv::vls_cc]] void test_st_i32x4_arr1(struct st_i32x4_arr1 arg) {}133// CHECK-LLVM: define dso_local riscv_vls_cc(256) void @_Z22test_st_i32x4_arr1_25613st_i32x4_arr1(<vscale x 1 x i32> %arg.target_coerce)134[[riscv::vls_cc(256)]] void test_st_i32x4_arr1_256(struct st_i32x4_arr1 arg) {}135 136// CHECK-LLVM: define dso_local riscv_vls_cc(128) void @_Z18test_st_i32x4_arr413st_i32x4_arr4(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %arg.target_coerce)137[[riscv::vls_cc]] void test_st_i32x4_arr4(struct st_i32x4_arr4 arg) {}138// CHECK-LLVM: define dso_local riscv_vls_cc(256) void @_Z22test_st_i32x4_arr4_25613st_i32x4_arr4(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %arg.target_coerce)139[[riscv::vls_cc(256)]] void test_st_i32x4_arr4_256(struct st_i32x4_arr4 arg) {}140 141// CHECK-LLVM: define dso_local riscv_vls_cc(128) void @_Z18test_st_i32x4_arr813st_i32x4_arr8(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %arg.target_coerce)142[[riscv::vls_cc]] void test_st_i32x4_arr8(struct st_i32x4_arr8 arg) {}143// CHECK-LLVM: define dso_local riscv_vls_cc(256) void @_Z22test_st_i32x4_arr8_25613st_i32x4_arr8(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %arg.target_coerce)144[[riscv::vls_cc(256)]] void test_st_i32x4_arr8_256(struct st_i32x4_arr8 arg) {}145 146// CHECK-LLVM: define dso_local riscv_vls_cc(128) void @_Z15test_st_i32x4x210st_i32x4x2(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %arg.target_coerce)147[[riscv::vls_cc]] void test_st_i32x4x2(struct st_i32x4x2 arg) {}148// CHECK-LLVM: define dso_local riscv_vls_cc(256) void @_Z19test_st_i32x4x2_25610st_i32x4x2(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %arg.target_coerce)149[[riscv::vls_cc(256)]] void test_st_i32x4x2_256(struct st_i32x4x2 arg) {}150 151// CHECK-LLVM: define dso_local riscv_vls_cc(128) void @_Z15test_st_i32x8x210st_i32x8x2(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %arg.target_coerce)152[[riscv::vls_cc]] void test_st_i32x8x2(struct st_i32x8x2 arg) {}153// CHECK-LLVM: define dso_local riscv_vls_cc(256) void @_Z19test_st_i32x8x2_25610st_i32x8x2(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %arg.target_coerce)154[[riscv::vls_cc(256)]] void test_st_i32x8x2_256(struct st_i32x8x2 arg) {}155 156// CHECK-LLVM: define dso_local riscv_vls_cc(128) void @_Z16test_st_i32x64x211st_i32x64x2(ptr dead_on_return noundef %arg)157[[riscv::vls_cc]] void test_st_i32x64x2(struct st_i32x64x2 arg) {}158// CHECK-LLVM: define dso_local riscv_vls_cc(256) void @_Z20test_st_i32x64x2_25611st_i32x64x2(ptr dead_on_return noundef %arg)159[[riscv::vls_cc(256)]] void test_st_i32x64x2_256(struct st_i32x64x2 arg) {}160 161// CHECK-LLVM: define dso_local riscv_vls_cc(128) void @_Z15test_st_i32x4x310st_i32x4x3(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %arg.target_coerce)162[[riscv::vls_cc]] void test_st_i32x4x3(struct st_i32x4x3 arg) {}163// CHECK-LLVM: define dso_local riscv_vls_cc(256) void @_Z19test_st_i32x4x3_25610st_i32x4x3(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %arg.target_coerce)164[[riscv::vls_cc(256)]] void test_st_i32x4x3_256(struct st_i32x4x3 arg) {}165 166// CHECK-LLVM: define dso_local riscv_vls_cc(128) void @_Z15test_st_i32x4x810st_i32x4x8(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %arg.target_coerce)167[[riscv::vls_cc]] void test_st_i32x4x8(struct st_i32x4x8 arg) {}168// CHECK-LLVM: define dso_local riscv_vls_cc(256) void @_Z19test_st_i32x4x8_25610st_i32x4x8(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %arg.target_coerce)169[[riscv::vls_cc(256)]] void test_st_i32x4x8_256(struct st_i32x4x8 arg) {}170 171// CHECK-LLVM: define dso_local riscv_vls_cc(128) void @_Z15test_st_i32x4x910st_i32x4x9(ptr dead_on_return noundef %arg)172[[riscv::vls_cc]] void test_st_i32x4x9(struct st_i32x4x9 arg) {}173// CHECK-LLVM: define dso_local riscv_vls_cc(256) void @_Z19test_st_i32x4x9_25610st_i32x4x9(ptr dead_on_return noundef %arg)174[[riscv::vls_cc(256)]] void test_st_i32x4x9_256(struct st_i32x4x9 arg) {}175