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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py2// RUN: %clang_cc1 -triple riscv32 -target-feature +zbc -emit-llvm %s -o - \3// RUN: -disable-O0-optnone | opt -S -passes=mem2reg \4// RUN: | FileCheck %s -check-prefix=RV32ZBC5// RUN: %clang_cc1 -triple riscv64 -target-feature +zbc -emit-llvm %s -o - \6// RUN: -disable-O0-optnone | opt -S -passes=mem2reg \7// RUN: | FileCheck %s -check-prefix=RV64ZBC8 9#include <riscv_bitmanip.h>10 11#if __riscv_xlen == 6412// RV64ZBC-LABEL: @clmul_64(13// RV64ZBC-NEXT: entry:14// RV64ZBC-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.clmul.i64(i64 [[A:%.*]], i64 [[B:%.*]])15// RV64ZBC-NEXT: ret i64 [[TMP0]]16//17uint64_t clmul_64(uint64_t a, uint64_t b) {18 return __riscv_clmul_64(a, b);19}20 21// RV64ZBC-LABEL: @clmulh_64(22// RV64ZBC-NEXT: entry:23// RV64ZBC-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.clmulh.i64(i64 [[A:%.*]], i64 [[B:%.*]])24// RV64ZBC-NEXT: ret i64 [[TMP0]]25//26uint64_t clmulh_64(uint64_t a, uint64_t b) {27 return __riscv_clmulh_64(a, b);28}29 30// RV64ZBC-LABEL: @clmulr_64(31// RV64ZBC-NEXT: entry:32// RV64ZBC-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.clmulr.i64(i64 [[A:%.*]], i64 [[B:%.*]])33// RV64ZBC-NEXT: ret i64 [[TMP0]]34//35uint64_t clmulr_64(uint64_t a, uint64_t b) {36 return __riscv_clmulr_64(a, b);37}38#endif39 40// RV32ZBC-LABEL: @clmul_32(41// RV32ZBC-NEXT: entry:42// RV32ZBC-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.clmul.i32(i32 [[A:%.*]], i32 [[B:%.*]])43// RV32ZBC-NEXT: ret i32 [[TMP0]]44//45// RV64ZBC-LABEL: @clmul_32(46// RV64ZBC-NEXT: entry:47// RV64ZBC-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.clmul.i32(i32 [[A:%.*]], i32 [[B:%.*]])48// RV64ZBC-NEXT: ret i32 [[TMP0]]49//50uint32_t clmul_32(uint32_t a, uint32_t b) {51 return __riscv_clmul_32(a, b);52}53 54#if __riscv_xlen == 3255// RV32ZBC-LABEL: @clmulh_32(56// RV32ZBC-NEXT: entry:57// RV32ZBC-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.clmulh.i32(i32 [[A:%.*]], i32 [[B:%.*]])58// RV32ZBC-NEXT: ret i32 [[TMP0]]59//60uint32_t clmulh_32(uint32_t a, uint32_t b) {61 return __riscv_clmulh_32(a, b);62}63 64// RV32ZBC-LABEL: @clmulr_32(65// RV32ZBC-NEXT: entry:66// RV32ZBC-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.clmulr.i32(i32 [[A:%.*]], i32 [[B:%.*]])67// RV32ZBC-NEXT: ret i32 [[TMP0]]68//69uint32_t clmulr_32(uint32_t a, uint32_t b) {70 return __riscv_clmulr_32(a, b);71}72#endif73